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Showing content with the highest reputation since 08/18/19 in Posts

  1. 1 point
    mmdsaifudn

    SREC SPI Bootloader is Very Slow

    @bhall Thanks a lot bhall for giving info.I got this elf bootloader working when I started from scratch.
  2. 1 point
    Peggy

    an easy way to read log file by MATLAB

    Hi everyone, I found an easy way to read .log file by MATLAB. MATLAB has functions to read binary file but the difficulty is that we are not sure about the header and format of the log data. I am not familiar with Python so the other way that posted by benl using Python is such a pain to me. Here are a few lines that can easily decode .log file with two channels of data: %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %% Read Data from OpenLogger file close all;clear;clc logfilename = '20190723_9_0.log'; finfo = dir(['F:\' logfilename]); channelNum = 2; %number of channels sampleNum = finfo.bytes/2/channelNum; fileID = fopen(logfilename); logdata = fread(fileID,[channelNum sampleNum],'int16=>int16'); fclose(fileID); headerNum=257; plot(logdata(1,headerNum+1:end),'-'),hold on %channel 1 plot(logdata(2,headerNum+1:end),'-'),hold off %channel 2 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% WaveForms Live read in Matlab Note: I don't care about the header info so I just get rid of it. I use random input pulses for ch2; The two plots are not from the same time. peggy
  3. 1 point
    Bianca

    Unable to download Adept 2

    Hi @Mahmood ul Hassan, I just tried and it works. You have to fill in the form and the download will start. Regards, Bianca
  4. 1 point
    Hi @m72 After adding the Order option in Logic Analyzer (splitting the Input selection in two) I have forgotten to update the Protocol/Logic Analyzer to set the Order option automatically. Thank you for the observation, it is fixed for the next release.
  5. 1 point
    Hi @GeorgeMina, Yes, you may attach one Pmod to the top row of the 2x6 header and the other Pmod to the bottom row of the 2x6 Pmod host port; you will need to use a cable of some kind though since the Pmods won't both physically fit on top of each other, but there is nothing electrically preventing you from doing this. I am not familiar with the Nebula board you mentioned, but you should be able to program it such that each Pmod is controlled separately. I don't know if there are any nuances with this particular board that you would have to consider (such as the Pmod port is only compatible with SPI Pmods). Thanks, JColvin
  6. 1 point
    Hi @m72 You have in private message a software version which changes a bit the digital timings. Please install this, reconnect the device to make sure it will get reconfigured and start the application. Let me know if this solves the issue. The scope inputs are rated for up to +/-50V, but it should survive higher voltages due the 820k series resistor before the 7.5-20mA protection. High voltages (with energy) usually damage the gain selector analog switch, which leads to DC reading. https://reference.digilentinc.com/reference/instrumentation/analog-discovery-2/reference-manual#scope_input_divider_and_gain_selection The attenuation option is intended to scale the scope readings, it is not a device feature. For instance when you use a 10x scope probe (9M series), the scope input will actually get 1/10 of voltage. Specifying 10x attenuation the software will multiply the readings by 10, to compensate this. You can also use this to reflect external voltage dividers, amplifiers... Edit: The calibration adjust the amplitude and offset.
  7. 1 point
    I would look on Analog Device's wiki. Also look for how to cross compile QT.
  8. 1 point
    zygot

    Using tera term for two pmods

    Well I think that this is better stated as saying that most serial terminal applications can only connect to one COM port at a time. It is possible to mave multiple UARTs in your FPGA design and connect to multiple serial terminal applications. I like Putty myself, but there are other options. Another possibility is to look around in the Digilent Project Vault and see at least 3 project with source code that might accomplish what you want to do. If you instantiate your own UART you can access any number of internal registers or memory.
  9. 1 point
    Hi @Lesiastas The rg0 will get its value after you step over the respective line, after the decode function is executed. Byte sampling: Module Module1 Function decodeUart(ByRef rgData() As Byte, ByVal cSamplePerBit As Integer, ByVal pin As Integer) As List(Of Byte) Dim pData As Boolean Dim fData As Boolean = False Dim cSamples = rgData.Length Dim rgUart As New List(Of Byte) For i As Integer = 0 To cSamples - 1 Dim s = rgData(i) pData = fData fData = 1 And (s >> pin) If pData <> 0 And fData = 0 Then Dim bValue As Integer = 0 For b = 0 To 7 Dim ii = Math.Round(i + (1.499 + b) * cSamplePerBit) ''''' If ii >= cSamples Then Exit For End If s = rgData(ii) fData = 1 And (s >> pin) If fData Then bValue += (1 << b) End If Next rgUart.Add(bValue) i += cSamplePerBit * 9.499 - 1 ''''' 1 start + 8 bits + 0.5 stop -1 because For will increment End If Next Return rgUart End Function Sub Main() Dim hdwf As Long If FDwfDeviceOpen(-1, hdwf) = False Then Dim szError As String FDwfGetLastErrorMsg(szError) System.Console.WriteLine("Device open failed" & vbCrLf & szError, vbExclamation + vbOKOnly) End End If Const hzUart = 9600 Const hzRate = hzUart * 1 ''''' Const cSamples = 1000 Dim hzDI As Double FDwfDigitalInInternalClockInfo(hdwf, hzDI) FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDetectorDigitalIn) FDwfDigitalInTriggerSet(hdwf, 0, 0, 0, &HFFFF) 'any falling edge 'FDwfDigitalInTriggerAutoTimeoutSet(hdwf, 10.0) FDwfDigitalInDividerSet(hdwf, hzDI / hzRate) FDwfDigitalInSampleFormatSet(hdwf, 8) FDwfDigitalInBufferSizeSet(hdwf, cSamples) FDwfDigitalInTriggerPositionSet(hdwf, cSamples - 10) FDwfDigitalInConfigure(hdwf, 1, 1) Dim sts As Byte While True If FDwfDigitalInStatus(hdwf, 1, sts) = 0 Then Return End If If sts = DwfStateDone Then Exit While End If End While FDwfDigitalInDividerGet(hdwf, hzRate) ' get the actual rate Const cSamplePerBit = hzRate / hzUart Dim rgData(cSamples) As Byte FDwfDigitalInStatusData(hdwf, rgData, 1 * rgData.Length) Call FDwfDeviceCloseAll() Dim rg0 = decodeUart(rgData, cSamplePerBit, 0) System.Console.Write("Hex 0: ") For i = 0 To rg0.Count - 1 System.Console.Write(" 0x" + Conversion.Hex(rg0(i))) Next System.Console.WriteLine() System.Console.WriteLine("Text 0: " + System.Text.Encoding.ASCII.GetString(rg0.ToArray)) End Sub End Module
  10. 1 point
    JColvin

    Impedance anlyzer

    Hi @spaske, Did you take a look at this tutorial that we have for the Analog Discovery 2 here, https://reference.digilentinc.com/learn/instrumentation/tutorials/ad2-impedance-analyzer/start? Thanks, JColvin
  11. 1 point
    Hi @Lesiastas Added to the previous post the following to prevent such exception: If ii >= cSamples Then Exit For End If I'm not sure what you mean by 'enable DIOs'... The Digital-In functions are not enabling any kind of output on DIOs. Internally for AD2 the digital-in always samples at 16bits, just the FDwfDigitalInStatusData format changes: 8, 16 or 32 bits. If you want you can use 8 bit data you can do with the following changes: ... Function decodeUart(ByRef rgData() As Byte, .... ... FDwfDigitalInSampleFormatSet(hdwf, 8) ... Dim rgData(cSamples) As Byte FDwfDigitalInStatusDataUShort(hdwf, rgData, rgData.Length) ...
  12. 1 point
    Hi @Lesiastas You should use higher sample rate to capture raw data than the UART rate. Otherwise due to clock jitter and signal slew rate the capture could be wrong. Imagine on sample could be captured exactly on bit start and next bit on the end of the same bit, instead of next bit start... Anyway, here I have modified the decodeUart to work with sample rate = uart rate, see the lines marked with ' ' ' ' Module Module1 Function decodeUart(ByRef rgData() As UShort, ByVal cSamplePerBit As Integer, ByVal pin As Integer) As List(Of Byte) Dim pData As Boolean Dim fData As Boolean = False Dim cSamples = rgData.Length Dim rgUart As New List(Of Byte) For i As Integer = 0 To cSamples - 1 Dim s = rgData(i) pData = fData fData = 1 And (s >> pin) If pData <> 0 And fData = 0 Then Dim bValue As Integer = 0 For b = 0 To 7 Dim ii = Math.Round(i + (1.499 + b) * cSamplePerBit) ''''' If ii >= cSamples Then Exit For End If s = rgData(ii) fData = 1 And (s >> pin) If fData Then bValue += (1 << b) End If Next rgUart.Add(bValue) i += cSamplePerBit * 9.499 - 1 ''''' 1 start + 8 bits + 0.5 stop -1 because For will increment End If Next Return rgUart End Function Sub Main() Dim hdwf As Long If FDwfDeviceOpen(-1, hdwf) = False Then Dim szError As String FDwfGetLastErrorMsg(szError) System.Console.WriteLine("Device open failed" & vbCrLf & szError, vbExclamation + vbOKOnly) End End If Const hzUart = 9600 Const hzRate = hzUart * 3 ''''' Const cSamples = 1000 Dim hzDI As Double FDwfDigitalInInternalClockInfo(hdwf, hzDI) FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDetectorDigitalIn) FDwfDigitalInTriggerSet(hdwf, 0, 0, 0, &HFFFF) 'any falling edge 'FDwfDigitalInTriggerAutoTimeoutSet(hdwf, 10.0) FDwfDigitalInDividerSet(hdwf, hzDI / hzRate) FDwfDigitalInSampleFormatSet(hdwf, 16) FDwfDigitalInBufferSizeSet(hdwf, cSamples) FDwfDigitalInTriggerPositionSet(hdwf, cSamples - 10) FDwfDigitalInConfigure(hdwf, 1, 1) Dim sts As Byte While True If FDwfDigitalInStatus(hdwf, 1, sts) = 0 Then Return End If If sts = DwfStateDone Then Exit While End If End While FDwfDigitalInDividerGet(hdwf, hzRate) ' get the actual rate Const cSamplePerBit = hzRate / hzUart Dim rgData(cSamples) As UInt16 FDwfDigitalInStatusDataUShort(hdwf, rgData, 2 * rgData.Length) Call FDwfDeviceCloseAll() Dim rg0 = decodeUart(rgData, cSamplePerBit, 0) System.Console.Write("Hex 0: ") For i = 0 To rg0.Count - 1 System.Console.Write(" 0x" + Conversion.Hex(rg0(i))) Next System.Console.WriteLine() System.Console.WriteLine("Text 0: " + System.Text.Encoding.ASCII.GetString(rg0.ToArray)) End Sub End Module
  13. 1 point
    hamster

    Analog Discovery 2 vs Raspberry Pi 3

    Hi. I've replaced my Cubieboard with a Raspberry Pi 3, and it runs the ARM version of Waveforms really well. With an Electronics Explorer everything works sweet. With the AD2, it complains about supply and/or AUX voltage, even with a 5V 3A power pack attached (The power supply panel indicates that the AUX supply is present so I know it is working well). The USB voltage usually shows as 4.92V at a few 10s of mAs I've tried with 2.5A USB PSU => Pi3 => Powered Hub => AD2, as well as 2.5A USB PSU => Pi3 => AD2. I also get a "unsufficent power". I've tried a few different USB cables too. The USB 2.0 spec, according to Wikipedia is 5V +/- 0.25V, so anything above 4.75V should be possible. Is there any hints? If I wanted to make a USB dummy load and test the voltage drop, what specs should I be checking for?
  14. 1 point
    Cristian.Fatu

    tera term for two pmods

    Hello, The PmodAD2 communicates over I2C protocol with the main board on which the Pmod is plugged. The PmodAD2 has no UART / USB capabilities. It is the main board that communicates - using its USB-UART capability - with the PC. Connecting the board using a USB cable creates a COM port on the PC. When you open a TeraTerm (or other terminal) connection, you select the COM port. Therefore a possible approach could be to have 2 PmodAD2 connected to a single main board, in different Pmod connectors. The SDK application should gather the AD2 data (measurements), format a text message containing these measurements, and then sending the text message over UART to the PC, to be later visualized in a terminal. What application are you running on the FPGA board ? You should modify it to read the other Pmod as well.
  15. 1 point
    Hi @m72 The 24 refers to the digital input lines.
  16. 1 point
    Bianca

    Pmod OLEDrgb thickness?

    Hi @BradLevy, We don't have a 3D drawind for the Pmod OLEDrgb but i measured it and it was 4.45 mm (~0.175") in thickness. And from the attached picture you can see that it's not higher than the Pmod Connetor. I hope this helps. Regards, Bianca
  17. 1 point
    Hi @m72 The 1kHz is generated from the 100MHz system clock with 50% duty. The 1.1kHz is actually generated as 1.099989kHz with 49.9945% duty. Due to this the 180* phase, the middle falls in low level which gets used as initial value. For the next release I have modified the duty to round up, so the 1.1kHz will have 50.005499945% duty and the 180* phase will start high. I'm also adding negative delay for the next version. Thank you for the observation. Current version: Next version:
  18. 1 point
    Hi @JXS, The bests solution that I can offer would be to use a different/better quality usb cable; there is a collection of other threads on this particular topic with the Cmod A7 on this thread here: Thanks, JColvin
  19. 1 point
    Hi @Lesiastas The Logic Analyzer interface captures raw time domain samples and decodes the protocol in software, like it is in the above example. The Protocol tool is similar to the FdwfDigitalUart/Spi/I2c operation. The encoding/decoding takes place in the device, storing only the relevant samples for the protocol, like on SPI clock rising or falling edge, or detects UART starts and stores the required ~9 samples-bits. In the above example you can decode multiple UART lines from the same captured data, like: Dim rg0 = decodeUart(rgData, cSamplePerBit, 0) 'DIO-0 Dim rg1 = decodeUart(rgData, cSamplePerBit, 1) 'DIO-1 Dim rg2 = decodeUart(rgData, cSamplePerBit, 2) 'DIO-2 ... The cSamplePerBit should be Double.
  20. 1 point
    Hi @Lesiastas For the VB and C# wrappers I have added digital-in-data function variants with byte, short, integer data types. See SDK/ samples/ vb/ dwf.vb https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ Here you have a VB UART decoder example: vb.zip To decode from other lines add, like: decodeUart(rgData, cSamplePerBit, 2) 'DIO-2 Module Module1 Function decodeUart(ByRef rgData() As UShort, ByVal cSamplePerBit As [-Integer-] Double, ByVal pin As Integer) As List(Of Byte) Dim pData As Boolean Dim fData As Boolean = False Dim cSamples = rgData.Length Dim rgUart As New List(Of Byte) For i As Integer = 0 To cSamples - 1 Dim s = rgData(i) pData = fData fData = 1 And (s >> pin) If pData <> 0 And fData = 0 Then Dim bValue As Integer = 0 For b = 0 To 7 Dim ii = Math.Round(i + (1.5 + b) * cSamplePerBit) s = rgData(ii) fData = 1 And (s >> pin) If fData Then bValue += (1 << b) End If Next rgUart.Add(bValue) i += cSamplePerBit * 9.5 ' 1 start + 8 bits + 0.5 stop End If Next Return rgUart End Function Sub Main() Dim hdwf As Long If FDwfDeviceOpen(-1, hdwf) = False Then Dim szError As String FDwfGetLastErrorMsg(szError) System.Console.WriteLine("Device open failed" & vbCrLf & szError, vbExclamation + vbOKOnly) End End If Const hzUart = 9600 Const hzRate = hzUart * 10 Const cSamples = 1000 Dim hzDI As Double FDwfDigitalInInternalClockInfo(hdwf, hzDI) FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDetectorDigitalIn) FDwfDigitalInTriggerSet(hdwf, 0, 0, 0, &HFFFF) 'any falling edge 'FDwfDigitalInTriggerAutoTimeoutSet(hdwf, 10.0) FDwfDigitalInDividerSet(hdwf, hzDI / hzRate) FDwfDigitalInSampleFormatSet(hdwf, 16) FDwfDigitalInBufferSizeSet(hdwf, cSamples) FDwfDigitalInTriggerPositionSet(hdwf, cSamples - 10) FDwfDigitalInConfigure(hdwf, 1, 1) Dim sts As Byte While True If FDwfDigitalInStatus(hdwf, 1, sts) = 0 Then Return End If If sts = DwfStateDone Then Exit While End If End While FDwfDigitalInDividerGet(hdwf, hzRate) ' get the actual rate Const cSamplePerBit = hzRate / hzUart Dim rgData(cSamples) As UInt16 FDwfDigitalInStatusDataUShort(hdwf, rgData, 2 * rgData.Length) Call FDwfDeviceCloseAll() Dim rg0 = decodeUart(rgData, cSamplePerBit, 0) System.Console.Write("Hex 0: ") For i = 0 To rg0.Count - 1 System.Console.Write(" 0x" + Conversion.Hex(rg0(i))) Next System.Console.WriteLine() System.Console.WriteLine("Text 0:" + System.Text.Encoding.ASCII.GetString(rg0.ToArray)) End Sub End Module
  21. 1 point
    Hi @m72 The preview is further fixed. I hope there are no more issues with this: https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ Here you have the project: EMU_2CH_EACH_V10 (2).dwf3work
  22. 1 point
    The frequency fine tuning actually worked quite nicely. Thanks again! I measured the temporal drift with respect to a Stanford Signal Generator (SG384). In the 1 to 100 kHz range, the relative mismatch of the clocks was about 1e-6 (i.e. 1 kHz on the DD was about 0.99988 kHz on the SG). In the MHz regime (actually, 5.204 MHz), we could then see phase instabilities with transient drifts of about one 192 ns cycle over a few seconds to minutes. For the actual experiment, this was of no importance, since the setup was re-triggered at 1 kHz. We could see, however, that the "wait time" between the trigger of the logic analyzer and the pattern generator introduces a relative jitter of about 1e-3. To circumvent, we installed an external Delay Generator (DG584) to "jump" over 200 ยตs, and used the DD to generate the desired pulse patterns (to then gate a detector). We will certainly make much more use of this device in the future
  23. 1 point
    Hi @m72 The pulse preview is not correct. I will look into this. Thank you for the observations. You could use a custom bus or signals to easily create/modify such patterns.
  24. 1 point
    Hi @Lesiastas You should implement in python UART decoder. You can find a java script example in the Logic Analyzer Custom:
  25. 1 point
    Hi @m72 I have fixed the "pit top" for next version. I was unable to reproduce the crash. If you add multiple interpreters (Bus,I2C,SPI,UART...) it will use more memory and process the capture slower... The DD ram is 4Gbit (256MB). With 8 bit sampling (input: 800MHz x8) you can capture in ram 256M samples, with 16 bit (400MHz x16) 128M, with 32 bit (100-200MHz x32) 64M (67108864). At lower rate you can capture up to 100Mi samples. In this case the data is streamed over USB, which could lead to sample lost due to congestion.
  26. 1 point
    artvvb

    "#include "sleep.h"" error

    Hi @johnsan1 Microblaze does not support sleep.h in some older versions of Vivado. A nearly equivalent set of functions can be found in microblaze_sleep.h, though it may not include microsecond sleeps. Thanks, Arthur
  27. 1 point
    KeithRussell

    I think it's broken

    I ordered an ADG612 on Monday from Mouser and it came yesterday. I put in the new part, ran the calibration, and everything works great. Thanks for the help, Attila.
  28. 1 point
    Hi @Allmoz, We're not able to provide the schematics for the USB connectivity on the Basys 3, though there is a thread detailing what sort USB port would be needed here, though I personally have never been able to find a part that matches the dimensions. If some of the USB connectors do not have the traces ripped off, there is a possibility that you could solder the connector directly back onto the board, though there's no guarantee that'll work. Some of the connectors could still be okay; I have seen some boards come get returned where the user had plugged in the micro-USB cable upside down in the connector, but after carefully bending the connector back to the correct orientation (I used a small flathead screwdriver), I was able to plug a cable back in and have the board work with no issues. As for the switches, contact cleaner or compressed air would be what I would suggest to clean them. It is possible to remove the top half of the switch from the bottom half (since it's held on by four small tabs) to get easy access to the conductor to clean off the dirt or any sort of corrosion, though I don't know how easy it would be to get those tabs secured back into place (I would guess that it is not so easy). The part we specifically used for the Basys 3 is here, though apparently it's not stocked any more, but since it is a straightforward SPDT switch, any switch that has 4 mm of space between the centers of each of the through hole pins would work as a replacement. Let me know if you have any questions. Thanks, JColvin
  29. 1 point
    D@n

    Basys 3 implemented design

    @Chirag, What you are looking at is an image of the underlying silicon die within the chip, showing the layout of the various parts physically. The six big squares are clock regions IIRC. You can save some power and some wires if you can restrict a clock to a given region. That said, I tend to run all my designs with one giant system clock, so this hasn't helped me much. In your example above, the LUTs being used are in the middle row and colored light blue. There's more there than just LUTs, but that's where the LUTs are. What more is there? I can't be certain, but examples might be memory and DSP slices. If you zoom in on this area you'll see sub-pictures showing four LUTs to a slice, the FFs in the slice, and possibly the various mux-7 and mux-8 components as well. (It's been a while since I've done so) The I/O banks are all on the edges of the design. You can use them via the various IBUF, OBUF, IOBUF, IDDR, ODDR, ISERDESE, OSERDESE, etc. primitives. A wire going to or from an I/O port will naturally use one of these, or they can be manually instantiated as well for more control of what takes place. Yes, you can change cell locations manually, but knowing what you are doing enough to be successful doing so can be a real challenge. I know some folks who have hand placed their designs to great effect. I also know of at least one open source project to do the same. Indeed, at one time I tried to build a placer to map logic to FPGA elements--my efforts didn't work out so well. That said, I know my own limits and don't try to move components around myself. Dan
  30. 1 point
    Hi @johnsan1, I believe this documentation will help you make a log file in tera term. best regards, Jon
  31. 1 point
    Hi @m72 Thank you for the observation and sorry for this. It is fixed in the latest version: https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ I just notice that certain frequencies cause PLL not locked error. In this case select "Force Programming". I have to look exactly what synthesizer settings or PLL reset sequences lead to such problems.
  32. 1 point
    Hi @LukeChen The 480MHz is the USB 2.0 frequency, which uses some of this for sync and other usb protocol transfers, control... The maximum USB bulk IN bandwidth is about 40MBps, 370Mbps for large data transfers. In the AD2 the bandwidth is shared between various instruments, so the record is performed in small chunks which reduces the rate to about 1-2MHz
  33. 1 point
    artvvb

    Accessing GPIO through PS

    Hi @HasanWAVE Pin 14 won't work with the Arty Z7, as it corresponds to MIO 14, which is connected to the UART on the Arty Z7, rather than a button or switch. The Arty Z7 doesn't have any switches/buttons/LEDs connected to the Zynq's MIO pins. This means that to use the PS GPIO, you need to enable GPIO EMIO (extended MIO), which routes its signals through the PL. This allows you to connect and constrain the EMIO GPIO pins as you would any other GPIO interface in the IP Integrator. Unfortunately the EMIO can't be connected to the components in the board files, however, you can still make the EMIO GPIO bus external and constrain its pins with an XDC file. The EMIO GPIO is enabled through the Peripheral I/O Pins screen when re-customizing the Zynq block. You can then set the width of the bus through the MIO Configuration screen, under I/O Peripherals / GPIO. For SDK, the xgpiops pin numbers associated with the EMIO pins are assigned in ascending order above all of the MIO pin numbers - so, in the case of having only an EMIO GPIO interface with a width of 4, the pin numbers are 54, 55, 56, and 57. Note that the first 32 EMIO pins use the bank number 2, and that the way that the interrupt example creates the interrupt enable bit mask passed to XGpioPs_IntrEnable doesn't work with pin numbers greater than 31. I've attached a modified version of xgpiops_intr_example.c in the spoiler below that works with button 0 of the 4-button GPIO EMIO as described above. If you want more depth, there's some more information and references to Xilinx documentation in this thread from the Xilinx forums. Thanks for the question! -Arthur
  34. 1 point
    Hi @attila, Wow! That is really great, thanks a lot. We will directly use this on Tuesday and I will thank you with some photos and figures Best, osti
  35. 1 point
    jpeyron

    Using USB 2.0 on Cora Z7 board

    Hi @RFtmi, Welcome to the Digilent Forums! Are you referring to using the USB OTG and the USB 2.0 On-The-Go IP? Or the USB UART Bridge and the uartlite and the uart16550? I'm not aware of a free IP Core that facilitates using the USB OTG without linux. The USB UART Bridge is accessible through the ZYNQ Processor. Here is an Cora-Z7-10 XADC project that uses the USB UART Bridge which can be used through the Webpack edition of the Vivado. best regards, Jon
  36. 1 point
    Bianca

    JTAG-HS2 firmware erased by accident

    Hi @Chouchene, You have a private message. Regards, Bianca
  37. 1 point
    attila

    Analog Discovery Studio MATLAB add-on

    Hi @Erkang The Analog Discovery Studio should be supported by MatLab 2018a. The ADS has identical device ID to AD2, only the device variant is different. https://www.mathworks.com/hardware-support/digilent-analog-discovery.html The DAQ toolbox support package filters the devices based on ID. That is why MatLab 2013a supported only the AD(1). In 2018a AD2 was added. I don't think MatLab support looks for variant ID, so it should work with ADS too. See related post:
  38. 1 point
    Hi @osti 1. The Sync mode on Digital Discovery uses re-sampling at 1.25ns (800MHz) resolution. This uses the device triggering mechanism, so when using Sync mode the trigger options are not available. 2. At the moment only 100MHz base frequency is supported. I'm planning to add option to be able to fine adjust this frequency, like: 50.00836820083682, 50.00985221674877, 50.01197604790419, ... 98.86567164179104, 98.87323943661971, 98.88, ... ,99.97714285714285, 100 MHz
  39. 1 point
    tom21091

    DMC60c Default Settings

    Default Device ID is 0, Current limit is disabled, continuous current limit 40A, peak current limit is 60A, current duration is 500ms. There is no voltage limit? All parameters and their defaults can be found in the DMC60C CAN Protocol Guide.
  40. 1 point
    Azzor

    Vivado sysnthesis fail..Pcam

    A new monitor solved the problem. Resolution problem. Thanks for your help! i now can practice on the Zybo!
  41. 1 point
    D@n

    Amplitude modulation with DDS generator

    @chaitusvk, I notice that the on and off periods are ... not on an obvious integer spacing. Is there some greatest common sublength that all of the bits are described with? Is the carrier a multiple of this subwidth? Your goal is to create this signal, right? I think my goal would follow @xc6lx45's approach: create some form of NCO for the carrier, and then use multiples of it (if possible) for handling bit periods. You might find this article, or even this one, valuable back-reading on the topic. Dan
  42. 1 point
    Actually, I'm not sure what Diglent's policy is about questions that aren't specific to Xilinx or Digilent products. The various FPGA vendors are certainly competitors but I have a hard time seeing non-commercial customers as 'competitors' regardless of which vendors' products they are using. I would agree that, even though some of the people who respond to questions posted to Digilent's Forum have recent experience with a variety of FPGA vendor's devices and tools, posting questions to a website dedicated to Xilinx based products when your question is specific to Intel is a good way to get bad information and probably unwise. Also, and this hasn't happened yet, I suspect that having a lot of questions about non-Xilinx devices and tools would be confusing to a lot of readers and make the experience for many of them of reading posts to Digilent's forum less useful. Intel has a community forum as does Xilinx. Neither is, in my experience, as helpful as Digilent's most of the time. Intel is, well not Altera, and even Altera's community support wasn't that great. Digilent's Forum is a great place to ask about Digilent products and Xilinx tools. Even restricted to that it' must be hard for people to find answers that have already been posted because a a lot of questions keep getting repeated. I do heartily suggest that it would be more appropriate to seek out answers to questions like saif1's at forums where people who hang out there are very knowledgeable about the tools and devices for the platform that you are working on. There also must be vendor agnostic forums out there somewhere dealing with FPGA development tools and devices. My last word is that an awful lot of questions would be answered if the poster only took the time to read through the vendors' literature. If there's any practice that's bad form it's wasting other peoples time because you can't be bothered or don't have the time to read readily available literature. Everyone's time is as important to them as yours is to you.
  43. 1 point
    @saif91, In general, it's bad practice and frowned upon to ask a question about a product in their competitors forum. Hex file generation is pretty easy. You can see a discussion of how to do it in lesson 8 of my tutorial, the lesson on memory. You may struggle to build a big enough memory on-chip to hold such an image, though. If you are writing NiOS code, you might find it easier to create a C-array containing the image into your C code. Otherwise, you might wish to consider writing it to your flash yourself, and then copying it to whatever video memory you might have available to you: SDRAM, DDR3 SDRAM, SRAM, etc. Dan
  44. 1 point
    Hi @alien18331, Welcome to the Digilent Forum! I would suggest to use/install the Digilent board file. The board files become the default setting when running block automation. After running block automation connect m_axi_gp0_aclk pin to the fclk_clk0 pin. I have attached screen shots of the process for getting the hello world project working. best regards, Jon
  45. 1 point
    NotMyCupOfTea

    Using Pmod DA3 on a Zybo Z7

    Hi everyone, After having succesfully managed to use de XADC of the Zybo Z7010 board as explained in this post, I am now trying to use a DAC Pmod (reference and documentation here). After having checked the documentation, I have tried to write the SPI connection to the DAC (please find the verilog file and simulation in the attached files). Note, that I have decided to set the l_dac signal to 0 to enable continuous output to an oscilloscope. The simulation seems to run well to me and to be in accordance with the documentation, however, the result is not satisfactory. Indeed, the signal I want to output is on 16-bits and the command "output = 16'b1111111111111111", which should give the max value does not reach it. Besides, when I ask to "output = 16'b1000000000000000", which should give half of the max signal, the output is almost zero. Finally, please find in the attached files the image I get on an oscilloscope when I input a sine signal with 0.5V offset and 1Vpp. Does aybody see what I am missing ? Don't hesitate to ask more details if needed. Thank you in advance, DAC_wiz_0.v DAC_wiz_0.sim
  46. 1 point
    Hi @Lesiastas In the SDK the digital-in functions provides raw data, this needs to be interpreted in the custom application or script. See the SDK/ samples/ py/ DigitalIn_Spi_Spy.py An example UART interpreter can be found in the WF application/ Logic Analyzer/ Custom
  47. 1 point
    Thanks for the update @JColvin; obviously not what we'd like to hear in so far as lack of resources behind the product but the communications is appreciated. TBH, the dlog-utils code is... not great. The majority of the code is in type conversion and formatting (i.e. not germane to the actual processing of the data); I'm not surprised to hear it's problematic in updating it for OpenLogger as hard-coded assumptions on the data header abound (e.g. endianness; I presume the author is banking on that never changing, which may well be the case but it is in the format spec). As a reference implementation it hides the important data structure information in amongst language-specific type gymnastics. In contrast the Kaitai Struct approach removes all of that, and puts the data format front and centre, is trivially extensible (you update the struct definition and rebuild the library, done), and works "everywhere". If it were my decision I'd dump the current dlog-utils and start again based on Kaitai Struct, the result would be: a proper definition of the data format (rather than users having to reverse engineer the cpp code and troll the forums) a couple of dozen of lines of code for the reference Digilent implementation and most importantly would be useful/portable in any language/environment that Kaitai Struct supports (C++/STL, C#, Go, Java, JavaScript, Lua, Perl, PHP, Python, Ruby) As an example, what is implemented in nearly 180 LOC dlog-utils.cpp is under a dozen lines in the dlog-utils-portable Python example (`dlog = Dlog.from_file(args.inputfile)` followed by a `write_csv`), with far greater flexibility in terms of handling future variations on data formats, and better output formatting ๐Ÿ™‚ Given that Digilent have very limited resources for this project it's important they're used wisely, switching to Kaitai Struct is easily the best bang for buck we can ask for. (BTW, it might sound like I'm a shill for Kaitai Struct - nope, I'm just a satisfied user and first discovered it when writing dlog-utils-portable... I once wrote code to process structured binary data in the same way as dlog-utils, but I've now seen the light ๐Ÿ™‚
  48. 1 point
    Hi @sgrobler, The short answer is we are working on it (much like the statement has been for the last few months). The problem at hand is that engineers most familiar with the OpenLogger have retired, changed jobs, or been told from on high to focus on a different project at Digilent, leaving the project to others who are unfamiliar with the firmware and already have full days with their own Digilent tasks. As a small bit of good news, the engineers more familiar with the firmware are finally getting some more time to help out with the OpenLogger material (rather than something else) and so have been able to help provide some feedback on getting this necessary feature working. Bad news is that change hasn't fully happened yet. Other short answer of what needs done: Modify the parseFileHeader function in the dlog-utils.cpp to recognize when a file header that matches the OpenLogger style shown in the OpenLogger.h so that it supports both OpenScope MZ and OpenLogger Modify the convertToCsv function in the dlog-utils.cpp to also supports the OpenLogger with it's own set of timestamp, values, and units for an arbitrary amount of channels (and which channels) that are being sampled. Because of the multiple channels and the continuous logging nature, each conversion will probably need to be "chunked" out so that less powerful computers don't run into memory problems. Hopefully this gives some insight on the state of things. Thanks, JColvin P.S. - for my part on the OpenLogger project, I mostly just created and populated a number of the pages on the Digilent reference site, in case you were curious P.P.S. -- @benl, the channel map should be working as you suspect, but clearly this is a bug that hasn't been resolved yet. I'm not familiar enough with the OpenLogger code to know where to look for the error though.
  49. 1 point
    jpeyron

    Arty Z7-20 Serial Com

    Hi @MVS, The usb uart is directly connected to the PS of the Zynq Processor. You will need to use the PS to communicate through the usb uart. The Getting Started with the Vivado IP Integrator tutorial uses the Zynq processor and sends messages through the usb uart that can be read using a serial terminal like tera term. A good reference for using the Zynq processor is the Zynq Book here. thank you, Jon
  50. 1 point
    artvvb

    Generating project failed

    @kriob The TMDS interface can be found in the HDMI project's /repo/vivado-library/if subdirectory, the IP repository is supposed to be added when create_project is run, but this appears to be a difference between 2016.4 and 2017.2. You can add IP repositories manually through the project settings dialog, if 2017.2 has kept this dialog consistent, then you can go into the IP pane and select Repository Manager. As for the launch runs error, you will also need to manually create an HDL wrapper for the block design. In the sources tab, right click on the block design and select "Create HDL Wrapper". EDIT: Whoops, mistook the two of you... I will be releasing a fixed version of the project on Github within the next few hours... Hope this helps, Arthur