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Showing content with the highest reputation since 03/22/19 in Posts

  1. 2 points

    Read from MicroSD in HDL, Write on PC

    Hi @dcc, I'm not certain how you are verifying that the HDL is writing to and then reading back from the SD card in a normal formatting style, but in general FAT32 is a widely used format for SD cards that has existing material for it. I am uncertain why you are using a special tool to write to the SD card though; from what I can tell the tool is Windows compatible, so why not just use the Notepad program which comes with Windows and save a .txt file with the data you are interested in reading to the SD card or just using Windows Explorer (the file manager) to move the file of interest onto the SD card? If you do have a header in your file, you will need to take account for that, though I do not know what you mean by "random file" in this case. Thanks, JColvin
  2. 2 points

    Genesys 2 DDR Constraints

    Hi JColvin, I am definitely not using ISE. I think JPeyron had it correctly. I didn't have my board.Repopaths variable set and so the project wasn't finding the board files. Once I set this variable as suggested, the pin mapping and IO types were auto populated as expected. Kudos, Sean
  3. 2 points
    @jpeyron @D@n I fixed the bug in my SPI Flash controller design. Now I can read from Flash memory.
  4. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  5. 1 point
    well, by default your signal is between 0 V and Vref. The opamp circuit has a gain of 2 (range 0.. 2 VRef) but subtracts a constant VRef (range now -VRef..Vref). It'll just shift the waveform on the scope, and double its AC magnitude.
  6. 1 point
    @askhunter Tip if you want to notify someone that you are responding to a post type @and the first few letters of their username. A selection of usernames will appear in a popup window to choose from. If you just type @ and the whole name you won't get the desired result. I confess that I'm not an expert on using the features of this site but I did figure out this one. As to understanding all of the Xilinx documentation what yo are doing is correct. Speed-read though a document to get a general sense of what's being presented and don't worry about the things that you don't grasp. Just being familiar with what information is where will help with a specific question later. The DSP48E is a very complicated piece of hardware. You only understand how complicated by trying to instantiate it as a UNISIM component to implement a particular algorithm. I've done this and it take time. You understand by doing; one step at a time. In your case I'm assuming that you are starting with someone else's code and trying to modify it. This approach takes a difficult task and turns it into an extremely difficult task. [edit] Vivado uses the multipliers in a seamless way when you specify a multiply in your HDL code. It takes care of a lot of little details, such as that the multipliers are signed 18-bit. There are a LOT of options with the DSP48E blocks. Once you start making decisions for Vivado, by say, using the use_dsp attribute in your code you are taking on responsibility for more of those details... so you had better understand how the DSP48E blocks work. Trust me, even after you have figured out all of the necessary behaviors of the DSP48E blocks it doesn't get easier as you will have to contend with routing issues that might dramatically reduce your data rates. This is a general rule for using FPGA device resources. You can use the IP wizards to help construct a component that's useful for your needs or do it yourself in HDL code and assume the responsibility for getting all of the details and constraints right.
  7. 1 point

    Pmod IA AD5933 measurement speed

    Hi @M.Mahdi.T, Welcome to the Digilent Forums! We typically do not test the max throughput metric when validating our products. Looking at the AD5933 datasheet here the Pmod IA would be limited to 1 MSPS due to the on board ADC. The main bottleneck for throughput to a host board will be the I2C communication which runs at 400 KHz. Here is a good forum thread for using the Pmod IA with the Raspberry PI with code and hints for use , setup and calibration. Here is the resource center for the Pmod IA which has the Raspberry PI code as well. best regards, Jon
  8. 1 point

    CMOD A7 Schematic missing stuff

    Thank you Jon... I got the PM and will follow up as you suggested.
  9. 1 point

    OpenCV and Pcam5-c

    Hi @Esti.A, SDx, which includes SDSoC (Software Defined System on Chip), is a development environment that allows you to develop a computer vision application, in your case, using C/C++ and OpenCV library. The target of SDx-built applications are Xilinx systems on chip (SoC) (Zynq-7000 or Zynq Ultrascale+). Xilinx SoC architecture has two main components: ARM processor (single or multi core) named Processing System (PS) and FPGA, named Programmable Logic (PL). Using SDx to build an application for SoC allows you to choose which functions from your algorithm are executed in PS and which ones are executed in PL. SDx will generate all data movers and dependencies that you need to move data between PS, DDR memory and PL. The PL is suitable for operations that can be easily executed in parallel. So if you are going to choose a median filter function to be executed in PL, instead of PS, you will obtain a better throughput from your system. As you said, you can use OpenCV to develop your application. You have to take into account that OpenCV library was developed with CPU architecture in mind. So the library was designed to obtain the best performance on some specific CPU architectures (x86-64, ARM, etc.). If you are trying to accelerate an OpenCV function in PL using SDx you will obtain a poor performance. To overcome this issue, Xilinx has developed xfopencv, which is a subset if OpenCV library functions. The functionalities of xfopecv functions and OpenCV functions are the same but the xfopencv functions are implemented having FPGA architecture in mind. xfopencv was developed in C/C++ following some coding guideline. When you are building a project, the C/C++ code is given as input to Xilinx HLS (High Level Synthesis) tool that will convert it to HDL (Hardware Description Language) that will be synthetized for FPGA. The above mentioned coding guideline provides information about how to write C/C++ code that will be implemented efficiently in FPGA. To have a better understanding on xfopencv consult this documentation. So SDx helps you to obtain a better performance by offloading PS and by taking advantage of parallel execution capabilities of PL. Have a look on SDSoC documentation. For more details check this. An SoC is a complex system composed by a Zynq (ARM + FPGA), DDR memory and many types of peripherals. Above those, one can run a Linux distribution (usually Petalinux, from Xilinx) and above the Linux distribution, the user application will run. The user application may access the DDR memory and different types of peripherals (PCam in your case). Also, it may accelerate some functions in FPGA to obtain a better performance. To simplify the development pipeline Xilinx provides an abstract way to interact with, named SDSoC platform. SDSoC platform has two components: Software Component and Hardware Component that describes the system from the hardware to the operating system. Your application will interact with this platform. You are not supposed to know all details about this platform. This was the idea, to abstract things. Usually, the SDSoC platforms are provided by the SoC development boards providers, like Digilent. All you have to do is to download the last SDSoC platform release from github. You have to use SDx 2017.4. You don't have to build your own SDSoC platform. This is a complex task. You can follow these steps in order to build your first project that will use PCam and Zybo Z7 board. The interaction between PCam and the user application is done in the following way: there is an IP in FPGA that acquires live video stream from the camera, the video stream is written into DDR memory. This pipeline is abstracted by the SDSoC platform. The user application can access the video frames by Video4Linux (V4L2). The Live I/O for PCam demo shows you how to do this. I suggest you to read the proposed documentation to obtain a basic knowledge needed for SDSoC projects development. Best regards, Bogdan D.
  10. 1 point

    Vivado free for Artix-7?

    Hi @TerryS, Thank you for posting how you got to the legacy content. I will pass this on to our content team. We will still have this content accessible since there are a wide array of people that use different versions of vivado. The legacy content is accurate for earlier versions of Vivado/SDK. best regards, Jon
  11. 1 point

    Arty A7 USB mechanical USB problem

    Hi @acm45, I reached out to one of our design engineers about this thread. They responded that: "there are no series resistors between the D+ and D- pins of the connector and the those pins on the FT2232HQ. I think it would be very difficult to solder the D+ and D- wires directly to pins of the USB controller. My suggestion is to purchase an external JTAG programmer/debugger (JTAG-HS2) and attach it to header J8." best regards, Jon
  12. 1 point
    Hi @learni07, Can you please check the baud rate from Tera-Term? For this, click on Setup->Serial port and check Baud Rate down-menu. It has to be 115200. Best Regards, Bogdan Vanca
  13. 1 point

    OpenCV and Pcam5-c

    Hi @Esti.A, I would suggest using the version of Vivado/SDK/Petalinux that the project was made in and for. If you are typing to update an existing project to an newer version there are alot of potential issues that could occur. We do not have a tutorial on how to do this. I would suggest looking through the xilinx petalinux documentation like the petalinux wiki. Here is a forum thread that might be helpful as well. best regards, Jon
  14. 1 point

    Cora Z7 Basic IO example problem

    Hi @Lost_In_Space, Welcome to the Digilent Forums! Please download Adept 2. 1) Can Adept 2 recognize the Cora Z7? Please attach screen shots of the Adept 2 text when the Cora Z7 is connected. 2) Are you using Linux? Windows? 3) Is the Mode Jumper JP2 set to JTAG? 4) How are you powering the Cora Z7? USB or external power source? best regards, Jon
  15. 1 point

    Passing FFT result to DDS

    @FR There are many ways to construct a sine wave. You could do a table lookup, or even a quarter table lookup. You could do a CORDIC. You could do a table lookup followed by a linear or even a quadratic interpolation. That part is the least of your worries. Your bigger problem is going to be the fact that short-time Fourier Transforms (STFTs, such as what you've just used), are not phase continuous in nature. As a result, depending on how you set up the overlap, you might find that every odd bin jumps 180 degrees of phase between transforms. Worse, if that wasn't enough, what happens if the incoming tone doesn't line up exactly on an FFT bin? This piece of reality has been known to kill a lot of poorly thought out FFT approaches. Something else to think about: Are you hoping to match the phase of the incoming sine wave? The phase delay through the FFT is both coarsely sampled and linear in frequency. I might suggest perfecting your algorithm off-line before even experimenting with it on an FPGA. I often use Verilator to accomplish both at once, although I know there's a large group of individuals who like using MATLAB for prototyping before moving to hardware. Dan
  16. 1 point
    Hi @Phil_D It can be done like this: const NAVG = 10 Spectrum.run() var sum = [] for(var acq = 1; acq <= NAVG && Spectrum.wait(); acq++){ var hz = Spectrum.Channel1.dataRate // WF v3.11.2 { // padding in Trace 5 var rg = Spectrum.Channel1.data // channel 1 time domain data var c = rg.length var t = rg[c-1] // last sample for(var i = 0; i < c; i++) rg.push(t) // 2x padding Spectrum.Trace5.setSamples(rg, hz) } { // averaging in Trace 6 var rg = Spectrum.Trace5.magnitude if(acq==1){ sum = rg; Spectrum.Trace6.Clone(Spectrum.Trace5) }else{ rg.forEach(function(v,i){ sum[i] += v;}) // sum sum.forEach(function(v,i){ rg[i] = v/acq;}) // average Spectrum.Trace6.setMagnitude(rg, 0, hz/2) } } } Spectrum.stop()
  17. 1 point
    Hi jon! I have resolved that issue using a case statement to assign the bits instead of using the - operator.Hence I have deleted the post also immediately.where you still able to see it?
  18. 1 point

    Pmod DA3

    Hey everybody, A small question. I need to generate a signal of 28.8MHz (sine wave), so in FPGA I've build a DDS and it's generating a nice sine wave @ 27.799MHz (close enough :p). For connecting this to a certain target board I've bought the PMOD DA3 (https://store.digilentinc.com/pmod-da3-one-16-bit-d-a-output/). There is only one small problem that I can't figure out... I know when you're sampling you have to comply to Shannon's theory, but how is it with DACs when you are reconstructing a signal, do they also have to comply to this? I've dived into the schematic of the PMOD DA3 and saw that a chip from Analog Devices is used, more specific the AD5541A. When looking into the datasheet, I saw that it connects with a 50-MHz SPI-/QPSI-/... interface, meaning that SCLK can take a maximum of 50MHz when a voltage supply of 2.7 - 5.5V is applied... Now the question that I have is, does a DAC need to comply to Shannon's theorem, meaning that the absolute max I can generate with this DAC is a 25MHz signal (in ideal conditions), or does a DAC not have to comply with this and I can just generate the signal without any problem :)? Thank you :)!
  19. 1 point
    Hi @Phil_D There is no zero padding option but it can be done with Script like this: var rg = Spectrum.Channel1.data // channel 1 time domain data var c = rg.length var t = rg[c-1] // last sample for(var i = 0; i < c; i++) rg.push(t) // 2x padding var rghz = Spectrum.Trace1.frequency var hz = 2.0*rghz[rghz.length-1] //var hz = 2.0*Spectrum.Frequency.Stop.value // scope sample rate Spectrum.Trace5.setSamples(rg, hz) Some other suggestions to improve the resolution: 1. For lower frequencies, with 1MHz sampling you can use the Scope to perform a longer recording. This will highly improve the resolution in the FFT view. 2. With AD you can select the second device configuration to have 16k Scope buffer. 3. You can select a higher bandwidth window, like rectangular or cosine. 4. In the latest beta version with CZT algorithm you can select higher number of bins, higher resolution. https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ Here: - T1 is CZT BlackmanHarris 10x BINs, 244Hz resolution - T2 is FFT BlackmanHarris 4k BINs 2.4kHz resolution - T3 is FFT Cosine 4k BINs 2.4kHz resolution
  20. 1 point

    VGA on Zybo

    Hi @Mukul, Here is a VHDL VGA project that has pixel clock frequencies for multiple resolutions. Here and here are non-digilent VGA tutorials. Here is a listing for different pixel frequencies and resolutions. best regards, Jon
  21. 1 point
    Hey @Phil_D I too had a problem with getting WaveForms to run automatically, and my group didn't find a way to make it work through the suggested code. However, we did have success when we commanded Python to simulate an F5 key press, which is a shortcut in WF to run the script. We used the library "uinput". Here's a sample of the actual command we used. I'm not certain that it's all you need, as I was not the primary Python programmer for this project, but at least it'll give you an idea of what needs to be done for this workaround. The sleep timers are there to give the program time to start and load the workspace. waveform_Call = subprocess.Popen("exec " + waveforms, shell = True) waveform_Call time.sleep(10) device = uinput.Device([ uinput.KEY_FN, uinput.KEY_F5, ]) time.sleep(1) device.emit_combo([ uinput.KEY_FN, uinput.KEY_F5, ])
  22. 1 point
    So i did manage to get the multiple line print error fixed. By keeping track how how many bytes are being written to the card and then seeking by that amount I am able to print to the end of the file. It's not the most elegant solution but it works.
  23. 1 point

    ZYBO HDMI IN project

    Hi @birca123, I got the same errors when I loaded the applications. Looking at the last line says that the "BSP Project P/HDMI_IN_bsp has been successfully migrated" is a good thing. I was able to program the FPGA, run the application and the project to worked. I have updated the above linked HDMI project with my sdk portion done as well. I have also attached my SDK log so you can compare it to what you have. best regards, Jon SDK_LOG_HDMI_IN.txt
  24. 1 point
    Hello Jon! Thank you for giving hope in coding with what ever I am comfortable with.
  25. 1 point

    ZYBO HDMI IN project

    Hi @birca123, I would suggest to start with a fresh sdk portion of the project. To do this close SDK and delete the hdmi-in.sdk folder in the \Zybo-hdmi-in\proj folder. Then in vivado click file->export -> export hardware including the bitstream. Then launch SDK from Vivado by clicking in file and selecting launch SDK. Once in SDK and the HW platform is loaded click in file and import HDMI_IN and HDMI_IN_bsp from Zybo-hdmi-in\sdk. Once you have the HDMI_IN and HDMI_IN_bsp into your SDK project then program the FPGA Next open a serial terminal emulator like tera term and connect to the Zybo's com port. Set the baud rate to 115200 everything else should be left at default settings. Now connect the Zybo to the HDMI and VGA device. then in SDK right click on HDMI_IN and select run as->launch on hardware(system debugger). Do you see the serial terminal menu? Is there an image on the VGA device?
  26. 1 point

    ZYBO HDMI IN project

    Hi @birca123, You will need to click into setting->ip->repository and change the path to reflect where the vivado library folder is on your PC. On my pc the path is C:\Users\jpeyron\Desktop\Zybo-hdmi-in\repo\vivado-library. I have attached screen shots as well. best regards, Jon
  27. 1 point
    thanks for the response. Greatly appreciated. I figured out what I had done wrong....I didn't select the Board properly. I had filtered/searched for the Basys3 board and when that was the only one on the screen I "thought" that was all I needed to do to select it. I pressed next......and that caused my problem. I finally realized I had to click in one of the fields for the selected/filtered board, which turns the whole line blue...and THAT selected the proper board. I figured it out by looking at the Project Part # (within the project) and realized it was NOT the Basys3 board. Stupid mistake. Thanks again for responding...and so quickly!
  28. 1 point

    Read out .log file from OpenLogger

    Hi @Peggy, I spoke with some of the firmware folks for WFL and OpenLogger and learned that they haven't yet implemented the parsing of the header into the Digilent agent yet. I did receive a picture that showed the structure of the header file, which I have attached below. Thanks, JColvin
  29. 1 point

    Pmod ISNS20 SPI Arduino

    Hi @tfcb, I am taking a look into this; I connected a level shifter of my own (Digilent's Pmod LVLSHFT rather than the Sparkfun one you linked to) to connect an Arduino Uno and Pmod ISNS20, but I too am getting strange values (no initial offset for example), so I'm debugging some more. Thanks, JColvin
  30. 1 point

    IP used in Zybo-Z7 MIPI Pcam 5C demo

    I achieved everything to work properlly. Thanks @jpeyron. Kind regards Esti
  31. 1 point
    Hi, >> We are forced to work in assembly with picoblaze. you might have a look at the ZPU softcore CPU with GCC. The CPU is just a few hundred lines of code but most of its functionality is in software in the crt.o library in RAM. I understand it's quite well tested and has been used in commercial products. Not surprisingly, using an FPGA to implement a processor that then kinda emulates itself in software (aka RISC :) ) is maybe not the most efficient use of silicon - I'm sure it has many strong points but speed is not among them... Unfortunately, the broken-ness of Xilinx' DATA2MEM utility (to update the bitstream with a new .elf file) spoils the fun, at least when I tried in ISE14.7 (segfaults). When it works, the compile/build cycle takes only a second or two. Long-term, porting the processor to a new platform would be straightforward, or even fully transparent if using inferred, device-independent memory. This would also work for a bootloader that is hardcoded into default content in inferred RAM. I might consider this myself as a barebone "hackable" CPU platform strictly for educational purposes.
  32. 1 point

    Arty A7 vs Nexys A7

    Thanks @jpeyron for the info. I just received my board and some IO modules so I will be digging through the resources you mentioned
  33. 1 point
    Hi @callum413 You can find it here: To enable the option check the following:
  34. 1 point

    Inter core communication

    As far as I know the NN training phase takes long time and needs many resources. For this reason it is not recommended to train NN on FPGAs. On the other hand, FPGA is strong in inference. I advise you to use GPU and a learning framework, like Caffe, for the training phase. Fortunately, Xilinx released recently a new development kit for NN named Deep Neural Network Development Kit (DNNDK). Here you have the user guide and the DNNDK extension for SDSoC. Have a look on the Xilinx documentation and forum posts to get familiar with all concepts. Let us know if you have any questions.
  35. 1 point

    IP used in Zybo-Z7 MIPI Pcam 5C demo

    Hi @Esti.A, Can you be more specific? The Vivado library branch here has the updated MIPI_D_PHY_RX and MIPI_CSI_2_RX. These IP Cores were updated by the creator of these IP cores and should work are described in this forum thread here. Here is a forum thread that discusses some of the difference between Digilent's MIPI_D_PHY_RX and MIPI_CSI_2_RX IP Cores and those that are available for purchase. best regards, Jon
  36. 1 point
    Hi @callum413 Tomorrow beta build will support time stamp identified by the software. High precision timer is not available in the device.
  37. 1 point
    Hi @Luighi Vitón, I'm not sure it's a HDMI issue, have you tried to use X11 over SSH do you get the same result? -Ciprian
  38. 1 point
    Hi @askhunter, The top.vhd is already added to the project. If you are wanting this file to be underneath the design_1 then you should right click on the design_1 and select add sources. Then add the vhdl files you would like to add to the design. It might be easier to start with a fresh project. best regards, Jon
  39. 1 point

    Arty A7 vs Nexys A7

    Hi @Phil, The Arty-A7-100T comes with with a built in USB JTAG/UART (J10) programming circuit.You will not need an additional JTAG programmer like the JTAG-HS2 to configure the Arty-A7-100T. Here is the Arty A7 resource center. Under Additional Resources there is a tutorial called getting started with microblaze servers that goes through making an ethernet echo server with the Ethernet lite IP Core (no cost). best regards, Jon
  40. 1 point

    Nexys 2 - transistor part number

    Transistor has been replaced, board is back up and running. Thanks!
  41. 1 point

    Nexys 2 - transistor part number

    Hi @CVu, Welcome to the Digilent Forums! Q1 information is below: NTS2101P Single P-Channel Power Mosfet 1.4A, 8VSOT-323 (SC-70) best regards, Jon
  42. 1 point

    NexysDDR4 example projects

    OS file permissions are a two-edged sword. It can prevent users from changing stuff that shouldn't be changed but it can prevent users from doing their work unintendedly This is a user issue. You will have to learn how to change file permissions as a computer user to the extent that your privileges allow. Depending on the OS and how security is set up this can be a pain, especially when transferring files form one OS or computer to another one. If you have an IT department they should be able to help resolve issues. If you are the IT department then you need to learn how to set up and use your OS safely and securely.
  43. 1 point

    Pmod DA3 clocking

    Inside the AD5541A, the MOSI bits get clocked into a shift register and are held there until the ~CS line goes high. At that time, the bits are transferred from the shift register to the D/A. It does not matter what level is on MOSI at that instant. In the traces I posted earlier, I included a transition from full scale output to 0. I also show several cycles of writing all possible values in a ramp. The resulting voltage waveform shows the AD5541A is seeing the data correctly. The last four writes to the pmod in the zoomed trace show sending the values 0, 1, 2 and 3 to the D/A. You can observe SCLK's transition in relation to the least significant bits of the data. SCLK is not transitioning when ~CS transitions to high so the data on MOSI is "don't care" at that instant. I did use different clocks since the microblaze can run at higher clock rates than the AD5541A. Also, when you are troubleshooting, it can sometimes help to slow down the logic. I see you are using pmod connector JB whereas my project used JA. Just as a test, you might want to try moving your PmodDA3 to JA and use my project as is to replicate my results. You should be able to launch vivado, open my project then immediately launch the SDK from vivado. You should not have to generate a bitfile. I had included the hardware handoff in the zip file I gave you so you have my exact bitfile. Once the SDK loads, it should automatically load the project and compile it. At that point you can program the fpga from inside the SDK and then run my example app. You should see a sawtooth waveform coming out of the PmodDA3 if all is well.
  44. 1 point

    Pmod DA3 clocking

    I included visualizations of the ~CS, SCLK and DIN lines in the logic analyzer trace I posted Tuesday at 2:51 AM. In the trace, MOSI is the DIN line, Enable is the ~CS line and Clock is the SCLK line. Did the Xilinx SDK report any errors while opening the workspace? Did you program the fpga from the SDK?
  45. 1 point
    Hi @Nithin Yes. See the AnalogIO_DigitalDiscovery.py how to adjust the IO voltage, enable VIO output, set pull-up/downs, slew rate, drives The DigitalIO functions can be used the same way controlling DIO[24:31] The DigitalOut functions are the same but you have 32k custom bit/line for DIO[24:31] The DigitalIn by default samples DIN[0:23]&DIO[24:31]. To sample DIO lines first DIO[24:39]&DIN[0:15] set FDwfDigitalInInputOrderSet(hdwf, true). This way if you sample 16 bits you will get DIO[24:39]. The base frequency is 800MHz (FDwfDigitalInInternalClockInfo), like use FDwfDigitalInDividerSet(hdwf, 8 ) for 100MHz
  46. 1 point
    Hi, >> applying various algorithms if you don't know the algorithms yet, it might be easier to get the ADC data into a softcore CPU, then prototype in C using floating point. The point is, experimental prototyping of algorithms in fixed point RTL is a slow and painful process.whereas reloading a .elf binary takes a second. I'm guessing your intent but I suspect you'll find eventually that an FPGA is not the optimal platform choice for your application. Meaning, you can most likely get the same result cheaper and with less effort e.g. using a Raspberry PI + SPI converter. I'm guessing this simply because higher-rate ADCs where FPGA makes sense (hundreds of MHz) are hard to come by as OTS modules. Otherwise, if you design for, say, 1 MSPS, the FPGA fabric will do less than 1 % of the work it could do but you pay for 100 % so people usually don't use FPGA, if a CPU or DSP will do the job.
  47. 1 point

    NEXYS 3 frequency meter

    The problem is likely in the .ucf file where you define pin information. The error message says device pin LL8 doesn't exist. If you post the contents of your ucf, we can probably figure it out.
  48. 1 point
    Hi @ezadobrischi, Welcome to the Digilent Forums. Please be more specific on the Photo Diode output. Based on basic Photo Diode output I would: 1) Convert the photo diode receiver current output to voltage and use an ADC to read the voltage signal. 2) The Nexys 4 DDR has and on-board XADC (xilinx analog to digital converter) 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide. Here is our XADC demo for the Nexys 4 DDR done in Verilog. 3) The voltage input range is 0v to 1v in unipolar mode and -.5v to .5v for bipolar mode for the on-board XADC. 4) If the voltage is not within the 0v -1v then I would either use a level shifter circuit to bring the analog signal into the 0-1v range or use something like the Pmod LVLSHFT. 5) If the voltage is in the 3.3v - 5v range and do not want to use use a level shifter you can use other ADC's like the Pmod AD1. Once you have the signal in the Nexys 4 DDR you can filter the signal. cheers, Jon
  49. 1 point

    DAC Pmod DA3 on Spartan 3 Starter Kit

    Hi @lwew96, Here is a VHDL Pmod DA3 project done by a community member @hamster that is made in vivado with the Basys 3. To make this project work with the spartan 3 you will need to use the xdc file as a reference for the spartan 3's ucf file. cheers, Jon
  50. 1 point

    MMCM dynamic clocking

    Hey, something else I just saw when reading the clocking guide was: MMCM Counter Cascading The CLKOUT6 divider (counter) can be cascaded with the CLKOUT4 divider. This provides a capability to have an output divider that is larger than 128. CLKOUT6 feeds the input of the CLKOUT4 divider. There is a static phase offset between the output of the cascaded divider and all other output dividers. And: CLKOUT4_CASCADE : Cascades the output divider (counter) CLKOUT6 into the input of the CLKOUT4 divider for an output clock divider that is greater than 128, effectively providing a total divide value of 16,384. So that can divide a 600 MHz VCO down to 36.6 kHz.