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Showing content with the highest reputation since 02/25/19 in Posts

  1. 2 points
    Hi, there's a lot of new information in your last post. You aren't just "trying" FPGA but have a professional interest in Zynq. Don't let anybody scare you it's "difficult" and go for it, possibly with the cheapest board, no tutorials and low expectations like, blinking LEDs for quite a while. Given the price tag of any industrial training coarse, an FPGA board for self-study is a no-brainer. Maybe save some money to buy your FPGA engineer a coffee once a week, with some questions in mind
  2. 2 points
    True. Zygot believes that making you work for knowledge is kinder than giving you solutions that can be used to mindlessly resolve your problem of the hour.... it's just a different philosophical bent...
  3. 2 points

    Pmod DA3 clocking

    It looks to me like DA3_WriteSpi() was adapted from code for a different device and has vestigial and incorrect code. Reviewing the AD5541A datasheet, several things stand out There is only a single register in the chip so there is no need for the u8 reg parameter. There is no need for a"config byte" to be sent before the data. The transfer is always 16 bits so there is no need to allow for arbitrary length data quoting from the datasheet "Input data is framed by the chip select input, CS. After a high-to-low transition on CS, data is shifted synchronously and latched into the serial input register on the rising edge of the serial clock, SCLK. After 16 data bits have been loaded into the serial input register, a low-to-high transition on CS transfers the contents of the shift register to the DAC register if LDAC is held low". Reviewing the PmodDA3 schematic, the ~LDAC signal is softly pulled to ground with a 10K resistor. So there is no need to explicitly toggle ~LDAC. What all this means is DA3_WriteSpi could be simplified to something like void DA3_WriteSpi(PmodDA3 *InstancePtr, u16 wData) { u8 bytearray[2]; bytearray[0] = ((wData & 0xFF00) >> 8); bytearray[1] = (wData & 0xFF); XSpi_Transfer(&InstancePtr->DA3Spi, bytearray, 0, sizeof(bytearray)); } You would then call it passing in just the instance pointer and the value you want to write to the DAC. u16 dacValue = 1234; DA3_WriteSpi(&myDevice, dacValue); I do not have a PmodDA3 on my bench so I cannot verify the function works, You can give it a try and let us know how it goes.
  4. 2 points

    Pin Mapping for JTAG-SMT3-NC

    Hi @RussGlover, I apologize for the delay; the details you are looking are as follows: TCK - ADBUS0 TDI - ADBUS1 TDO - ADBUS2 TMS - ADBUS3 OEJTAG - ADBUS7 OESRSTN - ACBUS4 Let me know if you have any more questions. Thanks, JColvin
  5. 2 points

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  6. 2 points

    Pmod DA3 Pinout

    That is one of the conventions commonly used to indicate an Active Low signal. So in this case, you pull Chip Select low when you want to access the chip. After you have toggled in all the data bits on the DIN line, you pull LDAC low. The Pmod DA3 reference manual has a link to the D/A chip's datasheet. That is the best first place to look for information on the device's function. The required signal timings are on page 5 of the datasheet.
  7. 2 points
    @Ahmed Alfadhel If you installed Vivado then you also installed the Xilinx Document Navigator. If you are serious about developing with FPGA devices you need to know how to find and access the plethora of documents that your vendor provides in order to use their devices properly. Check the box for 7 Series devices to see the list of reference manuals, User's Guides, Datasheets etc. From there you can add all relevant documents to your search and keep up to date. Do the same for ISE or Vivado tools. This is where everyone needs to start their Xilinx FPGA journey. Xilinx makes it easier than other FPGA vendors to obtain knowledge.
  8. 2 points
    The hot plug detect should be on the rx side. The source will see that and will then initiate the DDC conversation.
  9. 1 point

    Nexys 2 - transistor part number

    Thank you very much Jon. Much appreciated.
  10. 1 point

    Nexys 2 - transistor part number

    Hi @CVu, Welcome to the Digilent Forums! Q1 information is below: NTS2101P Single P-Channel Power Mosfet 1.4A, 8VSOT-323 (SC-70) best regards, Jon
  11. 1 point

    NexysDDR4 example projects

    OS file permissions are a two-edged sword. It can prevent users from changing stuff that shouldn't be changed but it can prevent users from doing their work unintendedly This is a user issue. You will have to learn how to change file permissions as a computer user to the extent that your privileges allow. Depending on the OS and how security is set up this can be a pain, especially when transferring files form one OS or computer to another one. If you have an IT department they should be able to help resolve issues. If you are the IT department then you need to learn how to set up and use your OS safely and securely.
  12. 1 point

    Pmod DA3 clocking

    Inside the AD5541A, the MOSI bits get clocked into a shift register and are held there until the ~CS line goes high. At that time, the bits are transferred from the shift register to the D/A. It does not matter what level is on MOSI at that instant. In the traces I posted earlier, I included a transition from full scale output to 0. I also show several cycles of writing all possible values in a ramp. The resulting voltage waveform shows the AD5541A is seeing the data correctly. The last four writes to the pmod in the zoomed trace show sending the values 0, 1, 2 and 3 to the D/A. You can observe SCLK's transition in relation to the least significant bits of the data. SCLK is not transitioning when ~CS transitions to high so the data on MOSI is "don't care" at that instant. I did use different clocks since the microblaze can run at higher clock rates than the AD5541A. Also, when you are troubleshooting, it can sometimes help to slow down the logic. I see you are using pmod connector JB whereas my project used JA. Just as a test, you might want to try moving your PmodDA3 to JA and use my project as is to replicate my results. You should be able to launch vivado, open my project then immediately launch the SDK from vivado. You should not have to generate a bitfile. I had included the hardware handoff in the zip file I gave you so you have my exact bitfile. Once the SDK loads, it should automatically load the project and compile it. At that point you can program the fpga from inside the SDK and then run my example app. You should see a sawtooth waveform coming out of the PmodDA3 if all is well.
  13. 1 point

    Pmod DA3 clocking

    I included visualizations of the ~CS, SCLK and DIN lines in the logic analyzer trace I posted Tuesday at 2:51 AM. In the trace, MOSI is the DIN line, Enable is the ~CS line and Clock is the SCLK line. Did the Xilinx SDK report any errors while opening the workspace? Did you program the fpga from the SDK?
  14. 1 point

    NEXYS 3 frequency meter

    The problem is likely in the .ucf file where you define pin information. The error message says device pin LL8 doesn't exist. If you post the contents of your ucf, we can probably figure it out.
  15. 1 point

    FMC Breakout

    Thanks for all your help guys. I chose the XM105.
  16. 1 point

    FMC Breakout

    I like the IAM electronics board better because you can stack another board on top, somewhat like a pcie card interposer. The Xilinx XM105 is ok but I had to use ribbon cables to get the signals to a prototyping board. That may not be a problem if you are routing lower speed signals thru the FMC, but it might affect the fidelity of higher speed signals.
  17. 1 point

    CMOD a7-35t Schematic

    I found this page useful. About 1/3 the way down is a picture of the two boards side by side.
  18. 1 point

    PMODDA2 on ZedBoard

    Ah thats right, I had to correct that as well. Just change the instance name of the up/down counter to counter. Sorry I forgot about that. up_down_counter counter ( .clk(clk_div), .counter(counter1) );
  19. 1 point

    PMODDA2 on ZedBoard

    You can delete the reference to DA2RefComp.vhd under non-module files (right click on the file and select "Remove file from project"). Then re-add the file to the project using the "Add sources" command. Simply copying the file to the directory from outside of vivado is not sufficient for vivado to know about the file.
  20. 1 point

    Pmod DA3 clocking

    @Ahmed Alfadhel, I have sent you a PM with a link to the project archive. The forum limits the size of attachments so I am not able to upload it.
  21. 1 point

    Pmod DA3 clocking

    I obtained a DA3 and was able to get it working. Here are some pictures of my setup. I am limited by how big the attachments are so I will post again with an archive of the project I used.
  22. 1 point
    As a member of the self-taught group, I will agree that it is possible to learn how to use a Zynq or any other board. However, you will absolutely run into the fact that that zygot put nicely where you will need: You can readily get an understanding of the basics, but you will also need (to loosely quote Dan) "an understanding of the formal methods" to both create and verify work. Otherwise you will run into the mentioned "I ran the demo, but tried to change one thing and now nothing works"; it's hard to know what you're doing if you don't know how it works. So is it possible to learn? Yes, but if you're wanting to do complex designs (which you only learn which ones are complex by trying to build them yourself) you'll need to dedicate more than just spare time on the weekends to learning. The phrase "reap what you sow" is applicable here I think.
  23. 1 point
    Hello JColvin, The connectors are totally broken off with the main issue being the mounting tabs. It is because the students aren't careful when removing the cable, mishandling their setup when using the board, or forcing the insertion. Many of the cables they are using have spring tangs on the mating connector which tend to lock in the corresponding slots in the connector housing. The links you provided look like they show a compatible connector so I will order some and try them out before committing to a larger quantity. Thanks much, John Evans - USAF Academy, CO
  24. 1 point
    Hi @John Evans, I'm personally not able to find the actual part number individually, but there are some details about the microUSB connector on this thread here: Is the connector broken off entirely, or are there some instances where the cable was plugged in upside down so that the tab inside of the connector was simply bent downward slightly? If the latter is the case, you can push the tab back up with a small flathead screwdriver or something similarly sized. Thank you, JColvin
  25. 1 point
    Hi @ezadobrischi, Welcome to the Digilent Forums. Please be more specific on the Photo Diode output. Based on basic Photo Diode output I would: 1) Convert the photo diode receiver current output to voltage and use an ADC to read the voltage signal. 2) The Nexys 4 DDR has and on-board XADC (xilinx analog to digital converter) 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide. Here is our XADC demo for the Nexys 4 DDR done in Verilog. 3) The voltage input range is 0v to 1v in unipolar mode and -.5v to .5v for bipolar mode for the on-board XADC. 4) If the voltage is not within the 0v -1v then I would either use a level shifter circuit to bring the analog signal into the 0-1v range or use something like the Pmod LVLSHFT. 5) If the voltage is in the 3.3v - 5v range and do not want to use use a level shifter you can use other ADC's like the Pmod AD1. Once you have the signal in the Nexys 4 DDR you can filter the signal. cheers, Jon
  26. 1 point

    Question about adding Pmod

    Hi Joe, Thank you so much for you help! It works! So I can now continue my final project. Mingfei
  27. 1 point
    Hi @MMateos, Welcome to the Digilent Forums! We have the Pmod KYPD which has Verilog and VHDL examples using it with a Nexys 3 and ISE. Here is an unverified VHDL Basys 3_PmodKYPD Vivado 2018.2 project that should help with your project. cheers, Jon
  28. 1 point
    It seems that something went wrong when preparing first partition with BOOT.BIN and image.ub files. First method : A minimal test that we can do is to prepare only one FAT32 partition and copy BOOT.BIN and image.ub files. Then start the board with this setup. This way it should only start the Linux kernel, however no rootfs. The UART should be initialize. and the green LED should be on. Step 1: format SD card as FAT32 file system Step 2: copy BOOT.BIN and image.ub files to the SD card (then safety remove the SD card) Step 3: insert SD card in zybo-z7-20 and power the board Step 4: The green LED turns on then it means that the UART(via FTDI) is ready. Note: Alternative: The second file attached was z7-20.img.zip which is a snapshot off a 2GB SD card containing both partitions. The image can be written to the micro SD card with `dd` tool on Linux or a similar tool for Windows (writing this image to SD card from windows 10 worked for me using Win32DiskImager). Step 1: extract the z7-20.img.zip Step 1.A : insert micro SD card if not already inserted. Step 2: run Win32DiskImager Step 3: For `Image File` field set the path to z7-20.img file. z7-20.img sha1sum: e08516edb24ff65d32ce7a43a946f0be9b9f0ebe (If you want to check) Step 4: In `Device` field make sure the Drive letter for microSD is selected (If not you risk loosing data from other devices). Step 5: Pres write.(If you are prompted to format partitions please do not. The second partition filesystem is ext4 which is not recognized by the OS) Step 6: After the process ended, safety remove the micro SD. Step 7: Plug the micro SD into the z7-20 board. Power up the board.
  29. 1 point

    Pin Mapping for JTAG-SMT3-NC

    Hi @RussGlover Ah, sorry about that; it's on ACBUS5. Let me know if you have any more questions. Thanks, JColvin
  30. 1 point

    Voucher for ARTY A7

    As a bit of further clarification, you would request any licenses from Xilinx, though it is my understanding that all of the Vivado WebPACK versions since 2016.4 or so are license free. I know that Digilent used to sell the original Arty board (now called the Arty A7) with a voucher for the Vivado Design Edition, but that was discontinued a few years ago (around the same time when Xilinx changed their own licensing policy and what was included in each edition). Thanks, JColvin
  31. 1 point
    I've been bothered by this question since it was posted. Is it possible to implement logic in hardware using and HDL to implement the basic requirements to send and receive UDP packets for a direct connection between your FPGA board and a computer? Sure. You can find a few implementations that will show you what the necessary functionality is. If the path between your computer and your FPGA board is not direct and your packets are not in order or get fragmented then things get complicated, but still doable. The question then becomes is it worth doing without a soft-processor? Only you can answer that question. I would suggest that you should have a practical understanding of all of the Ethernet layers. You can study the code for light-weight Ethernet stacks available for hard or soft processors to see what you need to support. Sending UDP ( or any packet structure you can imagine ) between two FPGA boards is relatively easy and can be done with minimal effort. Once you start dealing with a full-blown OS stack things can get quite complicated. I doubt that you care about this for your project but it is possible to avoid the PC Ethernet port on your computer and still implement communication between your PC and an FPGA target(s) using the target Ethernet PHY(s). Opencores has some interesting projects [some involving MACs and some not]. The Digilent Project Vault has a couple of projects that might help. There will be those who disagree but I suggest becoming knowledgeable with how Ethernet connectivity works is a precondition for trying to implement it in an embedded application using logic or software tools. [edit] You might find that using the parallel USB 2.0 interface on the Nexys Video is easier and possibly a better way to connect your board to a PC; unless, of course, you have a requirement for UDP packets.
  32. 1 point
    Hi @Shiro, Here and here are xilinx forum thread that discusses the multiple driver issue when making a custom IP. Here and here are a few ZYNQ tutorials that will help you with making a custom IP. thank you, Jon
  33. 1 point
    When you boot using the microSD card that you have prepared is the green led [LD12 DONE] turned on?
  34. 1 point
    In fact, I recommend either of the below: - use a speaker with Pmod Amp2 (without amplifier) - use Pmod I2S2, with external amplifier and speaker.
  35. 1 point

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, In section 2 Interfacing with the Pmod on page 1 of the reference manual for the Pmod DA3 here it states the pmod should use spi mode 0. thank you, Jon
  36. 1 point

     DIFF_SSTL15 to TMDS_33

    @Ahmed Alfadhel, The real answer is that if you have both sys_clk and ddr3_sdram_ck* on the same bank, your pinout is still wrong. sys_clk is on a 3.3V bank, ddr3_sdram_ck* is on a 1.35V bank. If you give Vivado the wrong pins for these three wires, it will complain about the wrong voltage standard. Go back and set these pins to their right values. If you want a quick way to do this, consider using this UCF file to load the pin definitions directly into the MIG DDR3 SDRAM controller generator. Dan
  37. 1 point

    GPS driver question.

    Hi @StefanOR, Here is a forum thread that discusses using the GPS.ping that might be helpful for your project. I believe that the GPS_setUpdateRate(&GPS, 1000); //Sets the frequency that the PmodGPS sends sentences. and an interrupt is sent every 8 bytes GPS_intHandler(PmodGPS *InstancePtr, u32 Event, unsigned int EventData) sets the InstancePtr->ping = TRUE; The PmodGPS.c, PmodGPS.h and main.c will be the files to look through. thank you, Jon
  38. 1 point

    booting linux on zynq with SD card

    Hi @Arjun, I moved this thread to a sub-section where more experienced embedded linux engineers look. cheers, Jon
  39. 1 point
    Hi @fonak The CC/CV mode was added to WF beta 3.10.3 https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ You can find the schematic of IA Adapter here: https://reference.digilentinc.com/reference/add-ons/impedance-analyzer/start Currently you can make lock-in amplifier like this: Impedance 1. Thanks for reminding. I wanted to add offset compensation for DC, just got distracted with other projects. 2. At the moment you can use a script for history like this: Impedance.run() // use averaging to control the sample rate Impedance.Frequency.Averaging.value = 0.2 plot1.X.AutoScale.checked = false var rg = [] while(true){ if(!Impedance.wait()) break rg.push(Impedance.Traces.Trace.getData("Impedance")[0]) if(rg.length>50) rg = rg.slice(1) // max length plot1.Y1.data = rg plot1.X.Range.value = rg.length plot1.X.Offset.value = -rg.length/2 } Power 1. With AD2 6th device configuration you can use the power supplies as AWG With EExplorer board you can use voltage or current AWG. 2, 3 Ok 4. You can use F5/F6 to start/stop an instrument. 5. The AD/AD2 has no voltage or current readback. On the EExplorer board you can adjust the voltage/current limit and also have voltage/current readback. Protocol Logic 1. You can use script, similar to the previous IA In the Logic analyzer increasing the row height you get analog representation for the bus, interpreted values 2. You have I2C scanner in Protocol/I2C/Custom/examples Other 1. You can export and import data into Scope, Spectrum, Logic Analyzer... 2. Ok. Thank you for your suggestions.
  40. 1 point

    No petaLinux projects found in bsp

    Zedboard was a joint effort between Digilent and Avnet. We developed the board and Avnet took on the platform support and community forums at zedboard.com As you found out, Xilinx also provided their own bsp, but we were not part of that effort.
  41. 1 point
    Hi @cephy var time = new Date() while(wait()){ print(time.toISOString()) for(var i = 0; i < 1; i++){ Network1.single() Network1.wait() var szfile = "~/Desktop/na/"+time.getFullYear()+"_"+(time.getMonth()+1)+"_"+time.getDate()+"-"+time.getHours()+"_"+time.getMinutes()+"_"+time.getSeconds()+"-"+i+".csv" print(szfile) Network1.Export(szfile) // make sure the directory exists } time = new Date(time.valueOf()+5*60*1000) // add 5 minutes while(wait() && Date.now()<time.valueOf()); // wait }
  42. 1 point

    Simple HDMI pass through with NexysVideo

    Hi @neocsc, I believe you should be using the hdmi_rx_hpa from the master xdc for the Nexys Video here. #set_property -dict { PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa thank you, Jon
  43. 1 point

    Simple HDMI pass through with NexysVideo

    Hi @neocsc, Please attach a screen shot of the error. Not all timing errors will break a project. 1) Are you still able to generate a bitstream or does the timing error force the bitstream generation to stop? 2) If you are able to generate a bitstream please export the hardware(include bitstream), launch sdk and import application. Then program the fpga and run as ->launch on hardware(system debugger). 3) If so does the project make a serial terminal menu? $) If so does the project generate a HDMI pass through along with a pre-generated image? thank you, Jon
  44. 1 point
    Hi @Mukul, Are you getting the Error while launching program: Memory write error at 0x100000. APB AP transaction error, DAP status f0000021? 1. Make sure the boot mode jumper JP5 is set to JTAG. If your Mode setting are JTAG and you are still having an issue then please attach a screen shot of your SDK errors? thank you, Jon
  45. 1 point
    Hi @fonak I thank you for the ideas. I plan to add CV/CC mode which will require auto resistor switching on wider frequency range, mentioned by @kojak
  46. 1 point
    Hi @Sarika Athya, I will reach out to more embedded linux engineers to see if they have any input for you. I did find some web pages that look like they would be helpful here and here .The Xilinx's u-boot might be helpful as well. thank you, Jon
  47. 1 point
    Hi @prashant, Welcome to the forums. Here is the Arty-Z7 resource center. Under example projects the HDMI and OOB demo's use the PS of the ZYNQ. cheers, Jon
  48. 1 point

    WaveForms beta download

    3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom mathematic channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Netowrk Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.