1 pointThat's not how TMDS termination works. Read the material that I've suggested. Do not try and connect custom hardware or wires to your board unless you understand supported IOSTANDARD specifications and terminations for your device and bank Vccio. TMDS_33 termination resistors are external. The FPGA IO PULL_UP and PULL_DOWN are not suitable. Again, you need to do your homework before starting any experimentation. You are not likely to find what you are looking for using Xilinx IP. and the board design flow. You will have better fortunes if you learn Verilog or VHDL. The Digilent staff are keen on the board design approach perhaps you will be lucky and one of them will have some suggestions. But really, the appropriate thing to do here is write your own HDL to experiment with IOSERDES.
1 pointIf this is your first FPGA project you jumped into the deep end of the pool. The UltraScale devices are a lot more complicated than the normal devices used in products normally discussed in the Digilent Forum and the key information tends to be a lot more difficult to tease out. The first thing that you want to do is try to at least build the demo projects that come with your development kit. You might not be able to run them due to odd requirements. This is what I ran into with the ZCU106 TRD. But, with a bit modification of the tcl I did manage to build the demo.
1 pointHi, it sounds very unlikely. Now it does happen that boards fail (which is very rarely related to the FPGA itself, but more often unreliable USB cables, connectors, failing voltage regulators, PCB microcracks and, did I mention, unreliable USB cables) but usually, the problem is somewhere else. The FPGA GPIO circuitry is very robust. Unless there is an external power source involved outside the bank voltage range, I doubt you'd manage to damage it even if you tried. I guess we all know those panic moments, like "oh no I've bricked / toasted the board" and then you have a coffee, reboot the PC and everything is well again.