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Showing content with the highest reputation on 10/31/19 in all areas

  1. 1 point
    Hi @P. Fiery Thank you for the observation. It is fixed for the next version. This problem occurred on application close having detached script plot windows. This did not manifest under win10, the app closed normally. The context could be cleared for each script run, but I let to keep it to have code completion for variables, like this: You could use this as feature to check if this is the first run of the script, like:
  2. 1 point

    Can Arty Z7 handle 4k60p hdmi?

    Hi @greengun, No, the transceiver pins on the Arty A7 FPGA (a XC7A35TICSG324-1L FPGA) are no broken out. As per Xilinx UG475 (page 41), the HR I/O bank 16 is only partially bonded out, but as per the Arty A7 schematic, the HR I/O pins on bank 16 are not used. Thanks, JColvin
  3. 1 point
    Thanks for reporting. There was a problem with the project. We updated the project and the instructions in the README. Just run the following commands: git clone https://github.com/Digilent/Petalinux-Arty-S7-50.git cd Petalinux-Arty-S7-50/Arty-S7-50/ git submodule update --init petalinux-config petalinux-build