Have you added the Vivado library to your Vivado 2019.1 installation? You can do this from inside Vivado by Choosing settings in the Project Manager in the upper left, expand the IP selection in Project Settings and choose Repository. You can then add in the path to the Vivado-Library from Digilent (which you can download from our GitHub here). This should let you generate the bitstream.
Otherwise, you don't need to open up Vivado at all. If you have a fresh project you can open Xilinx SDK 2019.1, choose the workspace folder when it prompts you as the sdk folder source (as an example, mine is C:\Users\jcolvin\Documents\VivadoPrj\Arty-S7-PmodGPS_Vivado_2019_1\Arty-S7-PmodGPS_Vivado_2019_1.sdk) and wait for SDK to finish loading the workspace. When it is completed, you should see the hardware platform_0, the PmodGPS application folder, and the PmodGPS_bsp. You can then click the Xilinx tab at the top of the GUI, and choose to program the FPGA with the bitstream it finds. You will then want to connect to your board with your serial terminal of choice (I used TeraTerm) otherwise you won't see anything printing out. I then right-click on the PmodGPS application folder and choose Run As->Launch on Hardware (System Debugger). I then see the data printing out on the serial terminal.
Is this what you did for your project?