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Showing content with the highest reputation on 07/10/19 in all areas

  1. 1 point
    JColvin

    HELP! General questions about OpenLogger

    Hi @CNg33, 1) No, the OpenLogger does not support triggers to start sampling process on an analog input. 2) The OpenLogger doesn't have readable data logging to the SD card at this point in time, though I think 3) No, I do not think there is a way to increase the bandwidth on the OpenLogger since that would require a hardware change and have been informed that even if you multiplexed the ADC channels the bandwidth would not improve. The drop-off after 50 kHz will be quite sharp as it was designed similarly to the OpenScope MZ which also has a sharp roll-off after its 2MHz bandwidth at -3dB as shown on page 45 of the Microchip Masters presentation for the OpenScope MZ here. I haven't done math to figure out what the bandwidth would be at 100 kHz for an OpenLogger, though I do know it's a 2-pole filter that is used on each analog input. Thanks, JColvin
  2. 1 point
    Hi @CNg33, There is not a way to generate a pulse wave on WaveFormsLive; the current waveform options are a sine, triangle, ramp up, square waves, and DC output, with the ability to change the frequency, amplitude, and DC offset as appropriate. As mentioned on this thread, the math function button is not operating correctly; I tried the smaller buffer size that was recommended to me but to no avail. I will let you know when I hear an update on this. Thanks, JColvin
  3. 1 point
    Hi @Foisal Ahmed, We are very sorry for the inconvenience. The PDF version of our reference manual for the basys 3 wasn't updated with the additional information on the WIKI version of the reference manual. This will be fix shortly. The WIKI version of the reference manual here states : "Some Basys 3s have been loaded with a Flash device from Spansion (part number S25FL032), while others have been loaded with a Macronix device (part number MX25L3233FMI-08G). The part loaded on any particular board can be determined by checking the part number and manufacturer logo printed on the Flash IC itself, as seen in the images below." If MX25L3233FMI is not an option in Vivado 2015.1 i would suggest to install a newer version of Vivado. I would suggest Vivado 2017.4 or higher. best regards, Jon
  4. 1 point
    Hello @jpeyron, thanks for the responses. I'll try that the next day as I'm away from the desktop now and will report whether it works or not. 😀
  5. 1 point
    joaquinbvw

    Cora Z7-10 High-Speed Pmods

    Hi zygot, thank you for your response, I appreciate it very much! You're right, just using LVDS is not enough, I was just trying to see if there were maximum speed tests on that interface. At the end I'm planning to use JESD204B for this application, since that interface was design for this type of requirements. The Cora z7 board is just for testing, in the future we will be building our own board for the acquisition system we want to implement. I'm new to this JESD204B protocol/interface but I know that it has a lot of advantages and a lot of Analog Devices high speed ADCs use it, that's why I want to use that. There are some problems using the Cora z7 that I found, it seems that the traces that goes to the PMOD connectors are designed for LVDS, so it is a different impedance matching. I guess if I adapt it well on the other side the JESD204B could be used (it seems that they use CML interfaces for the data lines in this JESD204B protocol). And also you're right on the clock issue, I didn't see if any of the PMOD pins goes to any clock pin, I will have to check this also. We will be doing some tests in the next days, I will post our results here so you can see it and maybe help me with some questions. Thank you again. Cheers, Joaquín
  6. 1 point
    In the Project Settings for the project in which you create your FIFO from the IP Wizard you can select VHDL or Verilog. In ISE there is a separate Core Generator file that does this for your IP. I have a few tips: You definitely need to use Verilog to simulate MIG code You should avoid the AXI interface and just select the Native FIFO interface. This will be much easier to hook up to the Xillybus code. I've done a number of KC705 Xillybus project though without using the DDR for storage. Start off by building the Xillybus project. After you think that you understand how his design works try creating a custom interface to provide some positive feedback on how well you do. After you are comfortable with the Xillybus then try an add the MIG DDR interface. There will be a lot of clocks involved and timing closure will start becoming tricky. If you try and jump to a final project it likely will take longer than if you progress through integrating interfaces in an orderly step by step manner. Having a verilog model for the DDR memory certainly helps with simulation. After creating a MIG DDR interface it is not as simple as hooking up some FIFOs and reading data. You will need to create your own state machines to interact with your code and the DDR interface FIFOs to perform external read and write operations. Regardless of any experience you might have developing FPGA DDR designs with other vendors devices and tools I suggest that you read through all of the relevant Xilinx literature. This includes IP documentation, Vivado simulation, etc. Jumping off a cliff into a pool is a lot safer if you know what's waiting for you once you hit the water....
  7. 1 point
    JColvin

    Pmod wifi

    Hi @kavya@iiitn, You need to keep your router set to DHCP; this should be the recommend settings of your router as per it's manual here, rather than a static IP; the example project we provide with our Pmod WiFi determines and sets up the IP address and the connectivity for you; you only need to provide the SSID and password to the WiFi -- this is described in this post here. Additionally, in your earlier post showing your router and Zedboard, it looked like you both 1V0 and 2V5 selected with jumpers on the VADJ select in the bottom right corner of the board near the 5 push buttons. This will cause conflicting voltages on the Zedboard and likely damage it, particularly on the FMC. I would also not recommend showing all of your router settings (I removed the picture) as that can provide all of the details a hacker needs to access your internet. Thanks, JColvin
  8. 1 point
    Hi @Lesiastas You could change the declaration in the wrapper to UInt16: <DllImport("dwf.dll", EntryPoint:="FDwfDigitalInStatusData", CallingConvention:=CallingConvention.Cdecl)> Function FDwfDigitalInStatusData(ByVal hdwf As Integer, <MarshalAs(UnmanagedType.LPArray)> rgData() As UInt16, ByVal countOfDataBytes As Integer) As Integer End Function And use as: Dim samples = 1000 Dim rgwData(samples) As UInt16 FDwfDigitalInStatusData(hdwf, rgwData, 2 * samples)
  9. 1 point
    Hi @Lesiastas, I moved your thread to a section where more experience Waveforms/AD2 engineers look. Also here is a forum thread that should be helpful for you. best regards, Jon
  10. 1 point
    Hi @PoojaN, Welcome to the digilent Forums! 1) Are you programming the QSPI flash through SDK or through Vivado? 2) Here is the Arty Programming Guide and the How To Store Your SDK Project in SPI Flash that should help depending on what type of project you are using. best regards, Jon
  11. 1 point
    Hi, check your options for bitstream generation. There is a clock frequency setting that determines the time it takes to move the data from flash to FPGA.