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Showing content with the highest reputation on 03/13/19 in all areas

  1. 1 point

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, I reached out to our content team about the default settings and how to change them for the generic SPI IP Core. To change the transaction width you will need to edit the DA3 IP in the IP Packager. Once that's open, double clicking on the SPI XCI in the sources pane will open it's customization wizard. The "Transaction Width" drop down can be set to 16 instead of 8. Click OK, merge changes to sources in the IP Packager, then Repackage the IP and close the packager. Update IPs in the host project and carry on as normal with the Pmod IP. Default settings are in the attached image - They created a default SPI IP using the generator and edited it in IP packager to get this screenshot. They do not know the effects changing C_NUM_TRANSFER_BITS would have on the drivers. If changes to the drivers are necessary, if changes are need to be made they expect that only the XSpi_Config instance in the Pmod's .c driver file would need to be changed. They believe that the asynchronous clock setting only really needs to be used when ext_spi_clk is not derived from the same clock source as the axi clock. If the Pmod IP guide is followed, the setting might be able to be disabled just fine, since both clocks will come from the same clocking wizard or MIG. Their best guess is that the main use case for the Async clock is for when the AXI Quad SPI is configured as a slave to a SPI master off of the board - all of the Pmod IPs use master mode SPI. thank you, Jon
  2. 1 point

    Pin Mapping for JTAG-SMT3-NC

    Hi @RussGlover, I apologize for the delay; the details you are looking are as follows: TCK - ADBUS0 TDI - ADBUS1 TDO - ADBUS2 TMS - ADBUS3 OEJTAG - ADBUS7 OESRSTN - ACBUS4 Let me know if you have any more questions. Thanks, JColvin
  3. 1 point

    Pmod DA3 clocking

    After going through the code posted in this thread, I want to amend my explanation of the 40 bits from yesterday. In the testperiph.c file, the DAC is being written at line 104. DA3_WriteSpi(&myDevice, 0x3A, &Hops_reading, sizeof(Hops_reading)); Hops_reading is a 32 bit value, so sizeof(Hops_reading) = 4. In PmodDA3.c, in the function DA3_WriteSpi(), the 4 gets passed as nData. The function prepends a 1 byte control word with address and write information. The function ends up writing all 5 bytes using the Xilinx SPI driver. 5 bytes * 8 bits per byte = 40 bits which is what you observed on the wire. void DA3_WriteSpi(PmodDA3 *InstancePtr, u8 reg, u16 *wData, int nData) { // As requested by documentation, first byte contains: // bit 7 = 0 because is a write operation // bit 6 = 1 if more than one bytes is written, 0 if a single byte is written // bits 5-0 - the address u16 bytearray[nData+1]; bytearray[0] = ((nData>1) ? 0x40: 0) | (reg&0x3F); memcpy(&bytearray[1],wData, nData);//Copy write commands over to bytearray XSpi_Transfer(&InstancePtr->DA3Spi, &bytearray, 0, nData+1); }
  4. 1 point

    Voucher for ARTY A7

    As a bit of further clarification, you would request any licenses from Xilinx, though it is my understanding that all of the Vivado WebPACK versions since 2016.4 or so are license free. I know that Digilent used to sell the original Arty board (now called the Arty A7) with a voucher for the Vivado Design Edition, but that was discontinued a few years ago (around the same time when Xilinx changed their own licensing policy and what was included in each edition). Thanks, JColvin
  5. 1 point

    FFT / iFFT / RS - Basys3

    @gummadi Teja, What you are asking for is not the common approach to building FFTs, therefore let me take this moment to invite you to build an FFT that uses the CORDIC algorithm without any multiplies. Let me also share with you what I think you will discover. While CORDIC algorithms do not use multiplies, they aren't necessarily logic efficient by any stretch of the imagination. Worse, CORDICs apply a gain to the incoming signal. Before you think this gain might be easily factored out since it applies to all incoming samples, let me remind you that there are two paths through each butterfly--one that would get the gain and one that would not. That brings you back to needing a multiply again. The FFT algorithm I linked to above does have an option that doesn't require hard multiplies (DSPs). Be aware, though, if you use this option the generator will build your multiplies from shifts and adds and this will cost you a lot of logic resources. Yes, I am aware of an alternative multiplication algorithm that I've come across that is very light on logic resources, but it also requires a delay equal to the number of bits in the multiply. That would slow the FFT processing down to (roughly) one sample every 54 clocks or so. Yes, the algorithm is similar to a shift-add multiplication algorithm, although about 2x less the area. While I've thought of integrating this into my own FFT design, no one has been paying for this upgrade so ... it may take a long while before I get to it. All that said, there's a saying in English that "Beggar's can't be choosers." If you really want a specific type of FFT implementation, you might be stuck with needing to build it yourself. Perhaps if you share more about why you are so interested in such an algorithm, and what engineering problem you are trying to solve, it might be easier to actually recommend a solution to your design problem. So far, you've been asking for an implementation, when I think what you need is a solution. The two are very different. Dan
  6. 1 point
    Thank you all for replying! @elodg Thanks for the tip! I was indeed using the vivado library IP core. From opencores I presume you meant this controller? https://opencores.org/projects/sdcard_mass_storage_controller If so, it does look promising, since it will basically be a direct hardware link to the SD card (if I am reading this correctly), currently it's running on the microBlaze and going through SPI. I just hope that the PmodSD supports the opencores controller. I registered there and hope to download and test the code soon! It appears to be written in verilog, hopefully that wont clash with my vhdl code. @MirceaDabacan Thanks for the explanation! I will search for some low power speakers to use with the AMP2 that I have right now since I couldn't find the max vpp specs of my JBL charge 2+. Your suggestion for the I2S2 is also a very interesting solution and if I do want to hook up a separate amplifier then I will definitely look into that module! @[email protected] Thanks for the suggestion! Creating a high speed buffer, with a much larger capacity than the RAM that is available on my basys 3 is very interesting! Considering that the data files are about 13 MB worth of samples per track, I could easily load the music from the SD card minute by minute, giving me ample time to continuously buffer during playback. Thanks for the support! Much appreciated! I will post back with my new findings! Jonathan
  7. 1 point
    Hi Jon, Thank you for your good advice. According to the tutorial here, I found that registers "slv_reg[1-4]" should not be written. Instead I prepared other register and change the read process of the register as follows: Insert these lines: signal my_in0_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); and -- Users to add ports here S_MY_IN0 : in std_logic_vector(3 downto 0); -- User ports ends and -- Add user logic here process( S_AXI_ACLK ) is begin if (rising_edge (S_AXI_ACLK)) then if ( S_AXI_ARESETN = '0' ) then my_in0_reg <= (others => '0'); else my_in0_reg(3 downto 0) <= S_MY_IN0(3 downto 0); end if; end if; end process; -- User logic ends And, change next line. -- reg_data_out <= slv_reg1; reg_data_out <= my_in0_reg; Anyway, my probrem is solved. Thank you very much. Shiro
  8. 1 point
    Hi @Shiro, Here and here are xilinx forum thread that discusses the multiple driver issue when making a custom IP. Here and here are a few ZYNQ tutorials that will help you with making a custom IP. thank you, Jon
  9. 1 point
    If memory on the Basys3 board is an issue, why not check out the HyperRAM PMod from 1-bit squared? It competes nicely with the traditional DRAMs, and easily adds on to the side of the Basys3 board. That would allow you to (slowly) load audio from the SD card, and buffer it in a massive external RAM for later (fast) use. Dan
  10. 1 point
    When you boot using the microSD card that you have prepared is the green led [LD12 DONE] turned on?
  11. 1 point
    In fact, I recommend either of the below: - use a speaker with Pmod Amp2 (without amplifier) - use Pmod I2S2, with external amplifier and speaker.
  12. 1 point
    Hi Jonathan, PmodAmp2 is a class D audio amplifier. Supplied with 3.3V (in conjunction with Basys 3), it generates an output voltage up to 6.6Vpp. The output signal will consist in only 3 levels: -3.3V, 0V, +3.3V. The load circuitry should filter the pulse modulated signal to an audio analog signal. The high input impedance of the speaker amplifier will not allow a high current. The voltage amplitude can eventually damage the speaker amplifier. Please check if this withstands a voltage of +/-3.3V (6.6Vpp). Reducing the “volume” of the digital signal would not help: the amplitude of the pulses will not decrease, just the duty factor… The next question is: how will you generate the signal to drive the Pmod Amp2. I see two possible options: Using an AD convertor Pmod (ex. Pmod DA2). The PmodAmp2 would be cascaded into Pmod DA2. Using a PWM modulator. In both cases, you can adjust the volume by multiplying the digital sample values with a “volume” constant.
  13. 1 point

    Support with the Pmod SD and Pmod AMP2

    Hello @Jonathan.O, SD cards usually only guarantee write bandwidth through class specifications. Usually we can extrapolate read performance too. However, all the performance levels are specified for SD native interface, not SPI. Since you mentioned library code, I suspect you are using the SPI-based IP from here: https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodSD_v1_0. Try an SD controller IP from OpenCores, see if it works better.