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Showing content with the highest reputation on 03/08/19 in Posts

  1. 1 point
    Hi @kwilber, Thank you for your input! Vivado 2018.3 does work with Ubuntu 18.04 LTS. My confusion came when I did not start with a simple project like blinky. Instead, in the Vivado Quick Start, I selected Open Example Project and tried to do the Base MicroBlaze example. In these templates you can only pick a default Xilinx development board but later in your Project settings you can select your Digilent board but then need to change your IP . . . it is a pain. Instead, if I pick Create Project in the Quick Start, I can then select my arty-a7-35. Also, the Vivado_init.tcl startup file does work and I don't need to add the Digilent board files to .../data/boards/board_files/. The other key issues with Ubuntu 18.04 LTS: don't use sudo to install Vivado but do use sudo to install the cable drivers!
  2. 1 point
    D@n

     DIFF_SSTL15 to TMDS_33

    @Ahmed Alfadhel, The real answer is that if you have both sys_clk and ddr3_sdram_ck* on the same bank, your pinout is still wrong. sys_clk is on a 3.3V bank, ddr3_sdram_ck* is on a 1.35V bank. If you give Vivado the wrong pins for these three wires, it will complain about the wrong voltage standard. Go back and set these pins to their right values. If you want a quick way to do this, consider using this UCF file to load the pin definitions directly into the MIG DDR3 SDRAM controller generator. Dan
  3. 1 point
    JColvin

     DIFF_SSTL15 to TMDS_33

    Hi @Ahmed Alfadhel, The DDR3 chip on the Arty A7 (datasheet link for the MT41K128M16) is designed to only operate at either 1.35V or 1.5V and as per the Arty A7 schematic the 1.35V configuration was chosen (you would have to change resistors around to adjust this configuration as mentioned on page 11) and is what our .prj file (github link) for the Arty A7 to configure the DDR3 and MIG IP uses as well. Going over the voltage input limit for the supply and IO supply voltages are limited to 1.45V (as per Table 41 on page 52 of the datasheet I linked) and if those maximum limits are exceeded, the input levels will be governed by DDR3 specifications (as per Note 5 on page 52), which limit the maximum supply voltages to 1.575V (with respect to Vss, as per Table 7 on page 26). Either way, using a clock signal that would be fed into the DDR3 chip that will go up to 3.3V will wildly overshoot the acceptable input levels (limitations detailed on page 57 in Table 46 of the datasheet, generally limited to 0.4V for a very small amount of time), effectively frying that pin on the DDR3 chip and possibly more. I would recommend carefully following voltage limitations of both the DDR3 chip and the Artix 7 if you are going to choose to configure and constrain the FPGA pins yourself. Thanks, JColvin
  4. 1 point
    Hi @CaptIgmu, Please download Adept 2 here. Please use the terminal command : # djtgcfg enum Here is a forum thread that discusses this situation with linux OS that might be helpful. thank you, Jon
  5. 1 point
    Vivado is pretty picky about having the correct folder structure. On my Centos system, the path to the Arty board files and the contents of the folder looks like the following. I have also observed the boards not being offered if the appropriate device family has not been installed. In the Help menu you can launch the "Add Design Tools or Devices" command. At the first dialog, press next to accept the current installation (eg Vivado HL Webpack). The next dialog allows you to select device families. Make sure the 7 Series and Artix-7 family is selected Also note that the Digilent supported version of Vivado is 2018.2 and not 2018.3.