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Showing content with the highest reputation since 03/04/19 in all areas

  1. 2 points

    Read from MicroSD in HDL, Write on PC

    Hi @dcc, I'm not certain how you are verifying that the HDL is writing to and then reading back from the SD card in a normal formatting style, but in general FAT32 is a widely used format for SD cards that has existing material for it. I am uncertain why you are using a special tool to write to the SD card though; from what I can tell the tool is Windows compatible, so why not just use the Notepad program which comes with Windows and save a .txt file with the data you are interested in reading to the SD card or just using Windows Explorer (the file manager) to move the file of interest onto the SD card? If you do have a header in your file, you will need to take account for that, though I do not know what you mean by "random file" in this case. Thanks, JColvin
  2. 2 points

    Genesys 2 DDR Constraints

    Hi JColvin, I am definitely not using ISE. I think JPeyron had it correctly. I didn't have my board.Repopaths variable set and so the project wasn't finding the board files. Once I set this variable as suggested, the pin mapping and IO types were auto populated as expected. Kudos, Sean
  3. 2 points
    @jpeyron @D@n I fixed the bug in my SPI Flash controller design. Now I can read from Flash memory.
  4. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  5. 2 points
    Hi, there's a lot of new information in your last post. You aren't just "trying" FPGA but have a professional interest in Zynq. Don't let anybody scare you it's "difficult" and go for it, possibly with the cheapest board, no tutorials and low expectations like, blinking LEDs for quite a while. Given the price tag of any industrial training coarse, an FPGA board for self-study is a no-brainer. Maybe save some money to buy your FPGA engineer a coffee once a week, with some questions in mind
  6. 2 points
    True. Zygot believes that making you work for knowledge is kinder than giving you solutions that can be used to mindlessly resolve your problem of the hour.... it's just a different philosophical bent...
  7. 2 points

    Pmod DA3 clocking

    It looks to me like DA3_WriteSpi() was adapted from code for a different device and has vestigial and incorrect code. Reviewing the AD5541A datasheet, several things stand out There is only a single register in the chip so there is no need for the u8 reg parameter. There is no need for a"config byte" to be sent before the data. The transfer is always 16 bits so there is no need to allow for arbitrary length data quoting from the datasheet "Input data is framed by the chip select input, CS. After a high-to-low transition on CS, data is shifted synchronously and latched into the serial input register on the rising edge of the serial clock, SCLK. After 16 data bits have been loaded into the serial input register, a low-to-high transition on CS transfers the contents of the shift register to the DAC register if LDAC is held low". Reviewing the PmodDA3 schematic, the ~LDAC signal is softly pulled to ground with a 10K resistor. So there is no need to explicitly toggle ~LDAC. What all this means is DA3_WriteSpi could be simplified to something like void DA3_WriteSpi(PmodDA3 *InstancePtr, u16 wData) { u8 bytearray[2]; bytearray[0] = ((wData & 0xFF00) >> 8); bytearray[1] = (wData & 0xFF); XSpi_Transfer(&InstancePtr->DA3Spi, bytearray, 0, sizeof(bytearray)); } You would then call it passing in just the instance pointer and the value you want to write to the DAC. u16 dacValue = 1234; DA3_WriteSpi(&myDevice, dacValue); I do not have a PmodDA3 on my bench so I cannot verify the function works, You can give it a try and let us know how it goes.
  8. 2 points

    Pin Mapping for JTAG-SMT3-NC

    Hi @RussGlover, I apologize for the delay; the details you are looking are as follows: TCK - ADBUS0 TDI - ADBUS1 TDO - ADBUS2 TMS - ADBUS3 OEJTAG - ADBUS7 OESRSTN - ACBUS4 Let me know if you have any more questions. Thanks, JColvin
  9. 2 points

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  10. 2 points

    Pmod DA3 Pinout

    That is one of the conventions commonly used to indicate an Active Low signal. So in this case, you pull Chip Select low when you want to access the chip. After you have toggled in all the data bits on the DIN line, you pull LDAC low. The Pmod DA3 reference manual has a link to the D/A chip's datasheet. That is the best first place to look for information on the device's function. The required signal timings are on page 5 of the datasheet.
  11. 2 points
    @Ahmed Alfadhel If you installed Vivado then you also installed the Xilinx Document Navigator. If you are serious about developing with FPGA devices you need to know how to find and access the plethora of documents that your vendor provides in order to use their devices properly. Check the box for 7 Series devices to see the list of reference manuals, User's Guides, Datasheets etc. From there you can add all relevant documents to your search and keep up to date. Do the same for ISE or Vivado tools. This is where everyone needs to start their Xilinx FPGA journey. Xilinx makes it easier than other FPGA vendors to obtain knowledge.
  12. 1 point
    My my... I'm not sure what LFSR you are using but mine have a shift enable input so that I can use any clock that's available but update the LFSR output at almost any update rate needed. You can create a counter to control the shift enable so that it's synchronous with whatever logic is running at 8 KHz and needs data at that rate. It's typical in a design to have lots of parts of the logic changing states at lots of different frequencies. You don't want separate clock domains for all of those rates even if those clocks are derived and phase coherent. Sometimes, for high speed applications you do need a higher, phase coherent clock; like in video where there might be a reference clock and a higher but synchronous pixel clock. In general it's best to have the minimum number of clock domains in a design that you can get away with. FPGA devices don't have long analog or combinatorial delay lines on the order of microseconds or milliseconds. The Series 7 devices do allow adding very small delays to signals coming into FPGA pins via the IDELAY2 primitive. If your device has outputs on pins on an HP bank you can also add similar small delays to output signals using the ODELAY2 primitive. Synchronous delays lines using counters and enables as I mentioned before are the normal way to achieve teh equivalent of the analog delay line that used to be part of some digital logic long long ago.
  13. 1 point
    @Ahmed Alfadhel, One other thing to note is your scope was AC coupled in your pictures so you were "seeing" a bipolar waveform of -1.28v to +1.28v. If you had DC coupled, the waveform on the scope would have shifted up and you would have observed the 0v to 2.5v the DA was outputting. To get an actual bipolar output, you need the opamp level shifter/scaler.
  14. 1 point
    @Ahmed Alfadhel To understand what's going on, check out table 8 of the datasheet on page 15. Basically, the DAC provides outputs between 0 and max, where 0 is mapped to zero and all ones is mapped to the max. In other words, you should be plotting your data as unsigned. To convert from your current twos complement representation to an unsigned representation where zero or idle is in the middle of the range, rather than on the far end, just toggle the MSB. Dan
  15. 1 point
    LOL yeppers! https://store.digilentinc.com/labview-physical-computing-kit-for-beaglebone-black-limited-time/ I've been struggling to dredge up my Unix experience from 30 years ago and apply it to this board as well as a RPi 3B+ in an effort to get them to run LabView. In the process, I had flashed the BBB's eMMC with the most current software only to find it broke LINX. I then back-rev'd the software to 8.6 2016-11-06 which seems to work so far. But, I'd like to know what it originally shipped with in order to fill out the revision continuum. -Scott
  16. 1 point

    Vivado free for Artix-7?

    Just as a reality check: To e.g. make a LED blink, the required CMOD A7-specific content is about five lines of constraints from CMODA7_Master.xdc. This may look more complicated than it actually is. And BTW, good choice, it's a great little board 🙂
  17. 1 point

    Cora Z7 Basic IO example problem

    Hi @Lost_In_Space, Welcome to the Digilent Forums! Please download Adept 2. 1) Can Adept 2 recognize the Cora Z7? Please attach screen shots of the Adept 2 text when the Cora Z7 is connected. 2) Are you using Linux? Windows? 3) Is the Mode Jumper JP2 set to JTAG? 4) How are you powering the Cora Z7? USB or external power source? best regards, Jon
  18. 1 point

    Passing FFT result to DDS

    @FR There are many ways to construct a sine wave. You could do a table lookup, or even a quarter table lookup. You could do a CORDIC. You could do a table lookup followed by a linear or even a quadratic interpolation. That part is the least of your worries. Your bigger problem is going to be the fact that short-time Fourier Transforms (STFTs, such as what you've just used), are not phase continuous in nature. As a result, depending on how you set up the overlap, you might find that every odd bin jumps 180 degrees of phase between transforms. Worse, if that wasn't enough, what happens if the incoming tone doesn't line up exactly on an FFT bin? This piece of reality has been known to kill a lot of poorly thought out FFT approaches. Something else to think about: Are you hoping to match the phase of the incoming sine wave? The phase delay through the FFT is both coarsely sampled and linear in frequency. I might suggest perfecting your algorithm off-line before even experimenting with it on an FPGA. I often use Verilator to accomplish both at once, although I know there's a large group of individuals who like using MATLAB for prototyping before moving to hardware. Dan
  19. 1 point

    VGA on Zybo

    Hi @Mukul, Here is a VHDL VGA project that has pixel clock frequencies for multiple resolutions. Here and here are non-digilent VGA tutorials. Here is a listing for different pixel frequencies and resolutions. best regards, Jon
  20. 1 point
    Hey @Phil_D I too had a problem with getting WaveForms to run automatically, and my group didn't find a way to make it work through the suggested code. However, we did have success when we commanded Python to simulate an F5 key press, which is a shortcut in WF to run the script. We used the library "uinput". Here's a sample of the actual command we used. I'm not certain that it's all you need, as I was not the primary Python programmer for this project, but at least it'll give you an idea of what needs to be done for this workaround. The sleep timers are there to give the program time to start and load the workspace. waveform_Call = subprocess.Popen("exec " + waveforms, shell = True) waveform_Call time.sleep(10) device = uinput.Device([ uinput.KEY_FN, uinput.KEY_F5, ]) time.sleep(1) device.emit_combo([ uinput.KEY_FN, uinput.KEY_F5, ])
  21. 1 point

    ZYBO HDMI IN project

    Hi @birca123, I got the same errors when I loaded the applications. Looking at the last line says that the "BSP Project P/HDMI_IN_bsp has been successfully migrated" is a good thing. I was able to program the FPGA, run the application and the project to worked. I have updated the above linked HDMI project with my sdk portion done as well. I have also attached my SDK log so you can compare it to what you have. best regards, Jon SDK_LOG_HDMI_IN.txt
  22. 1 point

    ZYBO HDMI IN project

    Hi @birca123, I would suggest to start with a fresh sdk portion of the project. To do this close SDK and delete the hdmi-in.sdk folder in the \Zybo-hdmi-in\proj folder. Then in vivado click file->export -> export hardware including the bitstream. Then launch SDK from Vivado by clicking in file and selecting launch SDK. Once in SDK and the HW platform is loaded click in file and import HDMI_IN and HDMI_IN_bsp from Zybo-hdmi-in\sdk. Once you have the HDMI_IN and HDMI_IN_bsp into your SDK project then program the FPGA Next open a serial terminal emulator like tera term and connect to the Zybo's com port. Set the baud rate to 115200 everything else should be left at default settings. Now connect the Zybo to the HDMI and VGA device. then in SDK right click on HDMI_IN and select run as->launch on hardware(system debugger). Do you see the serial terminal menu? Is there an image on the VGA device?
  23. 1 point

    ZYBO HDMI IN project

    Hi @birca123, The easiest why to use a newer version is load the project in the intended version , in this case Vivado 2016.4 and then open it in the desired Version of Vivado. Then upgrade the ip's and alter any xdc pin names that might have changed when the HDMI IP's were updated. Here is a project where I have upgraded the project to Vivado 2018.3. The project can be found in the proj folder. I did not validate that the project worked with SDK and Monitors but the Vivado project generated a bitstream. So you should only need to export the hardware including the bitstream launch SDK and import the HDMI applications. best regards, Jon
  24. 1 point

    Read out .log file from OpenLogger

    Hi @Peggy, I spoke with some of the firmware folks for WFL and OpenLogger and learned that they haven't yet implemented the parsing of the header into the Digilent agent yet. I did receive a picture that showed the structure of the header file, which I have attached below. Thanks, JColvin
  25. 1 point
    Well geees. In typical fashion as soon as I expose my ignorance, I answer my own question. What I should have been using is the "Latch". This works like I had expected assigning a port would have. LATGbits.LATG6 = 1; LATGbits.LATG15 = 1;
  26. 1 point
    Hi @callum413 Tomorrow beta build will support time stamp identified by the software. High precision timer is not available in the device.
  27. 1 point
    gummadi Teja

    FFT / iFFT / RS - Basys3

    thank u sir i complete my code for fft using cordic algorithm..
  28. 1 point

    Pmod DA3 clocking

    Inside the AD5541A, the MOSI bits get clocked into a shift register and are held there until the ~CS line goes high. At that time, the bits are transferred from the shift register to the D/A. It does not matter what level is on MOSI at that instant. In the traces I posted earlier, I included a transition from full scale output to 0. I also show several cycles of writing all possible values in a ramp. The resulting voltage waveform shows the AD5541A is seeing the data correctly. The last four writes to the pmod in the zoomed trace show sending the values 0, 1, 2 and 3 to the D/A. You can observe SCLK's transition in relation to the least significant bits of the data. SCLK is not transitioning when ~CS transitions to high so the data on MOSI is "don't care" at that instant. I did use different clocks since the microblaze can run at higher clock rates than the AD5541A. Also, when you are troubleshooting, it can sometimes help to slow down the logic. I see you are using pmod connector JB whereas my project used JA. Just as a test, you might want to try moving your PmodDA3 to JA and use my project as is to replicate my results. You should be able to launch vivado, open my project then immediately launch the SDK from vivado. You should not have to generate a bitfile. I had included the hardware handoff in the zip file I gave you so you have my exact bitfile. Once the SDK loads, it should automatically load the project and compile it. At that point you can program the fpga from inside the SDK and then run my example app. You should see a sawtooth waveform coming out of the PmodDA3 if all is well.
  29. 1 point
    Hi, >> applying various algorithms if you don't know the algorithms yet, it might be easier to get the ADC data into a softcore CPU, then prototype in C using floating point. The point is, experimental prototyping of algorithms in fixed point RTL is a slow and painful process.whereas reloading a .elf binary takes a second. I'm guessing your intent but I suspect you'll find eventually that an FPGA is not the optimal platform choice for your application. Meaning, you can most likely get the same result cheaper and with less effort e.g. using a Raspberry PI + SPI converter. I'm guessing this simply because higher-rate ADCs where FPGA makes sense (hundreds of MHz) are hard to come by as OTS modules. Otherwise, if you design for, say, 1 MSPS, the FPGA fabric will do less than 1 % of the work it could do but you pay for 100 % so people usually don't use FPGA, if a CPU or DSP will do the job.
  30. 1 point

    Pmod DA3 clocking

    I forgot you were using an Arty. I will retarget my project to use an Arty A35 and will then post it.
  31. 1 point

    Pmod DA3 clocking

    I obtained a DA3 and was able to get it working. Here are some pictures of my setup. I am limited by how big the attachments are so I will post again with an archive of the project I used.
  32. 1 point

    Support for Custom FPGA Board Design

    @hello.parth, You are quickly going to run into the problem that Digilent holds its configuration logic to be proprietary. It's not shown on the board schematic. (I haven't asked them, though, if they'd ever sell this information ...) Regarding reading the configuration from flash, that part of the design can usually be found on their boards. Each Xilinx FPGA has a specific set of pins for the configuration flash. Use those pins, and set the appropriate mode pins for loading from flash, and you should be good. Loading from JTAG is a bit more difficult. While you don't need to adjust the mode pins to switch from SPI loading to JTAG loading, you'll still need to figure out how to hook up the FTDI chip and that's the part of the Schematic that's missing on the Digilent boards. Let me suggest that you instead copy the JTAG+UART portion of the design from the Max-1000 circuit board from Trenz. If you dig a little deeper, you'll quickly discover that FTDI is so committed to supporting FPGA designs that they also have demonstration designs showing how to use JTAG when using their chips. If worse comes to worse, you can at least load a design via an FTDI chip using the open source libxsvf driver. Dan
  33. 1 point
    @Jonathon Kay, The short answer to your question is that, Yes, you can. I self learned on the Artix 7, and later on Altera's ARM+FPGA board, the Cyclone V. It is doable. The long answer to your question is that there are a lot of things to learn, and not all of them are easily self taught. Particular lessons include not only the language itself (I also recommend Verilog), but you should also have a good understanding of clock crossings (what they are and how to manage them), design to resource mapping (this can be learned through trial and error--pay attention to how much logic your design uses), how to correct timing problems (you can wait 'til you get some, and write back here for help if need be), how to connect to external pins for both inputs and/or outputs (PMods are good for this), as well as how to design a component using the AXI bus. I recommend learning how to use AXI-lite first, but the reality is--if you want to use a Zynq device, you'll need to be able to make and integrate AXI peripherals and AXI-lite is a whole lot easier than just AXI. You'll also need to learn very quickly that FPGA designs are not nearly as easy to debug as software designs--to include microcontroller designs. Most early/beginner lessons discuss how to use LEDs to debug a design. These are great for your first lesson or two, but you'll quickly outgrow them. Make sure you take some time to learn the other debugging methods available to you, or you will really struggle to get any significant design working. Remember, the simulator is your friend. Learn how to use it early, and use it often. Further, when you get to the point where you want to build an AXI peripheral, I strongly recommend having an understanding of formal methods. These come for free with Verilog, not so much with VHDL or SystemVerilog. (It's amazing how easy it is to debug someone else's AXI-lite core using formal methods ... your own core would be easier.) Just my two cents, Dan
  34. 1 point
    Hi @kmesne, We responded to your other question here with some detail, but I will try to elaborate a little bit more here. The Pmod COLOR is not intended to detect colors from any sort of distance, so you would need it next to the red/green light indicator and then have it transmit data to the main controller for the car as opposed to be mounted on the car (unless the red/green indicator was on the car itself). I believe the Pmod COLOR could detect the green in a green cube, but it would need to be fairly well lit up due to the limitations of the sensor itself. As a bit of perspective, this will be a large and non-trivial state machine (especially for first semester project) with a lot of conditions to be covered; is light red or green to control the enable bit on 2+ H-bridge drivers running the motor, which needs to be checked frequently in order to obey traffic laws, as well as the enable bit being toggled as appropriate when changing input directions if the vehicle can go in reverse to avoid burning out the h-bridges, pwm control over the enable pin to allow the vehicle to turn; all done over (presumably) 3 remote systems communicating with each other; the controller with the direction buttons, the color sensor detecting the light change, and the RC vehicle itself. Which system/input will have priority in the state machine and how often will you need to check each input to provide a "smooth driving experience" will all be things that you need to consider. Some good resources for VHDL basics can be found at asic-world.com and fpga4fun.com, as well as this page that discusses state machine construction in VHDL. Thanks, JColvin
  35. 1 point
    it looks like the file PmodOLEDrgb_axi_quad_spi_0_0.xcix is there, but not in the correct folder - will advise if it works after I copy the files to expected folders
  36. 1 point
    Thank you all for replying! @elodg Thanks for the tip! I was indeed using the vivado library IP core. From opencores I presume you meant this controller? https://opencores.org/projects/sdcard_mass_storage_controller If so, it does look promising, since it will basically be a direct hardware link to the SD card (if I am reading this correctly), currently it's running on the microBlaze and going through SPI. I just hope that the PmodSD supports the opencores controller. I registered there and hope to download and test the code soon! It appears to be written in verilog, hopefully that wont clash with my vhdl code. @MirceaDabacan Thanks for the explanation! I will search for some low power speakers to use with the AMP2 that I have right now since I couldn't find the max vpp specs of my JBL charge 2+. Your suggestion for the I2S2 is also a very interesting solution and if I do want to hook up a separate amplifier then I will definitely look into that module! @D@n Thanks for the suggestion! Creating a high speed buffer, with a much larger capacity than the RAM that is available on my basys 3 is very interesting! Considering that the data files are about 13 MB worth of samples per track, I could easily load the music from the SD card minute by minute, giving me ample time to continuously buffer during playback. Thanks for the support! Much appreciated! I will post back with my new findings! Jonathan
  37. 1 point
    Hi Jon, Thank you for your good advice. According to the tutorial here, I found that registers "slv_reg[1-4]" should not be written. Instead I prepared other register and change the read process of the register as follows: Insert these lines: signal my_in0_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); and -- Users to add ports here S_MY_IN0 : in std_logic_vector(3 downto 0); -- User ports ends and -- Add user logic here process( S_AXI_ACLK ) is begin if (rising_edge (S_AXI_ACLK)) then if ( S_AXI_ARESETN = '0' ) then my_in0_reg <= (others => '0'); else my_in0_reg(3 downto 0) <= S_MY_IN0(3 downto 0); end if; end if; end process; -- User logic ends And, change next line. -- reg_data_out <= slv_reg1; reg_data_out <= my_in0_reg; Anyway, my probrem is solved. Thank you very much. Shiro
  38. 1 point

    Pmod DA3 clocking

    The address bits being sent should not pose a problem since ~LDAC gets pulled low after the data bits have been sent and that will transfer the last 16 bits clocked into the serial register to the DAC. Admittedly, since the chip doesn't use the address bits, it is wasted time. That is one of the cons when using third party IP - generality usually costs either performance or resources. If you run into performance limitations, you would then consider coming up with your own logic for talking to the chip. In this case, the protocol is fairly simple.
  39. 1 point

    Support with the Pmod SD and Pmod AMP2

    If memory on the Basys3 board is an issue, why not check out the HyperRAM PMod from 1-bit squared? It competes nicely with the traditional DRAMs, and easily adds on to the side of the Basys3 board. That would allow you to (slowly) load audio from the SD card, and buffer it in a massive external RAM for later (fast) use. Dan
  40. 1 point
    In fact, I recommend either of the below: - use a speaker with Pmod Amp2 (without amplifier) - use Pmod I2S2, with external amplifier and speaker.
  41. 1 point

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, I have reached out to our content team about your Legacy, Enhanced or XIP mode question. If I were guessing i would say that its the Enhanced mode since the interface is set to AXI4 but I am not sure. thank you, Jon
  42. 1 point

    Hi to all

    Hi @RISC, Welcome to the Digilent forums! Here is the Basys MX3's resource center. cheers, Jon
  43. 1 point

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, In section 2 Interfacing with the Pmod on page 1 of the reference manual for the Pmod DA3 here it states the pmod should use spi mode 0. thank you, Jon
  44. 1 point
    Hi @kwilber, Thank you for your input! Vivado 2018.3 does work with Ubuntu 18.04 LTS. My confusion came when I did not start with a simple project like blinky. Instead, in the Vivado Quick Start, I selected Open Example Project and tried to do the Base MicroBlaze example. In these templates you can only pick a default Xilinx development board but later in your Project settings you can select your Digilent board but then need to change your IP . . . it is a pain. Instead, if I pick Create Project in the Quick Start, I can then select my arty-a7-35. Also, the Vivado_init.tcl startup file does work and I don't need to add the Digilent board files to .../data/boards/board_files/. The other key issues with Ubuntu 18.04 LTS: don't use sudo to install Vivado but do use sudo to install the cable drivers!
  45. 1 point

     DIFF_SSTL15 to TMDS_33

    @Ahmed Alfadhel, The real answer is that if you have both sys_clk and ddr3_sdram_ck* on the same bank, your pinout is still wrong. sys_clk is on a 3.3V bank, ddr3_sdram_ck* is on a 1.35V bank. If you give Vivado the wrong pins for these three wires, it will complain about the wrong voltage standard. Go back and set these pins to their right values. If you want a quick way to do this, consider using this UCF file to load the pin definitions directly into the MIG DDR3 SDRAM controller generator. Dan
  46. 1 point

    Conflicting Voltages in Bank Arty-A7

    @Ahmed Alfadhel, That "machine readable" board XML file for the Arty is actually pseudo-human readable. Feel free to download it. The current link for those files appears to be here. You might find it with a ".prj" extension. @zygot, It looks like the Digilent staff took my advice/suggestion and moved this into its own thread. (Thank you!) That would be why you aren't seeing the (irrelevant) history any more. Dan
  47. 1 point

    Digital Twin

    Hi @Kris Persyn, It depends on how you manage your resources, driving immersive visuals on a HDMI display can be done in multiple ways at different resolutions, some are PL taxing others are DDR taxing; you could generate entire frame buffers in PL or PS or you could find a optimal algorithm to change just the previous frame or you could allocate a high number of frame buffers and then run them in a loop. It also depends on how math lab synthesizes the IP you will need to add to your design. If you design your project properly and don't aim for a resolution higher more 720p( I'm being conservative, we managed to drive the HDMI at 1080p with processing filters without a problem) I think it should be enough for what you want to do, resource wise. My suggestion, download and install Vivado, download and install the board files, create and implement your project look at the resource consumption and then buy a board. - Ciprian
  48. 1 point

    DAC Pmod DA3 on Spartan 3 Starter Kit

    Hi @lwew96, Here is a VHDL Pmod DA3 project done by a community member @hamster that is made in vivado with the Basys 3. To make this project work with the spartan 3 you will need to use the xdc file as a reference for the spartan 3's ucf file. cheers, Jon
  49. 1 point

    0V5640 5MP Camera FPGA Board

    Hi @DFL, We have the Pcam 5C here that uses the Omnivision OV5640 5 megapixel (MP) color image sensor. The Zybo Z7 (either the Z7-10 or Z7-20) works with the Pcam 5C through the MIPI CSI-2 interface. There is a demo using the Pcam 5C and the Zybo-Z7 here. We have the Pcam 5C IP Core here. thank you, Jon
  50. 1 point

    MMCM dynamic clocking

    Hey, something else I just saw when reading the clocking guide was: MMCM Counter Cascading The CLKOUT6 divider (counter) can be cascaded with the CLKOUT4 divider. This provides a capability to have an output divider that is larger than 128. CLKOUT6 feeds the input of the CLKOUT4 divider. There is a static phase offset between the output of the cascaded divider and all other output dividers. And: CLKOUT4_CASCADE : Cascades the output divider (counter) CLKOUT6 into the input of the CLKOUT4 divider for an output clock divider that is greater than 128, effectively providing a total divide value of 16,384. So that can divide a 600 MHz VCO down to 36.6 kHz.