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Showing content with the highest reputation on 02/20/19 in Posts

  1. 1 point
    @khaledismail, I agree with @jpeyron somewhat. I think you have at least two bugs in your design. One of them is that your VSYNC/HSYNC signals and pixel rate aren't necessarily matching the screen resolution you are trying to create. The second bug is that your block RAM values aren't synchronized with your VSYNC/HSYNC signals. All of these can be easily discovered through either formal verification or extended simulation. If you go the simulation route, your goal should be to repeat that image within the simulator, then you'll have all the "evidence" you need to find the bug. Dan
  2. 1 point

    Zybo Z7 Development Board ESD&Safety

    @Sduru All electronic equipment is susceptible to ESD damage. Especially, on a board like yours with components exposed. Especially, if you are not using it in an environment where humidity is controlled. If you were working in such a controlled environment at a company, using company equipment, they would ( should ) require you to work on an ESD pad with a wrist band that has a qualified ESD to ground path to leak off ESD currents. And that's in a lab environment where the possibility of static discharge is minimal. If you are working at home and on a desk with a carpeted floor in the winter when heating is likely to make static a relatively likely possibility then I would suggest that buying a small ESD mat and ground strap is a worthwhile investment. You can damage your equipment without causing it to fail catastrophically. Yes you can be lucky enough to ignore well established and proper electronic handling guidelines without having an issue ( or more likely not being aware that you've had an issue ) but ignoring well established and proper guidelines is just a bad idea. You can get away with a lot of risky behavior for a while but sooner or later the piper will send his bill and you will pay. As a general rule you should never touch components on a PCB; at least without proper grounding. But even if you are very careful to move a board by the edge or shielded connectors like Ethernet RJ45 jacks that are grounded you can still zap components if you've built up enough static charge. You've asked a very good question. I understand that there are people who will choose to ignore this advice but I've given you an answer that is consistent with professional practice. Expensive electronic development kits don't come in a anti-static bag with a seal that is supposed to break when you open it for no reason even though it cost more for the vendor to do this. BTW ESD mats are high resistance affairs that are design to leak off static charge to a good ground ( this might not be available where you are working at home ) without endangering you to high voltage low impedance sources. Thought I'd mention this for anyone thinking that they might make their own cheap workstation....
  3. 1 point

    PMOD MTDS text font sizes

    Ah, yes - thanks. I should have paid more attention to the manual! Thank you for looking into this and providing the answer.
  4. 1 point

    Cmod S6 - Multilayer?

    It's easy, even for well trained people to develop mistaken ideas about PCB design. I've been involved with PCB design for digital and analog signals up to about 3 GHz. The analysis and rules for UHF or microwave is very different than that for 100 MHz. I'm very reluctant to make any broad generalizations that might be interpreted as guidance. I'm not countering the advice of @xc6lx45; just making a comment. Yes, I agree that you can find very good guidance from IC manufacturers who want their customers to be happy with the performance of their devices. Often very good general rules are available as application notes or EVM board design files. Some take great care in explaining why they chose to place parts, panes, traces, etc. the way they did. I never ignore such help. Designing a PCB to mitigate radiating energy in controlled spectrum is a bit different than thinking about designing a PCB to be less susceptible to external radiation. Often susceptible circuitry is shielded by a cage. You can find these on many a Xilinx development board. From the perspective of a PCB as a victim of electro-magnetic radiation I couldn't put a boundary on the frequency range of interest. Warning, long old man tale follows: I may have mentioned this in another post but many years ago I interviewed for a job with a high-end modem company. One of the engineers who took me for a tour explained how he had changed the whole philosophy of board layout by eliminating all planes and just having return traces to provide a path for return to ground currents from every component. After a long discourse he asked what I thought of his idea. I had to tell him that it really didn't make much sense or conform to what I had already learned. We had a brief discussion about this but who wants to get into a brawl with some nut interviewing you for a job? Later interviews with higher level managers confirmed that everyone in the company was grateful for the new direction for a number of reasons. Needless to say that, since I didn't choose to drink the cool aid , I wasn't considered a suitable candidate for a position with that company. Many years later I had an interview with another company and during a discussion with one of the engineers I found myself relating this prior experience. The guy interviewing got all red in the face and after a bit of silence told me that he was the engineer responsible for that change in design theory and that it ended up being a fiasco. He mentioned that he missed a few things in his analysis. I didn't make a suitable candidate for that company either.... If you are going to design a PCB or use a high performance component then you better avail yourself of all the reliable information you can find. Better yet work for a company that has years of success doing verifiable products that meet specifications under rigorous testing. For most of us general rules of thumb will do for the kinds of boards that we can afford to make. There are a few good texts but IC and microwave and RF component manufacturers still supply good advice if you can find it.
  5. 1 point

    Cmod S6 - Multilayer?

    You might go to Texas Instruments' site (or AD or both) and find documentation for some $500 high frequency ADC or DAC eval board as example to study.. There's nothing wrong with copper planes, generally. Free-standing structures (such as non-connected filler polygons) can be bad, if they resonate. So are loops if the driving wire spans an area together with the GND return wire (for which the ground plane is an obvious solution). The worst resonators have high quality factor meaning loose coupling meaning it can be surprising how the energy managed to couple in. There's no such thing as too many ground vias... Note, your ground plane can do very interesting things in combination with the metal box it's in (resonant cavity) but that's a different story.
  6. 1 point
    Hi @Danny Armstrong, 1) make sure you have added the vivado library to the ip repository by clicking into the project setting and selecting ip and adding the path to the vivado library on your PC in the IP Repository. 2) It is my understanding that you can add the pmod ip cores to the block design by clicking the add ip button and type pmod then select which pmod you would like to have added to the block design. thank you, Jon
  7. 1 point

    Cmod S6 - Multilayer?

    Uh Oh... you're prying open a can that a lot of people would rather not see opened. When I think of EMC I'm usually concerned with electromagnetic transmission by the product. If you buy just about any evaluation, demo or development board from major vendors, like Xilinx, you'll find some verbiage somewhere that the product in question does not conform to FCC rules and regulations and is only to be used in a lab setting ( let me say that this is a very poor paraphrase here ). You won't see that kind of verbiage anywhere in the packaging or user's manual of FPGA development boards like the ones discussed on this forum. My guess is that there's no such testing and it's gone unnoticed by the relevant organizations. Of course EMC has victims as well as aggressors ( forgive me if I get the lingo wrong.. it's been a while since I spent time in an EMC test chamber ). You are interested in what kind of effect an EMC aggressor might have on, say a CMOD6. I'd say you and a lot of other people; some with 'friendly' agendas and some not. Certainly if you wanted to send your CMOD6 on a mission to the moon you'd have to consider this. You'd also have to consider those very high energy Alpha particles flying about. For a while now IC vendors have been accommodating, to a limited extent, the Apha particle situation, mostly for high altitude aviation applications. FPGA devices and a lot of MCU devices have an SEU to detect such events. I'm quite sure that there are a lot of other radiation types an astronaut using your CMOD6 would need to be concerned about. Generally, for extreme environment applications these types of concerns are dealt with on a system as well as component level. If you scrounge around there are application notes on this topic. Start with Actel (Microsemi) as they are big in the 'non-terrestrial' market. Hmmm.. you're on to asking questions about a class of very interesting related topics for investigation.... [edit] One thought that just occurred to me... is that you might want to use an FPGA platform where the gerbers are available as this would provide a wealth of information.
  8. 1 point

    Vivado Bitstream Generation

    Hi @Hunaina, Have you tried reaching out to the two people maintaining the project here or here for more information about their Test Bench? The Test Bench may have initially be referring to function "int init_calltf(char*user_data)" in aes_init.h and the function "init_reset_calltf(char*user_data)" in aes_init_reset.h. Might try changing the $init to $init_calltf("probably a global Char *"); and init_reset_calltf("probably a global Char *"); thank you, Jon
  9. 1 point

    Cmod S6 - Multilayer?

    Consider that the FPGA on your module has 196 balls. The A7 versions have 236. You can answer your own question by thinking about how one gets all of those surface mount pads to ground, voltage and signal traces.
  10. 1 point

    Cmod S6 - Multilayer?

    Hey @TireV What your are referring to is called the stack-up and refers to the layers of non-conductive prepeg material and copper plating that makes the planes and signal traces. You are correct that as a user of the CMODS6 ( or any small form module for that matter ) has an interest in this part of the board. The thickness of the module is not necessarily proportional to the number of layers. What is important is how much and how thick the copper on the prepeg layers is because large ground or voltage planes thermally connected to the IC substrate are the only route for thermal energy to be 'wicked' away from the active devices on the module. More layers is not necessarily better. PC motherboard manufactures for a while there saved cost by using 2 layer boards but there is a lot of engineering and expensive tools required to do this right. I responded to your question because it's not just a good question but a nice segue into this comment that you brought to mind. FPGA timing performance is temperature dependent. There are industries that like miniaturized high performance modules and take extreme efforts to minimize and or manage heat. These are very expensive. These modules also [should] come with very detailed testing results that indicate what the upper level of performance the modules can handle and how much heat it dissipates into the system. When someone offers you a very cheap and tiny module you can assume that thermal issues are something to keep in mind when you use it. It's not just performance that heat has on and FPGA but longevity as well. I happen to very much like and uses the CMOD-A7 modules, as well as other modules from other vendors. I also keep in mind that it's possible to run into thermal problems if I expect too much out of them. But, like a speciality tool; when you need it it's nice to have around. I have no expectation that a vendor of cheap modules tests much less would specify in their advertising performance, environmental, or thermal information. If I was buying a $100K module with an FPGA then I would insist on this information. So I offered a narrow slice of a proper reply to your question. I do encourage you to lean more... the information is out there, often as documentation on EVMs that will supply all of the PCB design information as well as the guidelines that were followed in making them.