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Showing content with the highest reputation on 02/11/19 in all areas

  1. 1 point
    Hi @zygot, The Rubber duck debugging method! Hi @Archana Narayanan, I didn't see anything directly wrong with your VHDL code. I would suggest breaking down the project and verify each major component I.E. the FIFO, UART and the ADC. thank you, Jon
  2. 1 point
    And.... I have this sense that if you keep describing what you did you will answer your own question. I don't have enough information yet to help. [I confess that I haven't bothered to read through your code] Verbalizing problems, if you go into enough detail, is often a fairly reliably way to resolve them. Sometimes it helps to have someone throw in a good question or two.
  3. 1 point
    Welcome to debugging, where things get interesting and your work grades your design effort. Hopefully, you don't have too much confidence in any such assertions like the one above. I find myself in your position more often than I'd like to admit. Sometimes it turns out to be something completely unexpected... usually it ends with a slap on the forehead and DOH! You idiot!... Fortunately, we're working in the PL so there are options, Hopefully you have a few spare IO pins. Just as a sanity check I'd bring out the TxD and RxD internal signals to new GPIO that I'd name dbg_xxx. These can be observed wiht a scope or since I always have a few TTL USB UART cables or modules lying around try to loop back communication to a second COM port in my PC. I'd certainly try getting the PC to talk to one of your boards directly through your current pin assignments.Pay careful attention to signal directionality and be sure to avoid two sources driving any pins which could be easy to do. I might use a mux in the PL controlled by a physical switch to help with that. I never ask myself "DO I have to draw you a picture?" because usually the answer is yes... Your brain might be wired differently. Have you verified that the current signal IO standards are correct? It might not hurt to revisit the Zynq documentation for moving PS UART pins to the PL... this isn't always totally straightforward. [edit] Oh, and I forgot to mention that when things get really confusing I plod through all of the Synthesis and P&R messages. Sometimes Vivado and I aren't understanding each other the way that I assume we do. If I were smarter, I'd probably do this step after each bitstream production... but I want to keep moving...
  4. 1 point
    kotra sharmila

    sdsoc_opencv error

    Hi , Thank you very much for this platform its showing video i/o demo and build perfectly i will try with my own project if i got any doubts i will ask you. Regards, K Sharmila
  5. 1 point
    zygot

    Cmod S6 - Multilayer?

    Consider that the FPGA on your module has 196 balls. The A7 versions have 236. You can answer your own question by thinking about how one gets all of those surface mount pads to ground, voltage and signal traces.
  6. 1 point
    laughing out loud ... Formula-1-performance is niche business, combine harvesters bring home the money, walking barefoot is the norm. And why not, I'm even discouraging people to touch it as long as a UART does the job. Same as with fast cars, speed is largely overrated. Those who know otherwise, you know who you are 🙂
  7. 1 point
    I'm having a hard time comprehending how this project has gotten only 200 or so looks and my demo project has 10X that. I suspect that views may not be a good metric for interest. No one's talking but I surmise that people (students) are getting some utility out of the terminal based UART user interface that I provide. I certainly do. Who knows? Will anyone take the time to provide feedback? Is there a Multiverse?