Welcome to debugging, where things get interesting and your work grades your design effort. Hopefully, you don't have too much confidence in any such assertions like the one above.
I find myself in your position more often than I'd like to admit. Sometimes it turns out to be something completely unexpected... usually it ends with a slap on the forehead and DOH! You idiot!... Fortunately, we're working in the PL so there are options, Hopefully you have a few spare IO pins. Just as a sanity check I'd bring out the TxD and RxD internal signals to new GPIO that I'd name dbg_xxx. These can be observed wiht a scope or since I always have a few TTL USB UART cables or modules lying around try to loop back communication to a second COM port in my PC. I'd certainly try getting the PC to talk to one of your boards directly through your current pin assignments.Pay careful attention to signal directionality and be sure to avoid two sources driving any pins which could be easy to do. I might use a mux in the PL controlled by a physical switch to help with that. I never ask myself "DO I have to draw you a picture?" because usually the answer is yes... Your brain might be wired differently.
Have you verified that the current signal IO standards are correct? It might not hurt to revisit the Zynq documentation for moving PS UART pins to the PL... this isn't always totally straightforward.
 Oh, and I forgot to mention that when things get really confusing I plod through all of the Synthesis and P&R messages. Sometimes Vivado and I aren't understanding each other the way that I assume we do. If I were smarter, I'd probably do this step after each bitstream production... but I want to keep moving...