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Showing content with the highest reputation on 01/10/19 in Posts

  1. 1 point
    D@n

    NEXYS 4 Programming Flash

    @bhall, No, this makes perfect sense. Xilinx, in their infinite wisdom, created a SPI port clock pin to be used for configuring the device. It's controlled internally. When they then realized that customers would want to use it as well, they created a STARTUPE2 primitive that you need to use to get access to it. As such, its often not listed in the port lists, but still usable. On several of the newer Digilent designs, Digilent has connected that pin to two separate ports. This allows you to control the pin like a normal I/O. However, doing this requires special adjustments at the board level--not the chip level. Dan
  2. 1 point
    Hi @Suavek, Welcome to the forums. We have a completed project for the Zybo Z7 project using the PCAM-5C. thank you, Jon
  3. 1 point
    D@n

    NEXYS 4 Programming Flash

    @bhall, You should thank @jpeyron for calling me out. I tend to ignore any threads with block diagrams in them--I just don't seem to be able to contribute to them that well. @jpeyron also cited the wrong reference to my article (Oops!). I think he meant to cite this article here on flash controller development. In general it's not really all that hard to do--you just need to spend some time working with the specification and your hardware, and a *really* *good* means of scoping out what's going on. The design built in this article assumes a DDR output. As such it can read a 32-bit word in (roughly) 72 system clocks. I have an older QSPI controller as well that I've used on many of my flash designs. It takes up twice as much logic. The link above should show you where and how to find it if you would like. This one doesn't use the DDR components. The other trick in what you are attempting to do will require you to read an ELF file. Check out libelf for that purpose. It's really easy to use, and should have no problems parsing your executable file--before it turns into an MCS file. Hope this helps, Dan
  4. 1 point
    Hi @Sami Malik, Here is a link for using Block Ram in Verilog with Vivado. I have used IP Cores with a verilog top file like in the Zybo XADC demo. If you are also using the zynq processor then i believe you would need to use the IP Core along with controlling it from a SDK application. thank you, Jon