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  1. 3 points
    Ciprian

    Digital Twin

    Hi @Kris Persyn, It depends on how you manage your resources, driving immersive visuals on a HDMI display can be done in multiple ways at different resolutions, some are PL taxing others are DDR taxing; you could generate entire frame buffers in PL or PS or you could find a optimal algorithm to change just the previous frame or you could allocate a high number of frame buffers and then run them in a loop. It also depends on how math lab synthesizes the IP you will need to add to your design. If you design your project properly and don't aim for a resolution higher more 720p( I'm being conservative, we managed to drive the HDMI at 1080p with processing filters without a problem) I think it should be enough for what you want to do, resource wise. My suggestion, download and install Vivado, download and install the board files, create and implement your project look at the resource consumption and then buy a board. - Ciprian
  2. 3 points
    In your constraint file, the ddc pins have lowercase "ddc_scl_io" and "ddc_sda_io". Your block design has the port in uppercase "DDC". The case must match. Try editing your constraint file to have "DDC_scl_io" and "DDC_sda_io".
  3. 3 points
    jpeyron

    pmod wifi

    Hi @harika, I believe the HTML web page error is related to the materials on the SD card. 1) Please attach a screen shot of the contents of the Sd card you are using. 2) Please follow the YouTube video here from about 6 minutes and 28 seconds on for how to set up the HTTP server project. Make sure to update the login an password for the router/modem you are using. thank you, Jon
  4. 2 points
    JColvin

    Read from MicroSD in HDL, Write on PC

    Hi @dcc, I'm not certain how you are verifying that the HDL is writing to and then reading back from the SD card in a normal formatting style, but in general FAT32 is a widely used format for SD cards that has existing material for it. I am uncertain why you are using a special tool to write to the SD card though; from what I can tell the tool is Windows compatible, so why not just use the Notepad program which comes with Windows and save a .txt file with the data you are interested in reading to the SD card or just using Windows Explorer (the file manager) to move the file of interest onto the SD card? If you do have a header in your file, you will need to take account for that, though I do not know what you mean by "random file" in this case. Thanks, JColvin
  5. 2 points
    SeanS

    Genesys 2 DDR Constraints

    Hi JColvin, I am definitely not using ISE. I think JPeyron had it correctly. I didn't have my board.Repopaths variable set and so the project wasn't finding the board files. Once I set this variable as suggested, the pin mapping and IO types were auto populated as expected. Kudos, Sean
  6. 2 points
    @jpeyron @D@n I fixed the bug in my SPI Flash controller design. Now I can read from Flash memory.
  7. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  8. 2 points
    Hi, there's a lot of new information in your last post. You aren't just "trying" FPGA but have a professional interest in Zynq. Don't let anybody scare you it's "difficult" and go for it, possibly with the cheapest board, no tutorials and low expectations like, blinking LEDs for quite a while. Given the price tag of any industrial training coarse, an FPGA board for self-study is a no-brainer. Maybe save some money to buy your FPGA engineer a coffee once a week, with some questions in mind
  9. 2 points
    True. Zygot believes that making you work for knowledge is kinder than giving you solutions that can be used to mindlessly resolve your problem of the hour.... it's just a different philosophical bent...
  10. 2 points
    kwilber

    Pmod DA3 clocking

    It looks to me like DA3_WriteSpi() was adapted from code for a different device and has vestigial and incorrect code. Reviewing the AD5541A datasheet, several things stand out There is only a single register in the chip so there is no need for the u8 reg parameter. There is no need for a"config byte" to be sent before the data. The transfer is always 16 bits so there is no need to allow for arbitrary length data quoting from the datasheet "Input data is framed by the chip select input, CS. After a high-to-low transition on CS, data is shifted synchronously and latched into the serial input register on the rising edge of the serial clock, SCLK. After 16 data bits have been loaded into the serial input register, a low-to-high transition on CS transfers the contents of the shift register to the DAC register if LDAC is held low". Reviewing the PmodDA3 schematic, the ~LDAC signal is softly pulled to ground with a 10K resistor. So there is no need to explicitly toggle ~LDAC. What all this means is DA3_WriteSpi could be simplified to something like void DA3_WriteSpi(PmodDA3 *InstancePtr, u16 wData) { u8 bytearray[2]; bytearray[0] = ((wData & 0xFF00) >> 8); bytearray[1] = (wData & 0xFF); XSpi_Transfer(&InstancePtr->DA3Spi, bytearray, 0, sizeof(bytearray)); } You would then call it passing in just the instance pointer and the value you want to write to the DAC. u16 dacValue = 1234; DA3_WriteSpi(&myDevice, dacValue); I do not have a PmodDA3 on my bench so I cannot verify the function works, You can give it a try and let us know how it goes.
  11. 2 points
    JColvin

    Pin Mapping for JTAG-SMT3-NC

    Hi @RussGlover, I apologize for the delay; the details you are looking are as follows: TCK - ADBUS0 TDI - ADBUS1 TDO - ADBUS2 TMS - ADBUS3 OEJTAG - ADBUS7 OESRSTN - ACBUS4 Let me know if you have any more questions. Thanks, JColvin
  12. 2 points
    kwilber

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  13. 2 points
    kwilber

    Pmod DA3 Pinout

    That is one of the conventions commonly used to indicate an Active Low signal. So in this case, you pull Chip Select low when you want to access the chip. After you have toggled in all the data bits on the DIN line, you pull LDAC low. The Pmod DA3 reference manual has a link to the D/A chip's datasheet. That is the best first place to look for information on the device's function. The required signal timings are on page 5 of the datasheet.
  14. 2 points
    @Ahmed Alfadhel If you installed Vivado then you also installed the Xilinx Document Navigator. If you are serious about developing with FPGA devices you need to know how to find and access the plethora of documents that your vendor provides in order to use their devices properly. Check the box for 7 Series devices to see the list of reference manuals, User's Guides, Datasheets etc. From there you can add all relevant documents to your search and keep up to date. Do the same for ISE or Vivado tools. This is where everyone needs to start their Xilinx FPGA journey. Xilinx makes it easier than other FPGA vendors to obtain knowledge.
  15. 2 points
    The hot plug detect should be on the rx side. The source will see that and will then initiate the DDC conversation.
  16. 2 points
    The answer is yes, that fixed it! Thank you so much! The odd thing is that I tried this in one of my attempts and put it back to QSPI as it didnt work. Regardless thank you so very much for walking me through this. all looks good now:
  17. 2 points
    So the picture that you post of a (relatively) gigantic scope probe clip resting on a fairly small FPGA device in a BGA package is a way of making a statement. It might also be viewed as a picture that might be making a statement to you. I routinely use an LED to verify that my design is at least being clocked properly. Make a 32-bit counter and connect bit 26 or so to an obuf driving one of the boards LEDs. You can get an approximation of a 1 blink/s LED rate with a little math depending on the clock rate and the chosen counter bit. For me the clock rate of interest isn't the external clock coming into the FPGA but some clock output of an MMCM or PLL that I'm using for my design. If the LED is blinking then I at least know that something is alive in my design. You've got to be careful with those large scope probe grabbers around fine pitch components. I prefer to bring out a few debug versions of particular signals of interest to a PMOD and connect that to a scope probe ( the PMOD has DGND pin(s) ). You still have to exercise some caution with the ground clip on your scope probe as it's easy to short an adjacent pin to ground and ruin your day. It would be very useful if Digilent provided GND test points, or at least holes for test points, in an area of their boards for scope probing. The safest thing might be to stick a pin into the GND receptacle of one PMOD connector and probe on signals in another. Insulation stripped off suitably sized wires can help as well to keep ground clips from accidents. It's really easy to have that ground clip pop off whatever it's connect to and bounce around on exposed parts of your board; nothing good will come of that. I limit scope probing to when it's necessary. There are usually safer ways to evaluate signals in your FPGA design. Lastly, you should understand that its very easy to get a false impression of what a signal looks like, especially with normal scope probe ground clips. Think Heisenberg.
  18. 2 points
    Ciprian

    Hdmi out from zybo

    Try adding this: &i2c0 { clock-frequency = <100000>; status = "okay"; }; Here: <petalinux_project>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi -Ciprian
  19. 2 points
    xc6lx45

    Cmod S6 - Multilayer?

    You might go to Texas Instruments' site (or AD or both) and find documentation for some $500 high frequency ADC or DAC eval board as example to study.. There's nothing wrong with copper planes, generally. Free-standing structures (such as non-connected filler polygons) can be bad, if they resonate. So are loops if the driving wire spans an area together with the GND return wire (for which the ground plane is an obvious solution). The worst resonators have high quality factor meaning loose coupling meaning it can be surprising how the energy managed to couple in. There's no such thing as too many ground vias... Note, your ground plane can do very interesting things in combination with the metal box it's in (resonant cavity) but that's a different story.
  20. 2 points
    The warning you pasted is benign and simply means there are no ILAs present in your design. The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design. Finally, @elodg gives some great troubleshooting information in this thread.
  21. 2 points
    And.... I have this sense that if you keep describing what you did you will answer your own question. I don't have enough information yet to help. [I confess that I haven't bothered to read through your code] Verbalizing problems, if you go into enough detail, is often a fairly reliably way to resolve them. Sometimes it helps to have someone throw in a good question or two.
  22. 2 points
    zygot

    Cmod S6 - Multilayer?

    Consider that the FPGA on your module has 196 balls. The A7 versions have 236. You can answer your own question by thinking about how one gets all of those surface mount pads to ground, voltage and signal traces.
  23. 2 points
    You are not wrong - but for that device ID the tooling will not let you use all the LUTs present on the silicon die. It is a somewhat artificial restriction, and might have some implications for the power and thermal properties of the package (e.g. a smaller package may not be able to dissipate the heat).
  24. 2 points
    Hi, Abdul, Here are my notes/recommendations: 1. Open your block diagram in Vivado where you created BRAM configuration and then check the address editor. You should see whether the BRAM address was assigned. If you find assigned see axi_bram_ctrl_0 OffsetAdress and the Range then the BRAM was created and mapped to the memory. 2. Writing and reading from BRAM requires a clock signal. Check Xilinx templates for BRAM which you can access inside the Vivado. I am not sure that the code you've used to write into BRAM does anything. 3. You don't use an absolute address in your HDL when BRAM created in Vivado. Vivado maps the address 0x4000_0000 to 0. So you can start from the address 0 and it will be the lowest address of the BRAM. If your don't use Vivado then you will need to define your block in HDL and include addresses, and many other parameters. 4. The C-code in SDK should use BRAM address from the file parameters.h. You just need to use XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR as the begining of the BRAM address space. 5. You can treat BRAM as RAM meaning that all read/write operators are the same. For example you can copy BRAM content into the RAM: for(i = 0 ; i < BRAM_SIZE ; i++) *(destination + i) = *(source + i); where source = XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR Disclaimer: always read documentation, whatever you find on Internet might not be correct. Good luck!
  25. 2 points
    Hi @akhilahmed, In the mentioned video tutorial, the leds are controlled using "xgpio.h" library but the application is standalone. If you want to use a linux based application you have to use linux drivers for controlling. In the current Petalinux build, which is used in SDSoC platform, UIO driver is the best approach. Steps: 1. Vivado project generation: - Extract .dsa archive from /path_to_sdsoc_platform/zybo_z7_20/hw/zybo_z7_20.dsa - Launch Vivado - In Tcl Console: cd /path_to_extracted_dsa/prj - In Tcl Console: source rebuild.tcl - In this point you should have the vivado project which is the hardware component of SDSoC platform. Open Block Design. Change to Address Editor Tab. Here you will find the address for axi_gpio_led IP: 0x4122_0000 2. Petalinux UIO driver: - Launch SDx - Import zybo-z7-20 SDSoC platform - Create a new SDx linux based project using a sample application (e.g. array_zero_copy) - Build the project - Copy the files from /Dubug/sd_card to SD card - Plug the SD card in Zybo Z7. Make sure that the JP5 is set in SD position. Turn on the baord - Use your favorite serial terminal to interact with the board (115200, 8 data bits, 2 stop bits, none parity) - cd to /sys/class/uio - if you run ls you will get something like: uio0 uio1 uio2 uio3 uio4 uio5 - Now you have to iterate through all these directories and to search for the above mentioned axi_gpio_led address: 0x4122_0000 - For example: cat uio0/maps/map0/addr will output: 0x41220000, which means that the axi_gpio_led can be accessed using linux uio driver through uio0 device. - Code: #include <stdio.h> #include <stdlib.h> #include <sys/ioctl.h> #include <sys/mman.h> #include <stdint.h> #include <unistd.h> #include <fcntl.h> #define UIO_MEM_SIZE 65536 #define UIO_LED_PATH "/dev/uio0" void UioWrite32(uint8_t *uioMem, unsigned int offset, uint32_t data) { *((uint32_t*) (uioMem+offset)) = data; } uint32_t UioRead32(uint8_t *uioMem, unsigned int offset) { return *((uint32_t*) (uioMem+offset)); } void led_count_down(uint8_t *ledMem) { uint8_t count = 0xF; uint8_t index = 0; for (index = 0; index < 5; index++) { UioWrite32(ledMem, 0, count); count = count >> 1; sleep(1); } } int main() { // Set Leds as output int led_fd = open(UIO_LED_PATH, O_RDWR); uint8_t *ledMem = (uint8_t *) mmap( 0, UIO_MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, led_fd, (off_t)0); UioWrite32(ledMem, 4, 0x0); // Set all leds as output while(1) { // Start led count-down led_count_down(ledMem); } return 0; } - Build the project and copy the content of Debug/sd_card on SD sd_card - Power on the board and connect to it using a serial terminal - run the following commands: mount mmcblk0p1 /mnt cd /mnt ./project_name.elf - Result: A countdown should be displayed on leds.
  26. 2 points
    Hi @Ben B, Regarding your question on using Zybo Z7-20 to capture HDMI signals. It is possible and using UIO is also an option, but because we are using the VDMA to get the Video signal it's better to use a DMA driver. Unfortunately Xilinx does not provide a complete DMA driver for any of their DMA IPs, therefore I have been using this DMA driver which includes the VDMA functionality as well. To make things as easy as possible, I generated a example project for you with the VDMA used to capture video streams and OpenCV functions to write a *.bmp file. What you need to do in order to get it working is: 1. load the HDMI2BMP.elf to /home/root on your rootfs portion of your board 2. after the board boots you need to load the axi_dma_driver root@Zybo-Z7-20:~# insmod /lib/modules/4.9.0-xilinx-v2017.4/extra/xilinx-axidma.ko 3. run the HDMI2BMP.elf This will generate a test.bmp in /home/root with the captured image. The source file for the app is in the SDK folder. Changes which I had to do to the original petalinux project are: - create a new module in petalinux petalinux-create -t modules -n xilinx-axidma --enable - copy the necessary file to Petalinux-Zybo-Z7-20/Zybo-Z7-20/project-spec/meta-user/recipes-modules/xilinx-axidma/files and update the MAKE file and the xilinx-axidma.bb - update the system-user.dtsi in /Petalinux-Zybo-Z7-20/Zybo-Z7-20/project-spec/meta-user/recipes-bsp/device-tree/files - write the demo program Hope this helps. -Ciprian Zybo-Z7-20-HDMI-RX_peta.zip
  27. 2 points
    >> having about 60uF of ceramic decoupling goodness Maybe it's even more a question of ESR than capacitance. Ceramic if money doesn't matter (e.g. Mouser: 22 µF: €4..6). The typical solution are staggered capacitors, with a quick look at the datasheet for the self resonance frequency in the impedance curve. I do this for RF (try to get a quality short at n GHz...) but if I had to make a blind guess, I'd use two orders of magnitude, e.g. 10 µ, 100n, 1n and with a nervous glance at my Voodoo doll, 10p. The CMOD A7 is reported quite frequently (possibly because it's one of the most attractive boards) but I can tell that I've run into the same issues with FTDI's reference module for the 2232H. The chip just shuts down if it doesn't like what it sees on VCC. It took a long Friday night in the lab to prove without doubt that our system is sensitive to USB cables. We changed the design and shipped with non-detachable cable. Zero issues so far.
  28. 2 points
    HI @yottabyte, I realize (based on the time stamps) that you figured out the answer to your question before you got a response, but do you mind posting your original question and what you found out so any future users with a similar question would be able to see the answer you (and xc6lx45) found out? Thanks, JColvin
  29. 2 points
    xc6lx45

    Voice-activited

    >> Is that solution Will run? I suspect you mean crosscorrelation, and no, it will most likely not work. Maybe you'll save yourself much pain if you prototype the algorithm first in software. It doesn't need to be real time. E.g. get freeware Octave and use the audioread() function. Be sure to use two independent recordings for reference and simulated microphone input.
  30. 2 points
    You're welcome! I am glad it is working. Yes, this thread should help others trying to run the Pcam 5C demo on Zybo Z7. Best Regards, Ionut.
  31. 2 points
    attila

    AD2 over voltage :-(

    Hi @peter taylor This was a ferrite between the Analog Discovery and USB ground. Supposed to filter noise from USB cable/PC which acted as a fuse... You can solder a simple short instead this ferrite. Hopefully only this was damaged. Be careful. The devices and circuits should have the same ground. The AD ground is connected to the PC ground over the USB cable.
  32. 2 points
    Flux

    VGA Pmod Tutorials

    The VGA tutorials have been updated with support for the Basys 3 and Nexys Video as well as Arty: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 I'm currently adding SVGA (800x600) support as well as working on more advanced effects. All the Verilog is available under the MIT license on GitHub: github.com/WillGreen/timetoexplore I look forward to sharing more projects with the community soon. Will
  33. 2 points
    elodg

    Nexys Video "Feet"

    https://www.fastenal.com/products/details/0146057 https://www.fastenal.com/products/details/28783
  34. 2 points
    Ciprian

    Zynq book - tutorial 5 Zybo Z7

    Hi @n3wbie, Th working project is attached. what you have to take in to account when using this audio codecs with Digilent products is that you need to configure the codec (using I2C) as well as receive the samples using I2S IP core. Basically one is for the control of the codec and the other one is to receive the samples. I have written a small driver for both the I2S core and the I2C SSM2603 which is in the source files of the SDK project (in the sdk folder) which configures the registers for the codec and I2S IP core; the documentation for the codec can be found here. The IP core has not yet been documented which is the main reason we have not added it to the Digilent vivado-ip library, but it needs a 100MHz input for it to be able to synthesize the 12.228 MHz MCLK and the subsequent clocks for the I2S protocol. The demo project reads the buttons and based on the ones you press it will: BTN0 - Record 1s BTN1 - Set Mic input BTN2 - Set Line In input BTN3 - Playback 1s The project is not really optimized so it uses a variable "RecSamples", allocated to the stack memory which holds the recorded samples(48000 samples representing 1s at a 48KHz sampling rate) and it is also used fro play back, so don't press play back before record. The rest should be easily traceable from the comments in the driver and the main source code. If you have any other questions feel fr to ask. Ciprian ZyboZ7Audio.zip
  35. 2 points
    JColvin

    Arty A7 flash chip

    Hi @D@n, I believe the new part that is used in the Arty A7 boards (and other A7 boards) is now a Spansion S25FL128SAGMF100; based on old schematics, I believe this was added in Rev D of the Arty A7 (dated August 2017), though I do not know when that particular Rev was then released (or if it even was released) to the public. I confirmed that the Arty S7 also uses this part and I wouldn't be surprised if most of our other Artix 7 based boards use it now as well. I've requested that the chip name and images are updated in any appropriate tutorials and requested that the pdf version of the reference manual (updated wiki) is updated as well. Thanks, JColvin
  36. 2 points
    xc6lx45

    Diving in

    ... a slightly longer answer, if anybody is interested (analog mixing with square wave LO): One way is to look at the Fourier series of the square wave as a sum of sines at frequencies f, 3f, 5f, 7f, ... and to a lesser extent 2f, 4f, 6f from implementation imperfections. Then think of the mixer as linear multiplier, and use superposition (the distributive property of multiplication) for a*(b3+b5+b7+...) = a*b3+a*b5+a*b7+... Hint, if anybody wants to formally go through the math, it gets much less messy with cos(x) = (exp(ix)+exp(-ix))/2 aka DeMoivre. So you really get multiple frequency translations instead of one. What remains to be done is to manage the input signal energy at those frequencies I don't want, with a filter or narrow-band antenna. In the digital world, you'd always use a sine wave.
  37. 2 points
    attila

    WaveForms beta download

    3.11.4 digilent.waveforms_beta_v3.11.4_64bit.exe Added: - Scope: - set/reset zero offset in each channel option - precision option for measurements Fixed: - Script: access to traces and channels from Instrument.Export - unit conversions V to Ṽ, A to à - I2S 32 bit data 3.11.3 digilent.waveforms_beta_v3.11.3_64bit.exe digilent.waveforms_beta_3.11.3_amd64.deb digilent.waveforms_beta_3.11.3.x86_64.rpm Fixes 3.11.2 digilent.waveforms_beta_v3.11.2_64bit.exe digilent.waveforms_beta_3.11.2_amd64.deb digilent.waveforms_beta_3.11.2.x86_64.rpm Added: - Spectrum, Network and Impedance Analyzer store time data when this view is open Fixed: - runscript argument - loading of docked views geometry 3.11.1 digilent.waveforms_beta_v3.11.1_64bit.exe digilent.waveforms_beta_3.11.1_amd64.deb digilent.waveforms_beta_3.11.1.x86_64.rpm Added: - Scope: out of range warning in measurements - Protocol/UART: - support up to 32bit/word - TX/RX format: text, binary, decimal, hex - Wheel Direction option - Logic Analyzer: option to swap previous/next events - Spectrum Analyzer: allowing higher number of BINs for CZT 3.10.7 digilent.waveforms_beta_v3.10.7_64bit.exe Added: - Spectrum: logarithmic magnitude scale for voltage units - Protocol: datetime stamp for SPI/I2C Spy Fixes 3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom mathematic channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Netowrk Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.
  38. 1 point
    JColvin

    Pmod ISNS20 SPI Arduino

    Hi @tfcb, I am taking a look into this; I connected a level shifter of my own (Digilent's Pmod LVLSHFT rather than the Sparkfun one you linked to) to connect an Arduino Uno and Pmod ISNS20, but I too am getting strange values (no initial offset for example), so I'm debugging some more. Thanks, JColvin
  39. 1 point
    zygot

    How do I select the right FPGA board?

    I really don't know where to put this so I decided to ask myself a question and then propose an answer. Perhaps there needs to be a new home for basic assistance for users. A frequent question for beginners and even experienced people resolves around how to select an FPGA development board. The answer depends on what you want to do with it. The analysis can be anywhere from simple to complex. But there are three issues to resolve that will simplify the process of making a selection. Three questions that only you can answer are: What do you want to do with the hardware ? What is your budget ? What is your experience level ? For our context I'll be ignoring a 4th question, which might be the real driver for your interest. That question is: "What are your goals?". If you are just curious then that's different than if you want to add marketable skills to your resume. Also, you might perceive knowing how to develop with a particular device, such as Zynq, as an over-arching motivation. My view is that the Zynq is a great solution for a number of problems for a competent FPGA developer but except for running Ubuntu almost anything that I can do in software can be done with logic resources in an FPGA. On the theory that goals tend to change with experience and knowledge I'm going to proceed without answering that question. So let's group some possible answers to the responses to the previously listed questions and provide a bit of guidance. Case 1: 1) $0 OR 2) either "I don't know" or "I just want to learn how to use an FPGA". OR 3) None If you don't have a specific hardware project requiring an FPGA you don't need to spend anything to learn or develop FPGA applications and I suggest that you don't. Just get the latest version of Vivado or ISE. You can do everything except spend time debugging hardware with nothing more than Vivado or ISE. If you have no experience with VHDL or Verilog then I strongly suggest buying a used textbook but this is not a requirement. Xilinx provides information about how to use its devices and tools but assumes that you know enough about an HDL to accomplish synthesis or simulation for a project. Learning an HDL in the context of a directed or group setting is easier than teaching yourself, but not necessary. FPGA devices are complex and the tools are complex and no one is going to spend a Saturday afternoon reading the Xilinx literature and being a competent FPGA developer by Sunday. Understand that FPGA development is really just digital logic development. So if you come from a software background you might have to re-wire your brain a bit to grasp the basic concepts. Learn the basic concepts, how to be fluent in an HDL for both synthesis and simulation and how to know how to simulate effectively. You simply can't do competent FPGA development unless you know how to write a testbench in your HDL and perform effective simulation. You don't need to read the vendor manuals for the resources in any particular FPGA device but having an understanding of what and FPGA is certainly can't hurt. Case 2: 1) "not much" AND 2) "Nothing in particular but simple logic designs" AND 3) I'm competent using an HDL, simulator tools, and Vivado or ISE If these are your answers then the advice for case 1 might still be valid. It's true that most of us need some form of positive feedback to motivate us to do hard work. An FPGA development board might just do the trick. So my advice is simple. Spend the least amount possible. There are decent boards with a JTAG programming and minimal interface resources available such as the CMOD or DE0-NANO for < $100. Aside from the motivation factor you still don't need hardware to accomplish even complicated designs so why spend money until you know what to spend you money on? If you are determined to spend your allowance then start off with the least expensive and least expensive to replace board. The buttons, LEDs and switches can all be simulated. For basic HDL designs you can use global clock buffers and not worry about anything except pin location constraints. Case 3: 1) "not much" AND 2) "I want to use and FPGA to build a variety of hardware prototypes that don't require using advanced FPGA IO features" AND 3) "I'm competent using an HDL, simulator tools, and Vivado or ISE plus I'm reasonably competent designing with digital, analog or mixed-signal devices." For this case there are a number of inexpensive modules that offer 30 or more GPIO and basic functionally, but more importantly have the IO on headers that are easy to connect to a PCB of your own design that performs a specific function. In this case the FPGA development board is more of a component and might be dedicated to one prototype. There are a number of inexpensive modules from Digilent, Terasic and other vendors that might be ideal. You can make some pretty useful things with one of these modules and PCB vendors offering free layout and design tools like ExpressPCB. Here are some specific considerations in making a choice: What kind of documentation is provided? What kind of customer support is available? What kinds of demo projects are available and can I actually build them with my tool version Now of course merely understanding the manuals for clocking, IO, and other resources of a particular device isn't sufficient. You need to be able to make use of the device datasheet, especially the AC specifications. To give you an idea here is a table of useful switching specifications for a number of Digilent boards that I own ( the CMOD-A7 is an Artix-1 device ). Nexys Video Genesys2 ATLAS Artix(-1) Kintex(-2) Spartan6(LX-3) DS181 DS182 DS162 ----------- ----------- -------------- Fmax_bufg 464 710 400 Fmax_bufh 464 710 - Fmax_bufr 315 540 - Fmax_bufio 600 800 - Fmax_bufio2 - - 525 Fmax_buffpll - - 1050 Fmax_buffgmux - - 400 PLL_Finmax 800 933 525 PLL_Finmin 19 19 19 PLL_Foutmax 800 933 1050 PLL_Finmain 6.25 6.25 3.125 PLL_vcomax 1600 1866 1050 MMCM_Finmax 800 933 - MMCM_Finmin 10 10 - MMCM_Foutmax 800 933 - MMCM_Finmain 4.69 4.69 - Fmax_bram_xxx 297-388** 427-544** 280 Fmax_fifo 388* 544* - Fmax_dsp48e 177-464** 249-650** - Fmax_dsp48a - - 333** All values in MHz - not applicable * non-ECC mode ** depends on modes used [Update] Interesting SERDES performance specifications: Kintex-2 Artix-1 SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 - 8 HR 710 600 Mb/s HP 710 - Mb/s DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) HR 1250 950 Mb/s HP 1400 - Mb/s SDR LVDS receiver (SFI-4.1)(1) HR 710 600 Mb/s HP 710 - Mb/s DDR LVDS receiver (SPI-4.2)(1) HR 1250 950 Mb/s For Spartan6-3 (Network) SDR LVDS transmitter or receiver (using IOB SDR register) 400 Mb/s DDR LVDS transmitter or receiver (using IOB ODDR2/IDDR2 register) 800 Mb/s SDR LVDS transmitter (using OSERDES2; DATA WIDTH = 2 to 8 1050 Mb/s DDR LVDS transmitter (using OSERDES2; DATA WIDTH = 2 to 8 1050 Mb/s SDR LVDS receiver (using ISERDES2; DATA WIDTH = 2 to 8 1050 Mb/s DDR LVDS receiver (using ISERDES2; DATA WIDTH = 2 to 8 1050 Mb/s You also need to understand thermal management. Some of these boards don't have much copper mass and do have a lot of heat dissipating components in a very small area. It is likely that you will have issues trying to push these modules to the extreme limits for an application even with their limited power supply resources. If what you need is for some custom logic and <100 MHz switching and a few are output pins then you aren't likely to have problems, assuming that you properly terminate your IO signals. Since you are competent doing digital and analog design you know the differences between a .1" header and and HSMC or FMC connector as far as signal integrity characteristics are concerned. You also understand from the FPGA vendor's literature the termination requirements for all supported logic standards and clocking limitations. Case 5: 1) "Less than $2000" AND 2) "I want to experiment with using advanced IO resources" AND 3) "I'm competent using an HDL, simulator tools, and Vivado or ISE plus I'm reasonably competent designing with digital, analog or mixed-signal devices." In order to get experience using the advanced IO features or transceivers available in current generation FPGA devices you need a board that is designed to allow you to use these features. I bought a Genesys2 primarily because the way that they implemented mDP allowed me to experiment with multi-lane transceiver designs. The HPC FMC connector was a bonus but you have to do your homework if you plan on using a mezzanine board and the FMC connector. In particular, there are a lot of "FMC" mezzanine cards that aren't necessarily suitable for the Genesys2 FMC implementation or are even particularly VITA-57 compliant. Usually, this has to do with clocking and IO bank pin assignments. If you want to use a particular FPGA carrier board with a particular FMC type mezzanine card you have to trace through all of the pin assignments to make sure of compatibility. This is particularly true for differential LVDS IOSERDIES2 applications. In general it's easier to find an HSMC mezzanine card FPGA carrier board combination but you still have to do your homework as there are differences between differential signal pairs routed as differential pairs and differential signal pairs simply having matched trace lengths. If you have a bus of differential signals trace length matching across pairs is important. I've used the Nexys Video and Genesys2 boards for a number of projects using the FMC mezzanine cards with complete success. I've not been able to use either of those boards to connect every FMC card that I wanted to use. It is unlikely that you will find an FMC mezzanine card designed to work with an Intel based FPGA board that can be used on a Xilinx based FPGA board. It all has to do with pin assignments. This isn't a deficiency of the FMC implementation of the Digilent boards are even of the mezzanine boards, just an incompatibility for particular FPGA device pin locations and signal assignments. If you only get one takeaway from this thread this is it... just because it's on an FMC or HSMC connector doesn't mean you can use it with your FMC or HSMC equipped FPGA board. Digilent's current crop of FPGA boards provides either low speed PMOD connectors (<10 MHz) which are ease to connect to a custom PCB or high density FMC connectors which are expensive and difficult to connect to a custom PCB. No one knows what the so called high-speed PMODs were designed to do, but they aren't suitable for advanced IO experimentation. If you want to experiment with transceivers you need to read the Xilinx transceiver user manual and know the difference between GTP, GTH and GTY transceiver implementations and maybe those from other vendors. Before choosing a general purpose board to explore advances IO I suggest: Have a thorough understanding of advanced constraints beyond location and IOSTANDARD. There are user manuals for this. Have competence in timing closure methodologies. Read the manuals. Thoroughly understand the Series7 IO, clocking, and transceiver users' manuals Pore over the board documentation, especially the schematics, for boards on your short list. A lot of FPGA board vendors will make you do the work to figure out which banks specific IO pins are assigned to. Make sure that the support includes applicable demo projects that you can build them targettin that particular board with your version of Vivado easily. Figure out what IP if any you need to do something useful with your advanced IO plans. Case 6: 1) "The minimal to accomplish the project" AND 2) "I have a very specific project to complete using specific advanced IO resources" AND 3) "I'm competent using an HDL, simulator tools, and Vivado or ISE plus I'm reasonably competent designing with digital, analog or mixed-signal devices." For this case the analysis gets complicated. If you want need to do video or Ethernet based communication there might be a board that fits your specific needs for a particular project. The general rule is that buying hardware that isn't designed to accomplish a particular purpose is rarely a good investment. 10G Ethernet is a different animal than Gigabit Ethernet. 12G SDI video is a different animal than HDMI video. You need to verify that either the board can do what you want to do or provides the IO in a form that let's you add a mezzanine card to it to do the job. Neither of these investigations is necessarily straightforward or easy. So by now you probably realize that each of the cases that I posit involve building an ever increasing level of competence and body of expertise. So everything that applies to the previous cases applies here except that you now have to select all of the boards that will allow you to complete your project. If you need to have a temporoary or time-restricted license to complete your project then what good will that be next year? Clearly I haven't addressed all of the possible scenarios for the three questions put forth in the beginning but hopefully I've presented the basic ideas for a wide range of people willing to take the time to read it. One case that I didn't address is where you want to do something using one of the many PMODs available for purchase and want to create an HDL solution to accomplish something. Again, the cheapest board available with the most standard PMODs will likely be what you want. Make sure that you understand what will be provided for you and what you needs to do for yourself. This is a small universe but one in which a lot of people will happily spend there lives. A lot of what's been presented is 'common sense', whatever that is. If you've never ridden a bike but saw the Tour de France and want to dip your toe into competitive racing the first thing to do is not spend 100's of dollars on shoes, helmets, clothes and $10K on a road bike that's just over your wildest budget ( you know because you're going to grow into it...). If, once you know what you're doing, you decide that you want to do mountain trail racing none of that gear will be useful. Also learning how to ride in the company of a local bike club will be much more productive and fun than spending weeks on the couch reading books on technical riding concepts. I hope that this provides some things to consider for the many of you not having the experience with a lot of FPGA development boards and projects. I apologize for the rough formatting....
  40. 1 point
    JColvin

    PmodRs485 - Arduino Due

    Hi @Bhushan021, We don't have an Arduino Due to directly test this ourselves, but I believe the ModbusMaster.h should generally be compatible with the Pmod RS485 since from what I can tell in the material available on the associated github account (link) it just uses a serial port and flow control bits which are required for the Pmod RS485 to work correctly. My understanding with the Arduino Due is that it subject to the caveat listed in the readme where you will need to disconnect the module from RX while uploading the sketch before being able to reconnect and properly use it. I am uncertain of how the other two pieces of hardware listed in the Github hardware states differ from the Pmod RS485 though. Thanks, JColvin
  41. 1 point
    Hi @gregsa WF beta v3.10.3 lets you select extended frequency, up to 25MHz for AD. Note that at such high frequencies the signal will be attenuated.
  42. 1 point
    JColvin

    please help me

    Hi @Asmaa_as, The steps can be found at this Instructable here: https://www.instructables.com/id/Analog-Discovery-2-USB-Oscilloscope-LabVIEW2016-Up/. Thanks, JColvin
  43. 1 point
    zygot

    Zybo Z7 Development Board ESD&Safety

    @Sduru All electronic equipment is susceptible to ESD damage. Especially, on a board like yours with components exposed. Especially, if you are not using it in an environment where humidity is controlled. If you were working in such a controlled environment at a company, using company equipment, they would ( should ) require you to work on an ESD pad with a wrist band that has a qualified ESD to ground path to leak off ESD currents. And that's in a lab environment where the possibility of static discharge is minimal. If you are working at home and on a desk with a carpeted floor in the winter when heating is likely to make static a relatively likely possibility then I would suggest that buying a small ESD mat and ground strap is a worthwhile investment. You can damage your equipment without causing it to fail catastrophically. Yes you can be lucky enough to ignore well established and proper electronic handling guidelines without having an issue ( or more likely not being aware that you've had an issue ) but ignoring well established and proper guidelines is just a bad idea. You can get away with a lot of risky behavior for a while but sooner or later the piper will send his bill and you will pay. As a general rule you should never touch components on a PCB; at least without proper grounding. But even if you are very careful to move a board by the edge or shielded connectors like Ethernet RJ45 jacks that are grounded you can still zap components if you've built up enough static charge. You've asked a very good question. I understand that there are people who will choose to ignore this advice but I've given you an answer that is consistent with professional practice. Expensive electronic development kits don't come in a anti-static bag with a seal that is supposed to break when you open it for no reason even though it cost more for the vendor to do this. BTW ESD mats are high resistance affairs that are design to leak off static charge to a good ground ( this might not be available where you are working at home ) without endangering you to high voltage low impedance sources. Thought I'd mention this for anyone thinking that they might make their own cheap workstation....
  44. 1 point
    Andy7777

    USB OTG on Zybo does not work

    I know this is an old link, but in case anyone is still interested, i managed to get this working by changing the system-user.dtsi file to /include/ "system-conf.dtsi" / { model = "Zynq Zybo Z7 Development Board"; compatible = "digilent,zynq-zyboz7", "xlnx,zynq-7000"; chosen { bootargs = "console=ttyPS0,115200 earlyprintk uio_pdrv_genirq.of_id=generic-uio"; }; usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; };
  45. 1 point
    D@n

    NEXYS 4 Programming Flash

    @bhall, No, this makes perfect sense. Xilinx, in their infinite wisdom, created a SPI port clock pin to be used for configuring the device. It's controlled internally. When they then realized that customers would want to use it as well, they created a STARTUPE2 primitive that you need to use to get access to it. As such, its often not listed in the port lists, but still usable. On several of the newer Digilent designs, Digilent has connected that pin to two separate ports. This allows you to control the pin like a normal I/O. However, doing this requires special adjustments at the board level--not the chip level. Dan
  46. 1 point
    xc6lx45

    GPS Pmod

    I must say I share D@n's opinion here. What I would do is start with a plain serial port. Create a dumb (non-clocked) FPGA design that routes the FTDI chip's UART pins to some GPIOs, and hook up the GPS module. Alternatively, use a standalone FTDI-to-UART module or equivalent. Fire up teraterm (e.g.) on the PC, open the COM port, set the correct baud rate. Check that the GPS module responds as expected. Check that the message format is exactly as you expect it. I suspect this assumption >> it seems, that the given functions from digilents pmodgps.h heather are doing already the right stuff won't hold. What you're trying reminds me of the old joke about a gynecologist retraining as a car mechanic🙂
  47. 1 point
    Hi @xzsawq21, The add a module function works with the zynq processor as well. What zynq board are you using? Here is another tutorial for using the custom ip core if you would still prefer to use the custom ip core instead of the add a module function. thank you, Jon
  48. 1 point
    attila

    Math on FFT traces

    Hi @lab!fyi The Script/Spectrum is added to the Help of beta version. Please use the Help of the application since this is the most up to date resource. https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ You could use Ctrl+Space, code completion: https://forum.digilentinc.com/topic/15433-more-meta-data-wanted/?do=findComment&amp;comment=37724 Beside this the code is JavaScript: http://www.ecma-international.org/publications/standards/Ecma-262.htm https://www.w3schools.com/jsref/jsref_obj_math.asp For next software version added support to set trace data from script.
  49. 1 point
    shahbaz

    How to read from SD card on ZYBO

    hi @jpeyron, I followed the guide at GitHub under Readme in PMODSD. can you please guide me step wise on how to start from block design and than going to SDK and running the demo. I have added the pmodsd and zynq PS IPs, after auto connection and running the generate bitstream I get following error. I need your guidance at this
  50. 1 point
    attila

    Analog Discovery 2 vs Raspberry Pi 3

    FTDI USBs like AD, AD2, DD are not working with RPI model B (1,2,3) data packets/bytes are randomly lost. The EExplorer with different USB controller is working fine on these. All devices are working with other embeddeds: Zed, Zybo, BeagleBone… According reports AD is working with the original RPI model A and probably Zero because it has similar chipset/USB. The problem seems to be with FTDI or RPI B USB, library or hardware. You can find such comments regarding RPI problems with other devices too. Unfortunately we couldn't remediate this problem.