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  1. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  2. 2 points
    kwilber

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  3. 2 points
    Hi @neocsc, Here is a verified Nexys Video HDMI project updated from Vivado 2016.4 to Vivado 2017.4. You should be able to find the updated project in the proj folder . Here is a GitHub project done in HDL using the clocking wizard, DVI2RGB and RGB2DVI IP Cores for another FPGA. Here is a unverified Nexys Video Vivado 2017.4 HDMI pass through project made from the linked Github project. In the next few days I should have the bandwidth to verify this project. thank you, Jon
  4. 2 points
    The warning you pasted is benign and simply means there are no ILAs present in your design. The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design. Finally, @elodg gives some great troubleshooting information in this thread.
  5. 2 points
    Hi @akhilahmed, In the mentioned video tutorial, the leds are controlled using "xgpio.h" library but the application is standalone. If you want to use a linux based application you have to use linux drivers for controlling. In the current Petalinux build, which is used in SDSoC platform, UIO driver is the best approach. Steps: 1. Vivado project generation: - Extract .dsa archive from /path_to_sdsoc_platform/zybo_z7_20/hw/zybo_z7_20.dsa - Launch Vivado - In Tcl Console: cd /path_to_extracted_dsa/prj - In Tcl Console: source rebuild.tcl - In this point you should have the vivado project which is the hardware component of SDSoC platform. Open Block Design. Change to Address Editor Tab. Here you will find the address for axi_gpio_led IP: 0x4122_0000 2. Petalinux UIO driver: - Launch SDx - Import zybo-z7-20 SDSoC platform - Create a new SDx linux based project using a sample application (e.g. array_zero_copy) - Build the project - Copy the files from /Dubug/sd_card to SD card - Plug the SD card in Zybo Z7. Make sure that the JP5 is set in SD position. Turn on the baord - Use your favorite serial terminal to interact with the board (115200, 8 data bits, 2 stop bits, none parity) - cd to /sys/class/uio - if you run ls you will get something like: uio0 uio1 uio2 uio3 uio4 uio5 - Now you have to iterate through all these directories and to search for the above mentioned axi_gpio_led address: 0x4122_0000 - For example: cat uio0/maps/map0/addr will output: 0x41220000, which means that the axi_gpio_led can be accessed using linux uio driver through uio0 device. - Code: #include <stdio.h> #include <stdlib.h> #include <sys/ioctl.h> #include <sys/mman.h> #include <stdint.h> #include <unistd.h> #include <fcntl.h> #define UIO_MEM_SIZE 65536 #define UIO_LED_PATH "/dev/uio0" void UioWrite32(uint8_t *uioMem, unsigned int offset, uint32_t data) { *((uint32_t*) (uioMem+offset)) = data; } uint32_t UioRead32(uint8_t *uioMem, unsigned int offset) { return *((uint32_t*) (uioMem+offset)); } void led_count_down(uint8_t *ledMem) { uint8_t count = 0xF; uint8_t index = 0; for (index = 0; index < 5; index++) { UioWrite32(ledMem, 0, count); count = count >> 1; sleep(1); } } int main() { // Set Leds as output int led_fd = open(UIO_LED_PATH, O_RDWR); uint8_t *ledMem = (uint8_t *) mmap( 0, UIO_MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, led_fd, (off_t)0); UioWrite32(ledMem, 4, 0x0); // Set all leds as output while(1) { // Start led count-down led_count_down(ledMem); } return 0; } - Build the project and copy the content of Debug/sd_card on SD sd_card - Power on the board and connect to it using a serial terminal - run the following commands: mount mmcblk0p1 /mnt cd /mnt ./project_name.elf - Result: A countdown should be displayed on leds.
  6. 2 points
    JColvin

    Arty A7 flash chip

    Hi @D@n, I believe the new part that is used in the Arty A7 boards (and other A7 boards) is now a Spansion S25FL128SAGMF100; based on old schematics, I believe this was added in Rev D of the Arty A7 (dated August 2017), though I do not know when that particular Rev was then released (or if it even was released) to the public. I confirmed that the Arty S7 also uses this part and I wouldn't be surprised if most of our other Artix 7 based boards use it now as well. I've requested that the chip name and images are updated in any appropriate tutorials and requested that the pdf version of the reference manual (updated wiki) is updated as well. Thanks, JColvin
  7. 1 point
    Tim S.

    Pmod OLEDrgb with Zybo Z7

    Just to make sure my explanation is thorough. The above has a typo. It should read: Linux has a case-sensitive file system whereas Windows has a case-insensitive file system.
  8. 1 point
    jpeyron

    GPS Pmod

    Hi @cepwin, I'm glad you we able to get to the bottom of the issue. Thank you for sharing what happened. cheers, Jon
  9. 1 point
    You can find newer version 1.0.0.76 in the description of the video: https://www.youtube.com/watch?v=4d3hc-9zBaI
  10. 1 point
    yes, for an application with basic requirements, like receiver gain control this will probably work just fine (it's equivalent to an analog envelope detector). Now it needs a fairly high bandwidth margin between the modulation and the carrier, and that may make it problematic in more sophisticated DSP applications (say "polar" signal processing when I try to reconstruct the signal from the envelope) where the tolerable noise level is orders of magnitude lower.
  11. 1 point
  12. 1 point
    Hi @pikeaero, Welcome to the Digilent forums! best regards, Jon
  13. 1 point
    attila

    Scope custom math channel limitations?

    Hi @P. Fiery You could use the View/Logging/Script to create an up-sampled reference channel like this: var rg = [] var v2 = 0 Scope.Channel1.data.forEach(function(v1){ rg.push((v1+v2)/2) rg.push(v1) v2 = v1 }) // upsampling by 2 doubles the sample rate Scope.Ref1.setData(rg, 2*Scope.Time.Rate.value)
  14. 1 point
    Nothing to worry about if only one is up at a time. It would mean that the frequencies of adjacent oscillators affect each other if they are running at the same time ("injection pulling", to the point that they agree on a common frequency ("locking"). Consider the oscillator as an amplifier with a feedback loop. The feedback path plus phase shift lead to a fairly narrow frequency response around the oscillation frequency or harmonically related frequencies). Weird things can happen with the gain - while it is unity in average steady-state operation, the circuit can get highly sensitive to external interference that is (near)-correlated with the oscillator's own signal. Wikipedia: Perhaps the first to document these effects was Christiaan Huygens, the inventor of the pendulum clock, who was surprised to note that two pendulum clocks which normally would keep slightly different time nonetheless became perfectly synchronized when hung from a common beam
  15. 1 point
    jpeyron

    Pmod da3 reconstruction filter

    Hi @lwew96, We have not used a reconstruction filter. I did find a paper that discusses a reconstruction filter with the AD5541 here. Hopefully one of the more experienced community members will have some input for you as well. best regards, Jon
  16. 1 point
    Hi @kuc3, Welcome to the Digilent Forums! I have moved your thread to a sub-section where more experienced embedded linux engineers look. best regards, Jon
  17. 1 point
    Hi @dmishins, Welcome to the Digilent Forums! Please attach a screen shot of your Block design. Did you connect the 200 MHz clock to the MIG as instructed in section 10? What did you set the local memory and cache when running clock automation for Microblaze? best regards, Jon
  18. 1 point
    Hi, For sw part I use Xilinx DMA driver (interface to VDMA IP core) and modified ADI AXI HDMI DRM driver for exposing frame buffer device to GUI sw (e.g. Qt). You can see driver bindings in above attached zyboz7-20.devicetree-1.zip (pl.dtsi). All video memory transfers to FPGA are managed by this two drivers.
  19. 1 point
    Hi @ahmedengr.bilal, Like I mentioned in the previous post there is no HDMI output from the Linux side, neither the embedded rootFS provided by petalinux nor the kernel configuration we give out is set to accommodate this feature. Regarding the missing media-ctl and v4l2-ctl, you have not activated the v4l-utils in the rootfs configuration of the petalinux. to do this you need to navigate to your petalinux project folder and run: petalinux-config -c rootfs Once the menu appears you need to go to Filesystem Packages->misc->v4l-utils and activate: v4l-utils, libv4l, media-ctl. Rebuild the whole project and it should be working now. -Ciprian
  20. 1 point
    Yep, seen that they were back online. Thanks, Jon
  21. 1 point
    Hi, as I may not have time for FPGA work for a while - just started in a fascinating new role related to high-speed digital diaper changing - I decided to post this now. Here's the Github repo (MIT-licensed) The project provides a very fast (compared to UART) interface via the ubiquitous FTDI chip to a Xilinx FPGA via JTAG. Most importantly, it achieves 125 us response time (roundtrip latency), which is e.g. 20..1000x faster than a USB sound card. It also reaches significantly higher throughput than a UART, since it is based on the MPSSE mode of the FTDI chip. Finally, it comes with a built-in bitstream uploader, which may be useful on its own. I implemented only the JTAG state transitions that I need but in principle this can be easily copy-/pasted for custom JTAG interfacing. So what do you get: On the software side an API (C#) that bundles transactions, e.g. scattered reads and writes, executes them in bulk and returns readback data On the RTL side a very basic 32 bit bus-style interface that outputs the write data and accepts readback data, which must be provided in time. See the caveats. In general, a significant increase in complexity over a UART. The performance comes at a price. In other words, if a UART will do the job for you, DO NOT use this project. For more info, please see the repo's readme file. For CMOD A7-35, it should build right out-of-the-box. For smaller FPGAs, comment out the block ram and memory test routines, or reduce the memory size in top.v and Program.cs. I hope this is useful. When I talked to the FTDI guys at Electronica last week I did not get the impression that USB 3.0 will make FT2232H obsolete any time soon for FPGA: They have newer chips and modules but it didn't seem nearly as convenient, e.g. the modules are large and require high density connectors. In FPGA-land, I think USB 2.0 is going to stay... Cheers Markus
  22. 1 point
    jpeyron

    hdmi ip clocking error

    Hi @askhunter, I did a little more searching and found a forum thread here where the customer is having a similar issue. A community member also posted a pass through zynq project that should be useful for your project. best regards, Jon
  23. 1 point
    For the Protocol / SPI-I2C /Spy mode you should specify the approximate (or highest) protocol frequency which will be used to filter transient glitches, like ringing on clock signal transition. The Errors you get indicate the signals are not correctly captured. - make sure to have proper grounding between the devices/circuits - use twisted wires (signal/ground) to reduce EMI - use logic analyzer and/or scope to verify the captured data / voltage levels at higher sample rate at least 10x the protocol frequency Like here in the Logic Analyzer you can see a case when the samples are noisy:
  24. 1 point
    @longboard, Yeah, that's really confusing isn't it? At issue is the fact that many of these chips are specified in Mega BITS not BYTES. So the 1Gib is mean to refer to a one gigabit memory, which is also a 128 megabyte memory. That's what the parentheses are trying to tell you. Where this becomes a real problem is that I've always learned that a MiB is a reference to a million bytes, 10^6 bytes, rather than a mega byte, or 2^20 bytes. The proper acronyms, IMHO, should be Gb, GB, Mb, and MB rather than GiB or MiB which are entirely misleading. As for the memory, listed as 16 Meg x 8 x 8, that's a reference to 8-banks of 16-mega words or memory, where each word is 8-bits wide. In other words, the memory has 16MB*8 or 128MB of storage. You could alternatively say it had 1Gb of memory, which would be the same thing, but this is often confused with 1GB of memory--hence the desire for the parentheses again. Dan
  25. 1 point
    Hi @Phil_D Try calling to load the workspace and to run script one after the other. subprocess.Popen(['C:/Program Files/Digilent/WaveForms3/WaveForms.exe', 'phase_noise_237.dwf3work']) subprocess.Popen(['C:/Program Files/Digilent/WaveForms3/WaveForms.exe', '-runscript'])
  26. 1 point
    Hi @Jaraqui Peixe, Unfortunately, Digilent does not have the ability to obtain these licenses for you with regards to Xilinx negotiations. I do not doubt that the Spartan 3E Starter Boards you have are as good as new and work as such, but the reality is that last variant of ISE 14.7 that could support the FPGA chips on the Basys 2 and the Spartan 3E (both over 10 years old), was released by Xilinx back in 2013, so active support on these boards is limited as the required software will not install on newer OS's (at least the Windows variants anyway). As @xc6lx45, it is possible to make it work though. What I would probably recommend is looking into the newer 7 series boards, such as the Basys 3 (the most similar to the Basys 2) or if you would want access to more memory than is provided in BRAM, both the Arty A7 and the Nexys A7 have on-board DDR memory. All of these boards work with Microblaze and are supported by the free Vivado WebPACK from Xilinx (which is license-free if that is a factor for you and includes Microblaze). Naturally, there is no guarantee that the Vivado software that supports these Artix 7 FPGA chips will become end-of-life'd, but I can at least say from Digilent's end that I have not heard of this happening in the near future. Thanks, JColvin
  27. 1 point
    Hi, >> We are forced to work in assembly with picoblaze. you might have a look at the ZPU softcore CPU with GCC. The CPU is just a few hundred lines of code but most of its functionality is in software in the crt.o library in RAM. I understand it's quite well tested and has been used in commercial products. Not surprisingly, using an FPGA to implement a processor that then kinda emulates itself in software (aka RISC :) ) is maybe not the most efficient use of silicon - I'm sure it has many strong points but speed is not among them... Unfortunately, the broken-ness of Xilinx' DATA2MEM utility (to update the bitstream with a new .elf file) spoils the fun, at least when I tried in ISE14.7 (segfaults). When it works, the compile/build cycle takes only a second or two. Long-term, porting the processor to a new platform would be straightforward, or even fully transparent if using inferred, device-independent memory. This would also work for a bootloader that is hardcoded into default content in inferred RAM. I might consider this myself as a barebone "hackable" CPU platform strictly for educational purposes.
  28. 1 point
    jpeyron

    Nexys 2 - transistor part number

    Hi @CVu, Welcome to the Digilent Forums! Q1 information is below: NTS2101P Single P-Channel Power Mosfet 1.4A, 8VSOT-323 (SC-70) best regards, Jon
  29. 1 point
    You might have a look at Trenz Electronics "Zynqberry". I think they managed to get one of the cameras to work (not sure). What I do remember is that the board has some custom resistor circuitry to additional pins for the required low-speed signaling.
  30. 1 point
    kwilber

    Pmod DA3 clocking

    You may not have to build your own. That becomes a design decision that only you can make based on the requirements/specifications your design must meet. If the performance you are getting out of the Digilent IP meets your requirements, there is no reason to roll your own. On the other hand, if you are not able to meet your requirements and you are running up against limitations of the IP, then either look for a more performant IP or consider designing purpose specific logic. According to your measurements, it takes 40 bits sent at a rate of 3.125 Mhz for each update of the DAC. That is at least 12.8 microseconds per update. Take the inverse of that and you have a maximum update rate of 78,125 updates/second. Is that sufficient for your design?
  31. 1 point
    kwilber

    Simple HDMI pass through with NexysVideo

    Unfortunately, I do not have a NexysVideo board available. I have run the simple hdmi pass thru on both zybo and arty boards. Have you tried using a resolution of 720p yet? I find it useful to start with the lower frequencies first. Most sources and monitors have no trouble working with that.
  32. 1 point
    Hi @Mukul, Are you getting the Error while launching program: Memory write error at 0x100000. APB AP transaction error, DAP status f0000021? 1. Make sure the boot mode jumper JP5 is set to JTAG. If your Mode setting are JTAG and you are still having an issue then please attach a screen shot of your SDK errors? thank you, Jon
  33. 1 point
    are you maybe using a low-speed analog output with 200 ohms series resistor? Check the schematic of the board for a direct output.
  34. 1 point
    Well that's a pretty horrible looking 5 MHz signal coming directly out of an MMCM. It does remind me of the characteristic response of a particular passive component to a pulse, from decades ago when I took my intro electronics course. What do you think? Remind you of anything? I didn't mention the idea of scope probe compensation. It sure doesn't look like something that even a cheapo compensated probe would present for a low frequency signal out of a functioning FPGA pin into a high impedance load. Past that there are a number of usual suspects... but something is fundamentally wrong with your test setup.
  35. 1 point
    You can get the SDK to add a few example projects for any device in the system. Open the system.mss and click on the OS (the default is the standalone but you may have chosen another one when you created your BSP). Scroll down to the uart_x that you run through the PL and click on the demonstration examples. There is a nice variety of demonstrations and you probably want to add them all. The SDK will build these for the uart you selected. This is one nice feature of the SDK. If you chose another OS, such as the RTOS I'm not sure if examples are available. You likely want to use the interrupt driven example as a basis for your design ( depending on how you designed your overall software control). Of course, there are a lot of ways to arrange your communication protocol so I hope that you've spent some time thinking about how it will work. The simpler the better. Understand that the purpose of the example code is to show you the basic requirements to implement a particular interface and not to solve your problems... that is they are there for you to pore over and understand how they work. I can't send you code because your application is unique to you. If your SDK OS has a hardware abstraction layer then you will likely need to find other sources for example code. I rarely need (or want) a full-up OS like Linux for embedded applications. [edit] I should have mentioned that since you have at least two FPGA boards ( and ony you know what else ) you have a system. The basic system definition and design approach should be the first thing to flesh out. This includes inter-board communication; for instance are the boards peer-peer or is there a hierarchy? You can always tweak the system design if the lower level considerations demand it once you start fleshing out the actual implementation. If you haven't given any thought to the system interactions and structure then you are in for a lot of unnecessary work as the project nears integration.
  36. 1 point
    Nianyu Jiang

    PmodIA Extension

    https://www.researchgate.net/publication/236037769_A_four-electrode_low_frequency_impedance_spectroscopy_measurement_system_using_the_AD5933_measurement_chipt this is the paper I am talking about. Thanks for the further explaination, I start understanding the working principle and trying to combine everything. Will go back to you once I have more question. Nianyu Jiang
  37. 1 point
    Hi @bklopp, Here is a completed Nexys Video UART interrupt project in Vivado 2018.2 that uses interrupts in microblaze. thank you, Jon
  38. 1 point
    Hi @Amin, I know our content team is planning on updating our Petalinux projects. We currently do not have an ETA for this. Here is the Petalinux Support for Digilent Boards table that shows what Petalinux projects we have for our development boards and has a link to them as well. To use our most recent Petalinux release for the Zybo-Z7-20 I would suggest to download Vivado/SDK and Petalinux 2017.4. I would also suggest reading the Petalinux projects detailed readme as well. thank you, Jon
  39. 1 point
    jpeyron

    Source Code in SDK

    Hi @Ahmed Alfadhel, The most current version of the xbram examples I believe are here. thank you, Jon
  40. 1 point
    Hi @bklopp, 1) You do not need to use the JTAG HS2 to configure the Flash on the Nexys Video. I just saw the HS2 being mentioned in the txt file you attached. 2) I would also suggest leaving the spi mode for the QSPI flash IP set to Quad. thank you, Jon
  41. 1 point
    attila

    external p/s for analog discovery 2

    Szia @GaborG Unfortunately Analog Discovery and Digital Discovery are not working with RaspberryPI.
  42. 1 point
    jpeyron

    GPS Pmod

    Hi @HelplessGuy, To clarify you are trying to connect the Pmod GPS to the Zybo? Here is a completed Vivado 2018.2 Zybo/Pmod GPS without the sd card portion and using the interrupt. Here is a completed Vivado 2018.2 Zybo/Pmod GPS with the sd card portion and does not use the interrupt. Make sure you have the digilent board files installed correctly and that you fix the path to the vivado library to reflect where it is on your pc in Vivado's project manager->settings. thank you, Jon
  43. 1 point
    Hi @jli853, I reached out to one of our design engineers about this forum thread. They responded that "Unless you do a non-blocking (overlapped) transfer the time it takes to execute the function will include not only the time to transfer the data over USB but also to shift it onto the JTAG scan chain. When the function returns all data has been transferred to the target JTAG device. How long that takes is going to very with the TCK frequency, as well as the PC side hardware and operating system. I don’t have any measured data to provide." thank you, Jon
  44. 1 point
    jpeyron

    Labview with 7-segment display

    Hi @BROLYNE, I have not worked with multisim. I did find Digilent's Programming Digilent FPGA Boards Through Multisim and NI's Getting Started with Digilent Boards in Multisim tutorials that should help with getting the seven segment going. thank you, Jon
  45. 1 point
    Hi @sungsik, Those symbols show that the pins are differentially paired. The nomenclature of the pins also describe positive and negative. cheers, Jon
  46. 1 point
    xc6lx45

    Diving in

    >> it seems like it's very desirable to have a pure sin wave, Welcome to the world of radio engineering :) Very quick answer: Many modern receivers (e.g. take your cellphone) use a digital divider for LO generation that outputs a square LO signal. It actually gives higher mixer gain (which is good for noise) since the "switches" in the mixer conduct 100 % of the time and improves balance issues. The downside is, you get strong spurious responses at n times the LO frequency, which should be suppressed by filtering at the antenna side, before the mixer. But this is one problem from a very long list that you can probably ignore for a while. Generating a square LO is straightforward - simply use the clocking wizard to instantiate an MMCM/PLL. The chip does include LC oscillators (of which Colpitts is a textbook example) and they are digitally programmable. They can also provide 90 degree phase shifted outputs from a built-in divider. BTW, if you downconvert the ADC signal in software: You need a _decimating_ lowpass filter. Either that, or the number of MAC operations skyrockets (calculating samples that are mostly discarded).
  47. 1 point
    shahbaz

    How to read from SD card on ZYBO

    hi @jpeyron, I followed the guide at GitHub under Readme in PMODSD. can you please guide me step wise on how to start from block design and than going to SDK and running the demo. I have added the pmodsd and zynq PS IPs, after auto connection and running the generate bitstream I get following error. I need your guidance at this
  48. 1 point
    OK thanks. Yes, updating that tutorial would save a lot of time and confusion. I later noticed that Xilinx's page for 2017.2 has a bit more description relating to free WebPACK than the page for 2017.3, though it's still not clear how to invoke the free aspect. Further confusion is added by the Xilinx page you arrive at from Vivado's License Manager, as that page omits the Activation-based licenses, and the licenses it does show include a Free one for pre-2015, as though you can't license 2016 and later for free. Evidently that doesn't mean you can't use 2016 and later, it means that no license is required, and you don't need to be using the License Manager at all!
  49. 1 point
    attila

    Analog Discovery 2 vs Raspberry Pi 3

    FTDI USBs like AD, AD2, DD are not working with RPI model B (1,2,3) data packets/bytes are randomly lost. The EExplorer with different USB controller is working fine on these. All devices are working with other embeddeds: Zed, Zybo, BeagleBone… According reports AD is working with the original RPI model A and probably Zero because it has similar chipset/USB. The problem seems to be with FTDI or RPI B USB, library or hardware. You can find such comments regarding RPI problems with other devices too. Unfortunately we couldn't remediate this problem.
  50. 1 point
    hamster

    MMCM dynamic clocking

    I feel a bit bad about posting a minor novel here, but here is an example of going from "5 cycles on, 5 off" (i.e. divide by 10) to "10 on, 10 off" (device by 20). The VCO is initially to 800 MHz with CLK0 being VCO divide by 8.... so after config you get 100MHz. Push the button and you get 800/20 = 40MHz, release the button and you get 80MHz. It is all really hairy in practice! EDIT: Through experimentation I just found that you don't need to reset the MMCM if you are not changing the VCO frequency. So the 'rst' signal in the code below isn't needed (and LOCKED will stay asserted). -------------------------------------------------------------------------------------------------------- -- Playing with the MMCM DRP ports. -- see https://www.xilinx.com/support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf -- for the Dynamic Reconviguration Port addresses -------------------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity mmcm_reset is Port ( clk_100 : in STD_LOGIC; btn_raw : in STD_LOGIC; led : out STD_LOGIC_VECTOR (15 downto 0)); end mmcm_reset; architecture Behavioral of mmcm_reset is signal btn_meta : std_logic := '0'; signal btn : std_logic := '0'; signal speed_select : std_logic := '0'; signal counter : unsigned(26 downto 0) := (others => '0'); signal debounce : unsigned(15 downto 0) := (others => '0'); signal clk_switched : std_logic := '0'; signal clk_fb : std_logic := '0'; type t_state is (state_idle_fast, state_go_slow_1, state_go_slow_2, state_go_slow_3, state_idle_slow, state_go_fast_1, state_go_fast_2, state_go_fast_3); signal state : t_state := state_idle_fast; ----------------------------------------------------------------------------- --- This is the CLKOUT0 ClkReg1 address - the only register to be played with ----------------------------------------------------------------------------- signal daddr : std_logic_vector(6 downto 0) := "0001000"; signal do : std_logic_vector(15 downto 0) := (others => '0'); signal drdy : std_logic := '0'; signal den : std_logic := '0'; signal di : std_logic_vector(15 downto 0) := (others => '0'); signal dwe : std_logic := '0'; signal rst : std_logic := '0'; begin MMCME2_ADV_inst : MMCME2_ADV generic map ( BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW) CLKFBOUT_MULT_F => 8.0, -- Multiply value for all CLKOUT (2.000-64.000). CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000). -- CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). CLKIN1_PERIOD => 10.0, CLKIN2_PERIOD => 0.0, -- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128) CLKOUT1_DIVIDE => 1, CLKOUT2_DIVIDE => 1, CLKOUT3_DIVIDE => 1, CLKOUT4_DIVIDE => 1, CLKOUT5_DIVIDE => 1, CLKOUT6_DIVIDE => 1, CLKOUT0_DIVIDE_F => 8.0, -- Divide amount for CLKOUT0 (1.000-128.000). -- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.01-0.99). CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT2_DUTY_CYCLE => 0.5, CLKOUT3_DUTY_CYCLE => 0.5, CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5, CLKOUT6_DUTY_CYCLE => 0.5, -- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000). CLKOUT0_PHASE => 0.0, CLKOUT1_PHASE => 0.0, CLKOUT2_PHASE => 0.0, CLKOUT3_PHASE => 0.0, CLKOUT4_PHASE => 0.0, CLKOUT5_PHASE => 0.0, CLKOUT6_PHASE => 0.0, CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE) COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL DIVCLK_DIVIDE => 1, -- Master division value (1-106) -- REF_JITTER: Reference input jitter in UI (0.000-0.999). REF_JITTER1 => 0.0, REF_JITTER2 => 0.0, STARTUP_WAIT => FALSE, -- Delays DONE until MMCM is locked (FALSE, TRUE) -- Spread Spectrum: Spread Spectrum Attributes SS_EN => "FALSE", -- Enables spread spectrum (FALSE, TRUE) SS_MODE => "CENTER_HIGH", -- CENTER_HIGH, CENTER_LOW, DOWN_HIGH, DOWN_LOW SS_MOD_PERIOD => 10000, -- Spread spectrum modulation period (ns) (VALUES) -- USE_FINE_PS: Fine phase shift enable (TRUE/FALSE) CLKFBOUT_USE_FINE_PS => FALSE, CLKOUT0_USE_FINE_PS => FALSE, CLKOUT1_USE_FINE_PS => FALSE, CLKOUT2_USE_FINE_PS => FALSE, CLKOUT3_USE_FINE_PS => FALSE, CLKOUT4_USE_FINE_PS => FALSE, CLKOUT5_USE_FINE_PS => FALSE, CLKOUT6_USE_FINE_PS => FALSE ) port map ( -- Clock Outputs: 1-bit (each) output: User configurable clock outputs CLKOUT0 => clk_switched, CLKOUT0B => open, CLKOUT1 => open, CLKOUT1B => open, CLKOUT2 => open, CLKOUT2B => open, CLKOUT3 => open, CLKOUT3B => open, CLKOUT4 => open, CLKOUT5 => open, CLKOUT6 => open, -- Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs PSDONE => open, -- Feedback Clocks: 1-bit (each) output: Clock feedback ports CLKFBOUT => clk_fb, CLKFBOUTB => open, -- Status Ports: 1-bit (each) output: MMCM status ports CLKFBSTOPPED => open, CLKINSTOPPED => open, LOCKED => open, -- Clock Inputs: 1-bit (each) input: Clock inputs CLKIN1 => clk_100, CLKIN2 => '0', -- Control Ports: 1-bit (each) input: MMCM control ports CLKINSEL => '1', PWRDWN => '0', -- 1-bit input: Power-down RST => rst, -- 1-bit input: Reset -- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports DCLK => clk_100, -- 1-bit input: DRP clock DO => DO, -- 16-bit output: DRP data DRDY => DRDY, -- 1-bit output: DRP ready -- DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports DADDR => DADDR, -- 7-bit input: DRP address DEN => DEN, -- 1-bit input: DRP enable DI => DI, -- 16-bit input: DRP data DWE => DWE, -- 1-bit input: DRP write enable -- Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs PSCLK => '0', PSEN => '0', PSINCDEC => '0', -- Feedback Clocks: 1-bit (each) input: Clock feedback ports CLKFBIN => clk_fb ); speed_change_fsm: process(clk_100) begin if rising_edge(clk_100) then di <= (others => '0'); dwe <= '0'; den <= '0'; case state is when state_idle_fast => if speed_select = '1'then state <= state_go_slow_1; -- High 10 Low 10 di <= "0001" & "001010" & "001010"; dwe <= '1'; den <= '1'; end if; when state_go_slow_1 => if drdy = '1' then state <= state_go_slow_2; end if; when state_go_slow_2 => rst <= '1'; state <= state_go_slow_3; when state_go_slow_3 => rst <= '0'; state <= state_idle_slow; when state_idle_slow => di <= (others => '0'); if speed_select = '0' and drdy = '0' then state <= state_go_fast_1; -- High 5 Low 5 di <= "0001" & "000101" & "000101"; dwe <= '1'; den <= '1'; end if; when state_go_fast_1 => if drdy = '1' then state <= state_go_fast_2; end if; when state_go_fast_2 => rst <= '1'; state <= state_go_fast_3; when state_go_fast_3 => rst <= '0'; state <= state_idle_fast; end case; end if; end process; dbounce_proc: process(clk_100) begin if rising_edge(clk_100) then if speed_select = btn then debounce <= (others => '0'); elsif debounce(debounce'high) = '1' then speed_select <= not speed_select; else debounce <= debounce + 1; end if; -- Syncronise the button btn <= btn_meta; btn_meta <= btn_raw; end if; end process; show_speed_proc: process(clk_switched) begin if rising_edge(clk_switched) then counter <= counter + 1; led(7 downto 0) <= std_logic_vector(counter(counter'high downto counter'high-7)); end if; end process; led(15) <= speed_select; end Behavioral;