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  1. 2 points
    Hello @bitslip, Things are a little bit more complicated. Indeed, for changing the resolution you have to rewrite some registers. But you also need to make sure that the Video Trimming controller ip generates the required constants for you resolution. I wouldn't recommend to write all the needed registers from the control interface (it would be agonising) Instead I would go with the existent logic for changing the resolution, which is adding a new structure with all the register values. As an example, you can check the OV5640.H file. I much simple and quicker solution would be to use our video scaller ip. This ip was written in HLS and it was used in the fmc pcam adapter demo for re-scalling the video at a 640x480 resolution. You can check the design in here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-fmc-pcam-adapter-demo/start Best Regards, Bogdan Vanca
  2. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  3. 2 points
    kwilber

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  4. 2 points
    Hi @neocsc, Here is a verified Nexys Video HDMI project updated from Vivado 2016.4 to Vivado 2017.4. You should be able to find the updated project in the proj folder . Here is a GitHub project done in HDL using the clocking wizard, DVI2RGB and RGB2DVI IP Cores for another FPGA. Here is a unverified Nexys Video Vivado 2017.4 HDMI pass through project made from the linked Github project. In the next few days I should have the bandwidth to verify this project. thank you, Jon
  5. 2 points
    The warning you pasted is benign and simply means there are no ILAs present in your design. The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design. Finally, @elodg gives some great troubleshooting information in this thread.
  6. 2 points
    Hi @akhilahmed, In the mentioned video tutorial, the leds are controlled using "xgpio.h" library but the application is standalone. If you want to use a linux based application you have to use linux drivers for controlling. In the current Petalinux build, which is used in SDSoC platform, UIO driver is the best approach. Steps: 1. Vivado project generation: - Extract .dsa archive from /path_to_sdsoc_platform/zybo_z7_20/hw/zybo_z7_20.dsa - Launch Vivado - In Tcl Console: cd /path_to_extracted_dsa/prj - In Tcl Console: source rebuild.tcl - In this point you should have the vivado project which is the hardware component of SDSoC platform. Open Block Design. Change to Address Editor Tab. Here you will find the address for axi_gpio_led IP: 0x4122_0000 2. Petalinux UIO driver: - Launch SDx - Import zybo-z7-20 SDSoC platform - Create a new SDx linux based project using a sample application (e.g. array_zero_copy) - Build the project - Copy the files from /Dubug/sd_card to SD card - Plug the SD card in Zybo Z7. Make sure that the JP5 is set in SD position. Turn on the baord - Use your favorite serial terminal to interact with the board (115200, 8 data bits, 2 stop bits, none parity) - cd to /sys/class/uio - if you run ls you will get something like: uio0 uio1 uio2 uio3 uio4 uio5 - Now you have to iterate through all these directories and to search for the above mentioned axi_gpio_led address: 0x4122_0000 - For example: cat uio0/maps/map0/addr will output: 0x41220000, which means that the axi_gpio_led can be accessed using linux uio driver through uio0 device. - Code: #include <stdio.h> #include <stdlib.h> #include <sys/ioctl.h> #include <sys/mman.h> #include <stdint.h> #include <unistd.h> #include <fcntl.h> #define UIO_MEM_SIZE 65536 #define UIO_LED_PATH "/dev/uio0" void UioWrite32(uint8_t *uioMem, unsigned int offset, uint32_t data) { *((uint32_t*) (uioMem+offset)) = data; } uint32_t UioRead32(uint8_t *uioMem, unsigned int offset) { return *((uint32_t*) (uioMem+offset)); } void led_count_down(uint8_t *ledMem) { uint8_t count = 0xF; uint8_t index = 0; for (index = 0; index < 5; index++) { UioWrite32(ledMem, 0, count); count = count >> 1; sleep(1); } } int main() { // Set Leds as output int led_fd = open(UIO_LED_PATH, O_RDWR); uint8_t *ledMem = (uint8_t *) mmap( 0, UIO_MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, led_fd, (off_t)0); UioWrite32(ledMem, 4, 0x0); // Set all leds as output while(1) { // Start led count-down led_count_down(ledMem); } return 0; } - Build the project and copy the content of Debug/sd_card on SD sd_card - Power on the board and connect to it using a serial terminal - run the following commands: mount mmcblk0p1 /mnt cd /mnt ./project_name.elf - Result: A countdown should be displayed on leds.
  7. 2 points
    JColvin

    Arty A7 flash chip

    Hi @D@n, I believe the new part that is used in the Arty A7 boards (and other A7 boards) is now a Spansion S25FL128SAGMF100; based on old schematics, I believe this was added in Rev D of the Arty A7 (dated August 2017), though I do not know when that particular Rev was then released (or if it even was released) to the public. I confirmed that the Arty S7 also uses this part and I wouldn't be surprised if most of our other Artix 7 based boards use it now as well. I've requested that the chip name and images are updated in any appropriate tutorials and requested that the pdf version of the reference manual (updated wiki) is updated as well. Thanks, JColvin
  8. 1 point
    To clarify, the Microblaze clock was set to 100Mhz, and the Axi Quad SPI used the default internal frequency ratio, which I think is 16, so I got a SCLK frequency of around 6 Mhz. But you say that you fixed it, and I want to know which mode did you use and it's working properly with Pmod DA4?
  9. 1 point
    JColvin

    Storing Atlys PLB project to SPI/Flash

    Sweet, I'm glad to hear the design has been exported; I hope the bootloader side of things in SDK works as well.
  10. 1 point
    zygot

    Vitis

    @JColvin, I really appreciate your help. I suspect that I could have had more success by choosing the 'Hello' Application but why bother? I will pursue a Zedboard Vitis project and if it's interesting will post it. It'll be a tertiary level enterprise though. At this point I've concluded that Vitis and therefore Vivado 2019.2 or later are 'not ready for prime time'. Actually Vivado 2016.2 on WIn7 is my main HDL Xilinx toolset 'main squeeze' and except for a few idiosyncrasies gets the job done. At least I'm familiar with it's quirks. I still can't figure out why implementing a memory viewer in Vivado Simulator is so hard... Quartus has had a hardware memory tool for decades.... ISE ISIM can do it. A lot of my angst has to do with the knowledge that the Win7 box will die someday and I really haven't found a suitable successor yet. IF only Centos 6 were based on a slightly later Kernel it would be one OS to last (almost) forever.
  11. 1 point
    This is really something to consider in the long term. X and A have a strong interest to make us use their respective processor offerings. Nothing ever is for free and we may pay the price later when e.g. some third-party vendor (think China) shows up with more competitive FPGA silicon but I'd need a year for migrating my CPU-centric design. For industrial project reality, accepting vendor lock-in may be the smaller evil but if you have the freedom to look ahead strategically (personal competence development is maybe the most obvious reason for doing so, maybe also government funding) there may be wiser options. This is at least what keeps me interested in soft-core CPUs even though its absolute KPIs are abysmally bad.
  12. 1 point
    juliosilva

    4 analog Channel.

    Hello, I have an AD2 that I love. Sometimes I need 4 analog channels... if I buy other AD2 can I have 4 channels in the scope? I think not and I need to open 2 apps, if so is there a way that I can get the graph of both and join then on only 1 and take measurements after acquisition? Or is best to buy a 4ch scope? In this case what is the suggestions around the same price of AD2? Thanks!
  13. 1 point
    I receive and process serial data in this hack: http://hamsterworks.co.nz/mediawiki/index.php/PmodMAXSONAR It looks for an R character, then takes numeric ('0' to '9' ) that appear after that.
  14. 1 point
    JColvin

    PMODs - Spec 1.2.0

    Hi @andresb, I apologize for the delay. The best way to determine if they are complaint with specification 1.2.0 is by looking at their respect Resource Center (such as the Pmod AD1). On the right-hand side under Electrical, you will see the Specification version that the Pmod is currently compliant with. The Pmod Interface Specification 1.2.0 is available directly here: https://reference.digilentinc.com/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf. Let me know if you have any questions about this. Thanks, JColvin
  15. 1 point
    Hi @sgrobler, I am able to successfully connect to my phones WiFi hotspot on firmware 1.3.0. I get the same message pop-up as you regarding the firmware update required, but I click the "OK" option and then select the Instrument Panel where-upon am I greeted with the same message, choose OK again, and then I am brought to the Instrument Panel where I am able to successfully run the OpenLogger. I do agree though that the pop-up message should not be occurring though. I have reached to @AndrewHolzer to help address this. Thank you for the feedback, JColvin
  16. 1 point
    zygot

    Offline Installer

    I've been thinking that we've not been talking about the same things for a while now. In order to use your CMOD you need Vivado to create the configuration bitstreams. The last time I downloaded Vivado it was a file north of 40 GB. Yes, Gigabytes. Xilinx also supplies much smaller installers that require an internet connection in order to install Vivado on you PC. Digilent supplies tools for standalone configuration of the FPGA using bitstream that you create. Also, their tools can supplement Vivado to allow Vivado Hardware Manager to use the Digilent configuration facilities. Digilent also has software development tools and APIs for compiling your own software applications using various interfaces found on their FPGA boards. These files are all reasonably small. Trying to do FPGA development in a room or building without any internet access is going to be difficult without full support from the IT people maintaining your network and computing resources.
  17. 1 point
    Hey Paolo, I'm glad you found my videos helpful! I've been working on other projects, but if you have any other ideas for videos that you would find helpful let me know. Kaitlyn
  18. 1 point
    @ManserDimor Here's a general rule of thumb. Differential traces, whether laid out as differential or not must be length matched as best as possible. High speed bussed signals are usually length matched but normally this isn't nearly as critical as differential signalling; and this is usually done with a maximum data rate in mind. Everything else is usually assigned to the auto-router. Hand tuning traces is expensive and time consuming and usually there are a limited number that can be optimised with high ball count FPGA footprints. Usually, the focus is on external memory like DDR. If you need IO pins that are length matched then choose a board that makes it clear how well this was done. If the board vendor doesn't mention length matching then it was unlikely to have been done. Most of Digilent's boards with "high-speed" "differential" PMODS mention length matching in the reference manual. Some vendors offer a trace routing report of lengths for certain connectors. If differential signal traces are routed as true differential pairs then using them as single-ended signals might be problematic from a cross-coupling standpoint, especially if you don't take this into account. The only 3.3V differential IOSTANDARD supported by Series7 devices is TMDS and this is best done when the termination is as close to the receiver as possible. All of this does not necessarily mean that you can't design around a board's shortcomings to achieve some level of performance using a logic that the board wasn't designed for. This is one reason why all (most???) Series7 devices offer input delay management and in some cases output delay management features. There are boards from a few vendors with length matched GPIO on connectors are usually designed for high-speed. 2.56x2.56 mm connectors aren't that. Not many board vendors are going to go to the expense of designing a high performance board that they intend to sell at a cheap price. Final comment. If you are going to connect an external board or device to your FPGA board connector then you must assume the digital logic designer role required to do so.
  19. 1 point
    You can start with the following tutorials: http://www.ni.com/tutorial/14871/en/ https://reference.digilentinc.com/learn/programmable-logic/tutorials/program_fpgas_through_multisim/start
  20. 1 point
    Hi @m72 The pulse preview is not correct. I will look into this. Thank you for the observations. You could use a custom bus or signals to easily create/modify such patterns.
  21. 1 point
    Tim S.

    Pmod OLEDrgb with Zybo Z7

    Just to make sure my explanation is thorough. The above has a typo. It should read: Linux has a case-sensitive file system whereas Windows has a case-insensitive file system.
  22. 1 point
    You can find newer version 1.0.0.76 in the description of the video: https://www.youtube.com/watch?v=4d3hc-9zBaI
  23. 1 point
    attila

    Getting Input Phase Programmatically

    Hi @jamesbraza I constantly see the prefix `rg` in your programs. What is the meaning of `rg` prefix in all array namings? This are so called Hungarian notations originating from physics, to help identifying variable kinds like: rg Array, sz String, i Index, c Count Why does the gain term = V_C1 / V_C#? I would think it's the inverse... gain = output / input = V_C2 / V_C1 This is how the function returns it. You can convert it using 1.0/gain Does the formula you listed, M = gain2 - 1.0, come from a simplification of M = (V_C1 - V_C2) / (V_C2 - 0)? Yes. Also, please see the attached image. It's of input phase. Note sometimes the points are flipped about 360°. My final question is, do you know why this might be happening? The phase should be normalized to +/-PI. The next software version will correct this, but you can correct it in you script/application like this: if phase2.value > math.pi : phase2.value -= 2.0*math.pi if phase2.value < -math.pi : phase2.value += 2.0*math.pi Thank you for the observation.
  24. 1 point
    Hi @pikeaero, Welcome to the Digilent forums! best regards, Jon
  25. 1 point
    jpeyron

    ZedBoard and PmodCAN

    Hi @YellowYoung, Welcome to the Digilent forums! The PmodCAN facilitates CAN communication to another device through the PL.The PmodCAN uses SPI communication to communicate between the host board and itself. It would not be able to connect to the CAN on the PS. To use the CAN bus on the PS you would need to use the MIO Pmod JE1 as discussed in the user guide for the Zedboard here in section 2.9.2 Digilent Pmod Compatible Headers (2x6). The user guide states the bank that the MIO pins are connected to a 3.3V bank so you would need to make a level shifting circuit for CAN communication to work since CAN uses voltage level as part of its communication. If all you need to do is communicate data from the Zedboard using CAN communication. Then you can send data from the PS to the PL and then send that data through the PmodCAN. Here is an Avnet forum thread that discusses sending data from the PS to the PL. Here is a Xilinx forum thread that initially discusses how they accomplished sending data from the PS to the PL. best regards, Jon
  26. 1 point
    For the Protocol / SPI-I2C /Spy mode you should specify the approximate (or highest) protocol frequency which will be used to filter transient glitches, like ringing on clock signal transition. The Errors you get indicate the signals are not correctly captured. - make sure to have proper grounding between the devices/circuits - use twisted wires (signal/ground) to reduce EMI - use logic analyzer and/or scope to verify the captured data / voltage levels at higher sample rate at least 10x the protocol frequency Like here in the Logic Analyzer you can see a case when the samples are noisy:
  27. 1 point
    Hi @askhunter, The top.vhd is already added to the project. If you are wanting this file to be underneath the design_1 then you should right click on the design_1 and select add sources. Then add the vhdl files you would like to add to the design. It might be easier to start with a fresh project. best regards, Jon
  28. 1 point
    jpeyron

    Nexys 2 - transistor part number

    Hi @CVu, Glad to hear that replacing the transistor fix the issue. Thank you for sharing what you did. best regards, Jon
  29. 1 point
    kwilber

    NEXYS 3 frequency meter

    The problem is likely in the .ucf file where you define pin information. The error message says device pin LL8 doesn't exist. If you post the contents of your ucf, we can probably figure it out.
  30. 1 point
    Hi @kmesne, We responded to your other question here with some detail, but I will try to elaborate a little bit more here. The Pmod COLOR is not intended to detect colors from any sort of distance, so you would need it next to the red/green light indicator and then have it transmit data to the main controller for the car as opposed to be mounted on the car (unless the red/green indicator was on the car itself). I believe the Pmod COLOR could detect the green in a green cube, but it would need to be fairly well lit up due to the limitations of the sensor itself. As a bit of perspective, this will be a large and non-trivial state machine (especially for first semester project) with a lot of conditions to be covered; is light red or green to control the enable bit on 2+ H-bridge drivers running the motor, which needs to be checked frequently in order to obey traffic laws, as well as the enable bit being toggled as appropriate when changing input directions if the vehicle can go in reverse to avoid burning out the h-bridges, pwm control over the enable pin to allow the vehicle to turn; all done over (presumably) 3 remote systems communicating with each other; the controller with the direction buttons, the color sensor detecting the light change, and the RC vehicle itself. Which system/input will have priority in the state machine and how often will you need to check each input to provide a "smooth driving experience" will all be things that you need to consider. Some good resources for VHDL basics can be found at asic-world.com and fpga4fun.com, as well as this page that discusses state machine construction in VHDL. Thanks, JColvin
  31. 1 point
    kwilber

    Pmod DA3 clocking

    You may not have to build your own. That becomes a design decision that only you can make based on the requirements/specifications your design must meet. If the performance you are getting out of the Digilent IP meets your requirements, there is no reason to roll your own. On the other hand, if you are not able to meet your requirements and you are running up against limitations of the IP, then either look for a more performant IP or consider designing purpose specific logic. According to your measurements, it takes 40 bits sent at a rate of 3.125 Mhz for each update of the DAC. That is at least 12.8 microseconds per update. Take the inverse of that and you have a maximum update rate of 78,125 updates/second. Is that sufficient for your design?
  32. 1 point
    jpeyron

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, In section 2 Interfacing with the Pmod on page 1 of the reference manual for the Pmod DA3 here it states the pmod should use spi mode 0. thank you, Jon
  33. 1 point
    Hi @hello.parth, The Ethernet IP cores use the AXI BUS. You would need to implement the AXI BUS communication to interact with the Ethernet IP Cores. This is not an easy task. You do not need to use Microblaze or the Ethernet IP Cores to use the ethernet on the Nexys Video. Here is a community members( @hamster) VHDL GigabitTX project using the Nexys Video. thank you, Jon
  34. 1 point
    kwilber

    Simple HDMI pass through with NexysVideo

    Unfortunately, I do not have a NexysVideo board available. I have run the simple hdmi pass thru on both zybo and arty boards. Have you tried using a resolution of 720p yet? I find it useful to start with the lower frequencies first. Most sources and monitors have no trouble working with that.
  35. 1 point
    Hi @ebattaglia42, What operating system are you currently on? If you are Windows, can you attach a picture of what is shown in the Windows Device Manager and what you see in the WaveForms Device Manager (it should pop up when you initially connect the EE Board). The other thing I would suggest to try would be to use a different USB cable (make sure it's not just for charging only) and/or USB port on your computer as that is another source of error that is easy to check. Thank you, JColvin
  36. 1 point
    You can get the SDK to add a few example projects for any device in the system. Open the system.mss and click on the OS (the default is the standalone but you may have chosen another one when you created your BSP). Scroll down to the uart_x that you run through the PL and click on the demonstration examples. There is a nice variety of demonstrations and you probably want to add them all. The SDK will build these for the uart you selected. This is one nice feature of the SDK. If you chose another OS, such as the RTOS I'm not sure if examples are available. You likely want to use the interrupt driven example as a basis for your design ( depending on how you designed your overall software control). Of course, there are a lot of ways to arrange your communication protocol so I hope that you've spent some time thinking about how it will work. The simpler the better. Understand that the purpose of the example code is to show you the basic requirements to implement a particular interface and not to solve your problems... that is they are there for you to pore over and understand how they work. I can't send you code because your application is unique to you. If your SDK OS has a hardware abstraction layer then you will likely need to find other sources for example code. I rarely need (or want) a full-up OS like Linux for embedded applications. [edit] I should have mentioned that since you have at least two FPGA boards ( and ony you know what else ) you have a system. The basic system definition and design approach should be the first thing to flesh out. This includes inter-board communication; for instance are the boards peer-peer or is there a hierarchy? You can always tweak the system design if the lower level considerations demand it once you start fleshing out the actual implementation. If you haven't given any thought to the system interactions and structure then you are in for a lot of unnecessary work as the project nears integration.
  37. 1 point
    jpeyron

    Vivado and SDSoC with purchase

    Hi @Sduru, Welcome to the Digilent Forums. The list that comes with Vivado currently does not come with Digilent's board files included. You will need to install the board files as @kwilber describes above. thank you, Jon
  38. 1 point
    Hi @bklopp, Here is a completed Nexys Video UART interrupt project in Vivado 2018.2 that uses interrupts in microblaze. thank you, Jon
  39. 1 point
    Hi @Amin, I know our content team is planning on updating our Petalinux projects. We currently do not have an ETA for this. Here is the Petalinux Support for Digilent Boards table that shows what Petalinux projects we have for our development boards and has a link to them as well. To use our most recent Petalinux release for the Zybo-Z7-20 I would suggest to download Vivado/SDK and Petalinux 2017.4. I would also suggest reading the Petalinux projects detailed readme as well. thank you, Jon
  40. 1 point
    jpeyron

    Custom Image Processing on Zybo-Z7 20

    Hi @Amin, I have not made a project like this. To get a Zybo-Z7-20 project working with the SD card: Make sure you are using the Digilent board files.Here is the installation tutorial for the board files. Your block design should be the just the Zynq processor with FCLK_CLK0 connected to the M_AXI GP0_ACLK as shown with the attached screen shot. Run block automation as default(board files) when the Digilent board files are being used. Then create a wrapper and generate a bitstream. Next export the hardware including the bitstream and launch SDK. In SDK you should be able to alter the main.c file attache above to work for your needs. If your goal is to use a standalone project i can assist with using the ZYNQ processor with the SD card. I would have to reach out to more experience engineers for assistance using HLS or non-prebuilt SDSoC project. If your project does not need to be standalone then I would suggest using either an embedded linux project like petalinux , a pre-built SDSoC project or the SDSoC reVISION platform. 1) Here is the Petalinux Support for Digilent Boards which has two version releases and a very detailed readme which should help you get the project going. 2) Here is the SDSoC Platforms which has a project completed for the Zybo-Z7-20. 3) Here is the SDSoC reVISION project for the Zybo-Z7-20. thank you, Jon
  41. 1 point
    jpeyron

    Source Code in SDK

    Hi @Ahmed Alfadhel, The most current version of the xbram examples I believe are here. thank you, Jon
  42. 1 point
    Hi @Sami Malik, On Monday Ii will make a project and share it on this thread that I believe you are trying to do. thank you, Jon
  43. 1 point
    attila

    external p/s for analog discovery 2

    Szia @GaborG Unfortunately Analog Discovery and Digital Discovery are not working with RaspberryPI.
  44. 1 point
    jpeyron

    Labview with 7-segment display

    Hi @BROLYNE, I have not worked with multisim. I did find Digilent's Programming Digilent FPGA Boards Through Multisim and NI's Getting Started with Digilent Boards in Multisim tutorials that should help with getting the seven segment going. thank you, Jon
  45. 1 point
    They are to get a negative supply out of the positive digital output from the uC. Since the output of the uC is between 0 ... 3.3 V max. VREF1V5 is the node determining at which point the IC10A will switch from positive output to negative and vice versa. The opamp will always attempt to keep the difference between inverting and non-inverting inputs zero. VREF3V3 is a pullup of the inverting input, if the inverting input is pulled below 1.5V, the IC10A output will become positive in order to bring the inverting input back to 1.5V. On the other hand, when the inverting input is above 1.5V, the output of the IC10A will become negative to bring the inverting input back to 1.5V. I guess VREF3V0 could have been a higher voltage as well. But VREF1V5 should be as close to the center of the uC supply as possible in order to achieve symmetric output and the best resolution thereof. I'm also guessing they were not willing to rely on a stable supply voltage from the linear 3.3V regulator and probably already required a precision 3V reference for other purposes.
  46. 1 point
    Hello @Blake, I've created for you an image that test your FMC-HDMI adapter. It does a basic data transfer between the HDMI output of the ZedBoard and both of the adapter hdmi inputs. Prior to this it also uses all the I2C lines. Please check the .rar attached file. In order to recreate the test, please fallow the fallowing steps: 1.Make sure that you have everything in place, check the bellow instructions and the first image. Connect USB cable from PC to ZED USB PROG port (J17) Connect USB cable from PC to ZED UART port (J14) Connect FMC-HDMI board to FMC connector J1 (of ZED) Connect Power cable to J20 (of ZED) Set mode jumpers for JTAG programming (all to GND) Set J18 (of ZED) jumpers to 3V3 or 2V5. I'v tested both variants. Create a loop between HDMI-OUT J9(ZED) and FMC-HDMI IN1 of the adapter. Turn ZED board on 2. Open Vivado (I used Vivado 2017.4). Open Vivado, and click on Open Hardware Manager within the Welcome Page. After this click on Auto-Connect. You should see the Zed into the upper left panel.Check the image bellow. 3. Add Configuration Memory Device Right click on xc7z020_1 and choose "Add Configuration Memory Device". Check image bellow. 4. Choose the right memory device for ZED. Please choose "s25fl256s-3.3v-qspi-x1-dual_stacked" from the list. Click to program the device. Check images bellow. 5.Program the device with the files attached to this message. For "Configuration file" you choose BOOT.bin. For "Zynq Fsbl" you choose fsbl.elf. Click OK. 6. Wait until it gets programmed. After finish, you click OK. 7. Prepare the board for testing. Open a serial terminal, termite, putty, teraterm etc. Find the COM port and choose 115200 for baud rate. Set jumpers for QSPI programming (MIO5 on 3V3 and SIG, the others on 3V3 and GND). Power OFF the Board. Power ON the Board. The image should boot. See the image bellow. 8.Do the actually test. Make sure that the HDMI-OUT (ZED) is connected to HDMI-IN1 of the FMC-HDMI adapter. Press ENTER. Wait for the test to finalize. Make sure that the HDMI-OUT (ZED) is connected to HDMI-IN2 of the FMC-HDMI adapter. Make sure that your adapter is not loose. Press ENTER. Wait for the test to finalize. 9.Check the results, and give me an update . image.rar
  47. 1 point
    attila

    Math on FFT traces

    Hi @lab!fyi In the Network Analyzer extended option lets you use Wavegen channels at up to 20MHz and with external up to 50MHz. In the Spectrum Analyzer you can select frequency range up to 10MHz but with auto option lets you set Stop frequency up to 50MHz. Selecting the dB unit will let you specify custom reference, for dBm I think it should be 0.316V
  48. 1 point
    shahbaz

    How to read from SD card on ZYBO

    hi @jpeyron, I followed the guide at GitHub under Readme in PMODSD. can you please guide me step wise on how to start from block design and than going to SDK and running the demo. I have added the pmodsd and zynq PS IPs, after auto connection and running the generate bitstream I get following error. I need your guidance at this
  49. 1 point
    OK thanks. Yes, updating that tutorial would save a lot of time and confusion. I later noticed that Xilinx's page for 2017.2 has a bit more description relating to free WebPACK than the page for 2017.3, though it's still not clear how to invoke the free aspect. Further confusion is added by the Xilinx page you arrive at from Vivado's License Manager, as that page omits the Activation-based licenses, and the licenses it does show include a Free one for pre-2015, as though you can't license 2016 and later for free. Evidently that doesn't mean you can't use 2016 and later, it means that no license is required, and you don't need to be using the License Manager at all!