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  1. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  2. 2 points
    kwilber

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  3. 2 points
    Hi @neocsc, Here is a verified Nexys Video HDMI project updated from Vivado 2016.4 to Vivado 2017.4. You should be able to find the updated project in the proj folder . Here is a GitHub project done in HDL using the clocking wizard, DVI2RGB and RGB2DVI IP Cores for another FPGA. Here is a unverified Nexys Video Vivado 2017.4 HDMI pass through project made from the linked Github project. In the next few days I should have the bandwidth to verify this project. thank you, Jon
  4. 2 points
    The warning you pasted is benign and simply means there are no ILAs present in your design. The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design. Finally, @elodg gives some great troubleshooting information in this thread.
  5. 2 points
    Hi @akhilahmed, In the mentioned video tutorial, the leds are controlled using "xgpio.h" library but the application is standalone. If you want to use a linux based application you have to use linux drivers for controlling. In the current Petalinux build, which is used in SDSoC platform, UIO driver is the best approach. Steps: 1. Vivado project generation: - Extract .dsa archive from /path_to_sdsoc_platform/zybo_z7_20/hw/zybo_z7_20.dsa - Launch Vivado - In Tcl Console: cd /path_to_extracted_dsa/prj - In Tcl Console: source rebuild.tcl - In this point you should have the vivado project which is the hardware component of SDSoC platform. Open Block Design. Change to Address Editor Tab. Here you will find the address for axi_gpio_led IP: 0x4122_0000 2. Petalinux UIO driver: - Launch SDx - Import zybo-z7-20 SDSoC platform - Create a new SDx linux based project using a sample application (e.g. array_zero_copy) - Build the project - Copy the files from /Dubug/sd_card to SD card - Plug the SD card in Zybo Z7. Make sure that the JP5 is set in SD position. Turn on the baord - Use your favorite serial terminal to interact with the board (115200, 8 data bits, 2 stop bits, none parity) - cd to /sys/class/uio - if you run ls you will get something like: uio0 uio1 uio2 uio3 uio4 uio5 - Now you have to iterate through all these directories and to search for the above mentioned axi_gpio_led address: 0x4122_0000 - For example: cat uio0/maps/map0/addr will output: 0x41220000, which means that the axi_gpio_led can be accessed using linux uio driver through uio0 device. - Code: #include <stdio.h> #include <stdlib.h> #include <sys/ioctl.h> #include <sys/mman.h> #include <stdint.h> #include <unistd.h> #include <fcntl.h> #define UIO_MEM_SIZE 65536 #define UIO_LED_PATH "/dev/uio0" void UioWrite32(uint8_t *uioMem, unsigned int offset, uint32_t data) { *((uint32_t*) (uioMem+offset)) = data; } uint32_t UioRead32(uint8_t *uioMem, unsigned int offset) { return *((uint32_t*) (uioMem+offset)); } void led_count_down(uint8_t *ledMem) { uint8_t count = 0xF; uint8_t index = 0; for (index = 0; index < 5; index++) { UioWrite32(ledMem, 0, count); count = count >> 1; sleep(1); } } int main() { // Set Leds as output int led_fd = open(UIO_LED_PATH, O_RDWR); uint8_t *ledMem = (uint8_t *) mmap( 0, UIO_MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, led_fd, (off_t)0); UioWrite32(ledMem, 4, 0x0); // Set all leds as output while(1) { // Start led count-down led_count_down(ledMem); } return 0; } - Build the project and copy the content of Debug/sd_card on SD sd_card - Power on the board and connect to it using a serial terminal - run the following commands: mount mmcblk0p1 /mnt cd /mnt ./project_name.elf - Result: A countdown should be displayed on leds.
  6. 2 points
    JColvin

    Arty A7 flash chip

    Hi @D@n, I believe the new part that is used in the Arty A7 boards (and other A7 boards) is now a Spansion S25FL128SAGMF100; based on old schematics, I believe this was added in Rev D of the Arty A7 (dated August 2017), though I do not know when that particular Rev was then released (or if it even was released) to the public. I confirmed that the Arty S7 also uses this part and I wouldn't be surprised if most of our other Artix 7 based boards use it now as well. I've requested that the chip name and images are updated in any appropriate tutorials and requested that the pdf version of the reference manual (updated wiki) is updated as well. Thanks, JColvin
  7. 2 points
    @hamster I was able to run your AXI Slave interface. It works great! It is now very easy to exchange information between PS and PL, and it even supports execute-in-place (e.g. I can put ARM instructions to register file and run PS CPU directly from it). I have some questions about your AXI Slave design: 1) AXI_a*size has no effect on INCR type of burst transactions, but according to AXI protocol: the increment value depends on the size of the transfer. You set it only for WRAP type, is it correct? Thus, burst size is always 0 for INCR type? 2) Do you know how PS initiates INCR burst type? A kind of memset/memcpy need to be used for that or an incrementing pointer will also work? 3) Where WRAP type is necessary? How to use PS to work in WRAP mode? You may also update your wiki page with following: 0) Create provided VHDL files 1) Create a block-diagram and add PS IP core to it 2) Apply configuration provided by your board's pre-settings; this will set all necessary initialization settings for PS (e.g. clock frequencies, DDR bindings, etc.) 3) Press auto-configure (or how it's called) ==> this will connect PS IP to DDR and to fixed IO 4) Add "External ports" to the diagram (create new AXI_CLK and AXI external ports) and connect them to PS ports 5) Generate VHDL wrapping code for this block diagram 6) Put generated system under axi_test_top by renaming it to axi_test_wrapper (default name is design_#_wrapper in my Vivado version) 7) This will auto-connect block-diagram external ports with axi_test_top 8 ) Add constrains file and rename/uncomment external ports where necessary 9) Generate bitstream 10) File->Export->Hardware and create .hwf file which contains PS configuration 11) Open Xilinx SDK and create a new project: select .hwf file as Hardware BSP for this project 12) Now, Xilinx SDK will auto-generate few .c and .h files which contain necessary PS initialization ==> clocks, IRQs, DDR, etc. 13) Add hello_world.c application to the project @hamster Thank you very much. I've learned a bunch of new things thanks to your help!
  8. 1 point
    Hi @Ahmed Alfadhel I had the C code handy because I have been working on an atan2(y,x) implementation for FPGAs, and had been testing ideas. I left it in C because I don't really know your requirements, but I wanted to give you a working algorithm, complete with proof that it does work, and so you can tinker with it, see how it works, and make use of it. Oh, and I must admit that it was also because I am also lazy 😀 But seriously: - I don't know if you use VHDL or Verilog, or some HLS tool - I don't know if your inputs are 4 bits or 40 bits long, - I don''t know if you need the answer to be within 10% or 0.0001% - I don't know if it has to run at 40Mhz or 400Mhz - I don't know if you have 1000s of cycles to process each sample, or just one. - I don't even know if you need the algorithm at all! But it has been written to be trivially converted to any HDL as it only uses bit shifts and addition/subtraction. But maybe more importantly you can then use it during any subsequent debugging to verify that you correctly implemented it. For an example of how trivial it is to convert to HDL: if(x > 0) { x += -ty/8; y += tx/8;} else { x += ty/8; y += -tx/8;} could be implemented as IF x(x'high) = '0' THEN x := x - resize(y(y'high downto 3), y'length); y := y + resize(x(x'high downto 3), x'length); ELSE x := x + resize(y(y'high downto 3), y'length); y := y - resize(x(x'high downto 3), x'length); END IF My suggestion is that should you choose to use it, compile the C program, making the main() function a sort of test bench, and then work out exactly what you need to implement in your HDL., You will then spend very little time writing, debugging and improving the HDL because you will have a very clear idea of what you are implementing.
  9. 1 point
    Hi @kuc3, Welcome to the Digilent Forums! I have moved your thread to a sub-section where more experienced embedded linux engineers look. best regards, Jon
  10. 1 point
    D@n

    Noisy Output from FIR Compiler

    @Ahmed Alfadhel, You have a couple of options available to you: It's not clear, from your pictures above, whether or not the -40dB stop band was achieved. Some amount of noise is to be expected due to truncation errors, etc. Without seeing an estimated PSD, I can't tell. It may be that it's doing exactly what you required of it. -40dB is only so good. With more taps, you should be able to go deeper. How deep depends upon your requirements. How good do you want the signal to look? You may also need to provide more bits to both your signal and coefficient values in order to do better. You did prescale your coefficients so that, when rounded to integers, the taps were useful, right? Also, be aware, the filter will be specified for full scale. You'll want to measure it against a full scale input. Anything less will introduce additional truncation error. This is one of those reasons why the dynamic range (i.e. number of bits) of the input and output signals are so important. Enjoy! Dan
  11. 1 point
    Hi, For sw part I use Xilinx DMA driver (interface to VDMA IP core) and modified ADI AXI HDMI DRM driver for exposing frame buffer device to GUI sw (e.g. Qt). You can see driver bindings in above attached zyboz7-20.devicetree-1.zip (pl.dtsi). All video memory transfers to FPGA are managed by this two drivers.
  12. 1 point
    Yep, seen that they were back online. Thanks, Jon
  13. 1 point
    The example I posted would work for Linux or Mac with "common" tools installed. As to Windows... can't really help much there. git's not part of Python, it's used for managing code; you can achieve the same end result here by downloading the ZIP from https://github.com/bdlow/dlog-utils-portable/archive/master.zip and unzipping to a folder. Virtual environment support is a standard part of Python 3; you can skip that if you like but without virtual environments eventually your Python installation will end up like this: https://xkcd.com/1987/ Ah, of course, in Windows `activate` is a batch script not a shell script: https://www.techcoil.com/blog/how-to-create-a-python-3-virtual-environment-in-windows-10/
  14. 1 point
    jpeyron

    hdmi ip clocking error

    Hi @askhunter, I did a little more searching and found a forum thread here where the customer is having a similar issue. A community member also posted a pass through zynq project that should be useful for your project. best regards, Jon
  15. 1 point
    @longboard, Yeah, that's really confusing isn't it? At issue is the fact that many of these chips are specified in Mega BITS not BYTES. So the 1Gib is mean to refer to a one gigabit memory, which is also a 128 megabyte memory. That's what the parentheses are trying to tell you. Where this becomes a real problem is that I've always learned that a MiB is a reference to a million bytes, 10^6 bytes, rather than a mega byte, or 2^20 bytes. The proper acronyms, IMHO, should be Gb, GB, Mb, and MB rather than GiB or MiB which are entirely misleading. As for the memory, listed as 16 Meg x 8 x 8, that's a reference to 8-banks of 16-mega words or memory, where each word is 8-bits wide. In other words, the memory has 16MB*8 or 128MB of storage. You could alternatively say it had 1Gb of memory, which would be the same thing, but this is often confused with 1GB of memory--hence the desire for the parentheses again. Dan
  16. 1 point
    Hi @Phil_D The gain switch is adjusted automatically based on the selected scope range. At 500mV/div (5Vpk2pk ~0.3mV resolution) or lower the high gain is used with and above this the low gain (50Vpk2pk w ~3mV resolution). In case you specify trigger level out of the screen (5Vpk2pk) or offset higher/lower than +/- 2.5V the low gain will be used for the trigger source channel. This will be noted on the screen with red warning text. The attenuation is a different thing. This option lets you specify the external attenuation or amplification on the signals which enter the scope inputs and the data is scaled accordingly. Like, if you use a 10x scope probe, the scope input will actually get 1/10th of the original signal, but specifying 10x attenuation the signal is scaled to show values on the probe. In this case the 500mV/div (5Vpk2pk) low/high gain limit moves up to 5V/div (50Vpk2pk) and the low gain up to 50V/div If you have an external 100x amplifier on the scope input you can specify 0.01x attenuation. With this you will have 5mV/div (50mVpk2pk ~0.003mV resolution) for high gain.
  17. 1 point
    Hi @Jaraqui Peixe, Unfortunately, Digilent does not have the ability to obtain these licenses for you with regards to Xilinx negotiations. I do not doubt that the Spartan 3E Starter Boards you have are as good as new and work as such, but the reality is that last variant of ISE 14.7 that could support the FPGA chips on the Basys 2 and the Spartan 3E (both over 10 years old), was released by Xilinx back in 2013, so active support on these boards is limited as the required software will not install on newer OS's (at least the Windows variants anyway). As @xc6lx45, it is possible to make it work though. What I would probably recommend is looking into the newer 7 series boards, such as the Basys 3 (the most similar to the Basys 2) or if you would want access to more memory than is provided in BRAM, both the Arty A7 and the Nexys A7 have on-board DDR memory. All of these boards work with Microblaze and are supported by the free Vivado WebPACK from Xilinx (which is license-free if that is a factor for you and includes Microblaze). Naturally, there is no guarantee that the Vivado software that supports these Artix 7 FPGA chips will become end-of-life'd, but I can at least say from Digilent's end that I have not heard of this happening in the near future. Thanks, JColvin
  18. 1 point
    Hi, >> We are forced to work in assembly with picoblaze. you might have a look at the ZPU softcore CPU with GCC. The CPU is just a few hundred lines of code but most of its functionality is in software in the crt.o library in RAM. I understand it's quite well tested and has been used in commercial products. Not surprisingly, using an FPGA to implement a processor that then kinda emulates itself in software (aka RISC :) ) is maybe not the most efficient use of silicon - I'm sure it has many strong points but speed is not among them... Unfortunately, the broken-ness of Xilinx' DATA2MEM utility (to update the bitstream with a new .elf file) spoils the fun, at least when I tried in ISE14.7 (segfaults). When it works, the compile/build cycle takes only a second or two. Long-term, porting the processor to a new platform would be straightforward, or even fully transparent if using inferred, device-independent memory. This would also work for a bootloader that is hardcoded into default content in inferred RAM. I might consider this myself as a barebone "hackable" CPU platform strictly for educational purposes.
  19. 1 point
    jpeyron

    Nexys 2 - transistor part number

    Hi @CVu, Glad to hear that replacing the transistor fix the issue. Thank you for sharing what you did. best regards, Jon
  20. 1 point
    kwilber

    NEXYS 3 frequency meter

    The problem is likely in the .ucf file where you define pin information. The error message says device pin LL8 doesn't exist. If you post the contents of your ucf, we can probably figure it out.
  21. 1 point
    kwilber

    Pmod DA3 clocking

    You may not have to build your own. That becomes a design decision that only you can make based on the requirements/specifications your design must meet. If the performance you are getting out of the Digilent IP meets your requirements, there is no reason to roll your own. On the other hand, if you are not able to meet your requirements and you are running up against limitations of the IP, then either look for a more performant IP or consider designing purpose specific logic. According to your measurements, it takes 40 bits sent at a rate of 3.125 Mhz for each update of the DAC. That is at least 12.8 microseconds per update. Take the inverse of that and you have a maximum update rate of 78,125 updates/second. Is that sufficient for your design?
  22. 1 point
    jpeyron

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, In section 2 Interfacing with the Pmod on page 1 of the reference manual for the Pmod DA3 here it states the pmod should use spi mode 0. thank you, Jon
  23. 1 point
    Hi @hello.parth, The Ethernet IP cores use the AXI BUS. You would need to implement the AXI BUS communication to interact with the Ethernet IP Cores. This is not an easy task. You do not need to use Microblaze or the Ethernet IP Cores to use the ethernet on the Nexys Video. Here is a community members( @hamster) VHDL GigabitTX project using the Nexys Video. thank you, Jon
  24. 1 point
    D@n

    Conflicting Voltages in Bank Arty-A7

    @zygot, @Ahmed Alfadhel is not using a Basys3 board, and so this is really a bad example of attaching one question to another post. @Ahmed Alfadhel appears to be using an Artix-A7 board. In that case, the sys_clk is properly constrained, but he may well have some of the DDR3 I/O pins improperly constrained. These are the pins located on Bank 35. I think the problem in this case is that @Ahmed Alfadhel has improperly constrained in DDR DQS pins. For example, ddr3_dqs_[0] should be set to pin N2, not to A6. Compounding the problem is the way these pins are hidden in a "board definition file" rather than in the XDC file, making it likely to have conflicting pin definitions. @Ahmed Alfadhel, If you are following Digilent's instructions, you might want to double check that you have the appropriate board definition file. If you are trying this on your own, using only an XDC file, then you might find these instructions valuable. Also, I would recommend you not attach unrelated issues to old posts. Perhaps the Digilent staff might be kind enough to separate these two issues into separate forum posts--since they really are quite different. For example, the Basys3 board doesn't have the DDR3 memory which is the source of your pin-connection troubles. Dan
  25. 1 point
    kwilber

    Simple HDMI pass through with NexysVideo

    Unfortunately, I do not have a NexysVideo board available. I have run the simple hdmi pass thru on both zybo and arty boards. Have you tried using a resolution of 720p yet? I find it useful to start with the lower frequencies first. Most sources and monitors have no trouble working with that.
  26. 1 point
    are you maybe using a low-speed analog output with 200 ohms series resistor? Check the schematic of the board for a direct output.
  27. 1 point
    Nianyu Jiang

    PmodIA Extension

    https://www.researchgate.net/publication/236037769_A_four-electrode_low_frequency_impedance_spectroscopy_measurement_system_using_the_AD5933_measurement_chipt this is the paper I am talking about. Thanks for the further explaination, I start understanding the working principle and trying to combine everything. Will go back to you once I have more question. Nianyu Jiang
  28. 1 point
    kotra sharmila

    sdsoc_opencv error

    Hi , Thank you very much for this platform its showing video i/o demo and build perfectly i will try with my own project if i got any doubts i will ask you. Regards, K Sharmila
  29. 1 point
    jpeyron

    Custom Image Processing on Zybo-Z7 20

    Hi @Amin, I have not made a project like this. To get a Zybo-Z7-20 project working with the SD card: Make sure you are using the Digilent board files.Here is the installation tutorial for the board files. Your block design should be the just the Zynq processor with FCLK_CLK0 connected to the M_AXI GP0_ACLK as shown with the attached screen shot. Run block automation as default(board files) when the Digilent board files are being used. Then create a wrapper and generate a bitstream. Next export the hardware including the bitstream and launch SDK. In SDK you should be able to alter the main.c file attache above to work for your needs. If your goal is to use a standalone project i can assist with using the ZYNQ processor with the SD card. I would have to reach out to more experience engineers for assistance using HLS or non-prebuilt SDSoC project. If your project does not need to be standalone then I would suggest using either an embedded linux project like petalinux , a pre-built SDSoC project or the SDSoC reVISION platform. 1) Here is the Petalinux Support for Digilent Boards which has two version releases and a very detailed readme which should help you get the project going. 2) Here is the SDSoC Platforms which has a project completed for the Zybo-Z7-20. 3) Here is the SDSoC reVISION project for the Zybo-Z7-20. thank you, Jon
  30. 1 point
    Hi @Sami Malik, On Monday Ii will make a project and share it on this thread that I believe you are trying to do. thank you, Jon
  31. 1 point
    xc6lx45

    FFT / iFFT / RS - Basys3

    OK that starts to make more sense. So one channel is reference signal e.g. transmitted signal, one channel the received reflection. Capture both, FFT, multiply (don't forget the conjugate), iFFT. On the bright side, in this specific case you can solve the circularity issues mentioned above with sufficient zero padding on the transmit signal (rule of thumb: Add enough zeros until all reflections have died down to negligible level). This may be easier said than done with a hardware FFT, though... Resolution is limited to the sample rate. If you want to do better, you can interpolate by stealing lines 315..345 here . Needless to say, this calculation needs to be done on a microcontroller or the like. In double precision it's usually accurate to 1 % of a sample. For a reference algorithm, have a look here (this is more complex and somewhat heuristic but has proven itself over the years). With noise-free data this can be accurate to about one nanosample.
  32. 1 point
    jpeyron

    GPS Pmod

    Hi @HelplessGuy, To clarify you are trying to connect the Pmod GPS to the Zybo? Here is a completed Vivado 2018.2 Zybo/Pmod GPS without the sd card portion and using the interrupt. Here is a completed Vivado 2018.2 Zybo/Pmod GPS with the sd card portion and does not use the interrupt. Make sure you have the digilent board files installed correctly and that you fix the path to the vivado library to reflect where it is on your pc in Vivado's project manager->settings. thank you, Jon
  33. 1 point
    Hi @sungsik, Those symbols show that the pins are differentially paired. The nomenclature of the pins also describe positive and negative. cheers, Jon
  34. 1 point
    They are to get a negative supply out of the positive digital output from the uC. Since the output of the uC is between 0 ... 3.3 V max. VREF1V5 is the node determining at which point the IC10A will switch from positive output to negative and vice versa. The opamp will always attempt to keep the difference between inverting and non-inverting inputs zero. VREF3V3 is a pullup of the inverting input, if the inverting input is pulled below 1.5V, the IC10A output will become positive in order to bring the inverting input back to 1.5V. On the other hand, when the inverting input is above 1.5V, the output of the IC10A will become negative to bring the inverting input back to 1.5V. I guess VREF3V0 could have been a higher voltage as well. But VREF1V5 should be as close to the center of the uC supply as possible in order to achieve symmetric output and the best resolution thereof. I'm also guessing they were not willing to rely on a stable supply voltage from the linear 3.3V regulator and probably already required a precision 3V reference for other purposes.
  35. 1 point
    jpeyron

    Zedboard WiFi usage

    Hi @harika, Glad to hear you were able to get the bitstream to generate. cheers, Jon
  36. 1 point
    jpeyron

    Zedboard DMA Audio Demo problem

    Hi @Brinda, You want to download the release version of Zedboard DMA project here. I was able to generate a bitstream without issues in vivado 2016.4. Unfortunately, Vivado projects are version specific. This project was made in and works with Vivado 2016.4 without having to make alterations to the project. What version of Vivado are you using? cheers, Jon
  37. 1 point
    Hi @armin, Sorry for the confusion. I am suggesting that you program your Arty-A7 as you would normally through the usb uart. The program on the Arty-A7 should be a UART controller using pin E15 and E16 on Pmod Port JB for the TX and RX of the project. cheers, Jon
  38. 1 point
    attila

    Frequency profile generation with script

    Szia @Andras The Network Analyzer by default takes controls over the Wavegen channel 1 and configures the required frequency for each step. You could select NA/Wavegen/Channel/External but to be able the control the Wavegen manually, but in this case the previous Script solution won't work. The Insert/Local lists specific variables and is available in other scriptable places, like scope custom math, measurements, logging, network analyzer custom plots In each script editor including the Script tool you can use the Ctrl+Space to list available objects, variables... or child objects, properties, functions..
  39. 1 point
    attila

    Math on FFT traces

    Hi @lab!fyi In the Network Analyzer extended option lets you use Wavegen channels at up to 20MHz and with external up to 50MHz. In the Spectrum Analyzer you can select frequency range up to 10MHz but with auto option lets you set Stop frequency up to 50MHz. Selecting the dB unit will let you specify custom reference, for dBm I think it should be 0.316V
  40. 1 point
    Szia András, 1. The Spectrum Analyzer captures a buffer worth of data before processing it. For 200Hz it needs 400Hz capture of 8192 samples which takes 20 seconds. Reducing the number of samples to 1024 it will take 2.5 seconds. For slow progressive analysis you could use the FFT view in Scope with Scan Shift capture. 2. You can find the transparency option under WaveForms/Settings/Options. Also choosing light analog color might help in transparency. 3. You could do with a script like this eeg.dwf3work const neeg = 4 // sections const ceeg = 100 // history var rghistory = new Array(neeg); // history array for (var i = 0; i < neeg; i++) { // initialize array rghistory[i] = new Array(100); for(var j = 0; j < ceeg; j++) { rghistory[i][j] = 0 } } { // configure plot plot1.X.Units.text = "" plot1.X.Offset.value = -ceeg/2 plot1.X.Range.value = ceeg plot1.Y1.AutoScale.checked = false plot1.Y2.AutoScale.checked = false plot1.Y3.AutoScale.checked = false plot1.Y4.AutoScale.checked = false const vmax = 20 plot1.Y1.Offset.value = -vmax/2 plot1.Y2.Offset.value = -vmax/2 plot1.Y3.Offset.value = -vmax/2 plot1.Y4.Offset.value = -vmax/2 plot1.Y1.Range.value = vmax plot1.Y2.Range.value = vmax plot1.Y3.Range.value = vmax plot1.Y4.Range.value = vmax } Scope1.run() while(wait(0.5)){ // 0.5 second update rate var rgmag = Scope1.Channel1.fftmagnitude var rghz = Scope1.Channel1.fftfrequency var c = rgmag.length var rgeeg = [0,0,0,0] for(var i = 0; i < c; i++){ // calculate section power var hz = rghz[i] if(hz<4) rgeeg[0] += rgmag[i] else if(hz<7.5) rgeeg[1] += rgmag[i] else if(hz<12) rgeeg[2] += rgmag[i] else if(hz<30) rgeeg[3] += rgmag[i] } for(var i = 0; i < neeg; i++){ // shift history arrays rghistory[i].shift() rghistory[i].push(rgeeg[i]) } print(rgeeg[0],rgeeg[1],rgeeg[2],rgeeg[3]) plot1.Y1.data = rghistory[0] // yellow plot1.Y2.data = rghistory[1] // blue plot1.Y3.data = rghistory[2] // red plot1.Y4.data = rghistory[3] // green }
  41. 1 point
    Antonio Fasano

    Arty Z7 DRAM Memory

    Hi, Jon, I made a small software to test how big an array of char can be in SDK and still assign and read correct values on the ARTY-Z7-20 DRAM Memory. I found out that it goes all to way to 500 MB. I did not check further, but that is a hell of a memory capacity !!! Very good !!! Regards, Antonio
  42. 1 point
    Hi, @remalytics It can be definitely done by preparing custom software using Python, LabVIEW, etc...
  43. 1 point
    Hi @remalytics, I have moved you forum thread to a section where more experienced WaveForms/AD2 engineers look. thank you, Jon
  44. 1 point
    I should have known that you'd be around as I got this thread started. I'm thrilled to see a reply as I submit the first post. To answer you question; no I haven't but I promise to check out what you've been up to. If this venue fails to show interest I'd be happy to conspire with you to create one that does.
  45. 1 point
    Hi @Foisal Ahmed, I have not setup a project like this. I would suggest to look through the 7 Series FPGAs Configurable Logic Block User Guide. I would also reach out to xilinx support as well. thank you, Jon
  46. 1 point
    D@n

    XADC and the FFT

    @farhanazneen, I'm not sure how much help I can be if that error message doesn't make sense to you. You'll need to edit and "fix" your CSV file. Relax, it's text. Pull it up in an editor, examine it, then fix it. Dan
  47. 1 point
    shahbaz

    How to read from SD card on ZYBO

    hi @jpeyron, I followed the guide at GitHub under Readme in PMODSD. can you please guide me step wise on how to start from block design and than going to SDK and running the demo. I have added the pmodsd and zynq PS IPs, after auto connection and running the generate bitstream I get following error. I need your guidance at this
  48. 1 point
    Darryl Ring

    Arty7 xemacp undeclared

    This appears to be a known issue in 2018.2: https://www.xilinx.com/support/answers/71330.html. It appears that support for the emaclite driver got missed in a change (https://github.com/Xilinx/embeddedsw/commit/16c05f56fcb860513d34b83a1a301fa185e06316). Their patch can't actually be applied to Xilinx/SDK/2018.2/data/embeddedsw, but the changes are small and easy to make. I've attached the file here. It should replace ThirdParty/sw_services/lwip202_v1_1/src/contrib/ports/xilinx/netif/xadapter.c. Then you can regenerate the BSP sources and it will compile. xadapter.c
  49. 1 point
    lukeswr

    Adept library to use in visual .net c#

    I have an excellent example of interfacing with non-managed libraries using an internal sealed class. I have attached the file. I copied this foot print from another interface class regarding a USB interface. This example is nowhere near complete, but it provides the building block. using System; using System.IO; using System.Runtime.InteropServices; namespace Linear.common.lap.Digilent.Adept2 { /// <summary> /// This class library provides the 64-bit interface to the Digilent Inc. Adept2 dmgr library. /// </summary> internal sealed class StaticDmgr : IDisposable { // ReSharper disable InconsistentNaming /// <summary> /// The following value is passed to DmgrGetTransResult to specify /// wait until the transfer completes. /// </summary> public const UInt32 tmsWaitInfinite = 0xFFFFFFFF; // Handle to our DLL - used with GetProcAddress to load all of our functions private IntPtr hDMGR = IntPtr.Zero; // Declare pointers to each of the functions we are going to use in DMGR.DLL // These are assigned in our constructor and freed in our destructor. private readonly IntPtr pDmgrGetVersion = IntPtr.Zero; private readonly IntPtr pDmgrEnumDevices = IntPtr.Zero; private readonly IntPtr pDmgrGetDvc = IntPtr.Zero; private readonly IntPtr pDmgrIsEnumFinished = IntPtr.Zero; private readonly IntPtr pDmgrStopEnum = IntPtr.Zero; private readonly IntPtr pDmgrFreeDvcEnum = IntPtr.Zero; internal StaticDmgr() { // If DMGR.DLL is NOT loaded already, load it if (hDMGR == IntPtr.Zero) { // Load our DEPP.DLL library hDMGR = LoadLibrary(@"DMGR.DLL"); if (hDMGR == IntPtr.Zero) { // Failed to load our DEPP.DLL library from System32 or the application directory // Try the same directory that this Adept2 DLL is in hDMGR = LoadLibrary(@Path.GetDirectoryName(GetType().Assembly.Location) + "\\DMGR.DLL"); } } if (hDMGR == IntPtr.Zero) throw new ApplicationException("Cannot locate the driver's DMGR.DLL interface library."); // If we have succesfully loaded the library, get the function pointers set up // Set up our function pointers for use through our exported methods pDmgrGetVersion = GetProcAddress(hDMGR, "DmgrGetVersion"); pDmgrEnumDevices = GetProcAddress(hDMGR, "DmgrEnumDevices"); pDmgrGetDvc = GetProcAddress(hDMGR, "DmgrGetDvc"); pDmgrIsEnumFinished = GetProcAddress(hDMGR, "DmgrIsEnumFinished"); pDmgrStopEnum = GetProcAddress(hDMGR, "DmgrStopEnum"); pDmgrFreeDvcEnum = GetProcAddress(hDMGR, "DmgrFreeDvcEnum"); InitializeDelegates(); } private void InitializeDelegates() { if (pDmgrGetVersion == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrGetVersion."); if (pDmgrEnumDevices == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrEnumDevices."); if (pDmgrIsEnumFinished == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrIsEnumFinished."); if (pDmgrStopEnum == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrStopEnum."); if (pDmgrFreeDvcEnum == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrFreeDvcEnum."); DmgrGetVersion = (tDmgrGetVersion)Marshal.GetDelegateForFunctionPointer(pDmgrGetVersion, typeof(tDmgrGetVersion)); DmgrEnumDevices = (tDmgrEnumDevices)Marshal.GetDelegateForFunctionPointer(pDmgrEnumDevices, typeof(tDmgrEnumDevices)); DmgrGetDvc = (tDmgrGetDvc)Marshal.GetDelegateForFunctionPointer(pDmgrGetDvc, typeof(tDmgrGetDvc)); DmgrIsEnumFinished = (tDmgrIsEnumFinished)Marshal.GetDelegateForFunctionPointer(pDmgrIsEnumFinished, typeof(tDmgrIsEnumFinished)); DmgrStopEnum = (tDmgrStopEnum)Marshal.GetDelegateForFunctionPointer(pDmgrStopEnum, typeof(tDmgrStopEnum)); DmgrFreeDvcEnum = (tDmgrFreeDvcEnum)Marshal.GetDelegateForFunctionPointer(pDmgrFreeDvcEnum, typeof(tDmgrFreeDvcEnum)); } #region Instantiated Function Delegates internal tDmgrGetVersion DmgrGetVersion; internal tDmgrEnumDevices DmgrEnumDevices; internal tDmgrGetDvc DmgrGetDvc; internal tDmgrIsEnumFinished DmgrIsEnumFinished; internal tDmgrStopEnum DmgrStopEnum; internal tDmgrFreeDvcEnum DmgrFreeDvcEnum; #endregion #region IDisposable Methods /// <summary> /// Destructor for the D2XX class. /// </summary> ~StaticDmgr() { if (hDMGR != IntPtr.Zero) { // FreeLibrary here - we should only do this if we are completely finished FreeLibrary(hDMGR); hDMGR = IntPtr.Zero; } } public void Dispose() { if (hDMGR != IntPtr.Zero) { // FreeLibrary here - we should only do this if we are completely finished FreeLibrary(hDMGR); hDMGR = IntPtr.Zero; } } #endregion #region Marshalling Methods to Unmanaged DMGR /// <summary> /// Built-in Windows API functions to allow us to dynamically load our own DLL. /// Will allow us to use old versions of the DLL that do not have all of these functions available. /// </summary> [DllImport("kernel32.dll")] private static extern IntPtr LoadLibrary(string dllToLoad); [DllImport("kernel32.dll")] private static extern IntPtr GetProcAddress(IntPtr hModule, string procedureName); [DllImport("kernel32.dll")] private static extern bool FreeLibrary(IntPtr hModule); // Definitions for DMGR functions [UnmanagedFunctionPointer(CallingConvention.StdCall)] internal delegate int tDmgrGetVersion(byte[] szVersion); //OPEN & CLOSE functions internal delegate int tDmgrOpen(ref int phif, byte[] szSel); internal delegate int tDmgrOpenEx(ref int phif, byte[] szSel, int dtpTable, int dtpDisc); internal delegate int tDmgrClose(int hif); //ENUMERATION functions internal delegate int tDmgrEnumDevices(ref int pcdvc); //internal delegate int tDmgrEnumDevicesEx(ref int pcdvc, int dtpTable, int dtpDisc, int dinfoSel); //internal delegate int tDmgrStartEnum(ref int pcdvc); internal delegate int tDmgrIsEnumFinished(); internal delegate int tDmgrStopEnum(); //internal delegate int tDmgrGetEnumCount(ref int pcdvc); internal delegate int tDmgrGetDvc(int pcdvc, byte [] dvc); internal delegate int tDmgrFreeDvcEnum(); #endregion } }