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  1. 7 points
    attila

    WaveForms beta download

    3.15.5 digilent.waveforms_beta_v3.15.5_64bit.exe - Scope, Zoom view zoom options - more progress dialogs - recording for LabView VIs, go to MSO Read Block Diagram and increase the analog and digital array size as needed 3.15.4 digilent.waveforms_beta_v3.15.4_64bit.exe Added: - import support for Multisim CSV export: Transient to Scope, AC to Network Analyzer - time/data interpolation for import samples (Scope, Spectrum) - Scope/FFT graphics speedup for large number of BINs - Scope quick measure for large number of samples Fixing: - last word was not marked when: the SPI sampling was on falling edge, there were even number of words and the last word equals to the one before it - update checking on Windows, SSL library version 3.15.3 digilent.waveforms_beta_v3.15.3_64bit.exe Added: - auto reconnect to device - run and stop all instrument buttons - ki, Mi, Gi units - progress dialog for workspace compression - Scope: - smooth handling of huge number of samples - progress dialog for FFT, Math processes - adding Window trigger - Phase for Spectrum and Scope/FFT, cursors and export Fixing: - fixing eating first character of binary input text 3.15.2 Windows: digilent.waveforms_beta_v3.15.2_64bit.exe digilent.waveforms_beta_v3.15.2_32bit.exe MacOS: digilent.waveforms_beta_v3.15.2.dmg Linux 64bit: digilent.waveforms_beta_3.15.2_amd64.deb digilent.waveforms_beta_3.15.2.x86_64.rpm Linux 32bit: digilent.waveforms_beta_3.15.2_i386.deb digilent.waveforms_beta_3.15.2.i686.rpm Linux ARM 64bit: digilent.waveforms_beta_3.15.2_arm64.deb digilent.waveforms_beta_3.15.2.aarch64.rpm Linux ARM 32bit: digilent.waveforms_beta_3.15.2_armhf.deb digilent.waveforms_beta_3.15.2.armhf.rpm Changed: - Windows 64bit and MacOS updated to Qt5.12.9 - Windows XP compatible 32bit app still using Qt5.6.3 - Linux installers use system Qt5 libs - i386/amd64 build machine updated to Ubuntu 16.04 glibc 2.23 - armhf/aarch64 build machine updated to Ubuntu 18.04 glibc 2.27 Added: - Network Analyzer Phase Reference option Fixing: - MacOS file association - Analog Discovery oscilloscope calibration, min/max 0 failure - communication failure under VBox Linux and Adept Runtime 2.20.2 with Analog and Digital Discovery 3.13.23 Windows: digilent.waveforms_beta_v3.13.23_64bit.exe digilent.waveforms_beta_v3.13.23_32bit.exe MacOS: digilent.waveforms_beta_v3.13.23.dmg Linux 64bit: digilent.waveforms_beta_3.13.23_amd64.deb digilent.waveforms_beta_3.13.23.x86_64.rpm Linux 32bit: digilent.waveforms_beta_3.13.23_i386.deb digilent.waveforms_beta_3.13.23.i686.rpm Linux ARM 64bit: digilent.waveforms_beta_3.13.23_arm64.deb digilent.waveforms_beta_3.13.23.aarch64.rpm Linux ARM 32bit: digilent.waveforms_beta_3.13.23_armhf.deb digilent.waveforms_beta_3.13.23.armhf.rpm Fixing Digital Discovery Frequency setting 3.13.22 Windows: digilent.waveforms_beta_v3.13.22_64bit.exe digilent.waveforms_beta_v3.13.22_32bit.exe MacOS: digilent.waveforms_beta_v3.13.22.dmg Linux 64bit: digilent.waveforms_beta_3.13.22_amd64.deb digilent.waveforms_beta_3.13.22.x86_64.rpm Linux 32bit: digilent.waveforms_beta_3.13.22_i386.deb digilent.waveforms_beta_3.13.22.i686.rpm Linux ARM 64bit: digilent.waveforms_beta_3.13.22_arm64.deb digilent.waveforms_beta_3.13.22.aarch64.rpm Linux ARM 32bit: digilent.waveforms_beta_3.13.22_armhf.deb digilent.waveforms_beta_3.13.22.armhf.rpm Fixing known bugs 3.13.21 digilent.waveforms_beta_v3.13.21_64bit.exe Added: - Logic Analyzer Export All Events - AD2 7th device configuration Fixed: - Script plot with high offset/range ratio 3.13.20 Windows: digilent.waveforms_beta_v3.13.20-2_64bit.exe digilent.waveforms_beta_v3.13.20-2_32bit.exe MacOS: digilent.waveforms_beta_v3.13.20.dmg Linux 64bit: digilent.waveforms_beta_3.13.20_amd64.deb digilent.waveforms_beta_3.13.20.x86_64.rpm Linux ARM 64bit: digilent.waveforms_beta_3.13.20_arm64.deb digilent.waveforms_beta_3.13.20.aarch64.rpm Linux ARM 32bit: digilent.waveforms_beta_3.13.20_armhf.deb digilent.waveforms_beta_3.13.20.armhf.rpm Patch for RaspberryPi4B ERC 2 with Digital Discovery and Analog Discovery 1/2 with 2nd device configuration. Replace frequency/bandwidth limits option with warning. Fixing cleanup process, random WF app crash. 3.13.19 Windows: digilent.waveforms_beta_v3.13.19_64bit.exe digilent.waveforms_beta_v3.13.19_32bit.exe MacOS: digilent.waveforms_beta_v3.13.19.dmg Linux 64bit: digilent.waveforms_beta_3.13.19_amd64.deb digilent.waveforms_beta_3.13.19.x86_64.rpm Linux ARM 64bit: digilent.waveforms_beta_3.13.19_arm64.deb digilent.waveforms_beta_3.13.19.aarch64.rpm Linux ARM 32bit: digilent.waveforms_beta_3.13.19_armhf.deb digilent.waveforms_beta_3.13.19.armhf.rpm Fixing ERC 0x2 Linux and Raspberry Pi 4 B with AD, AD2, DD 3.13.18 digilent.waveforms_beta_v3.13.18_64bit.exe digilent.waveforms_beta_v3.13.18.dmg digilent.waveforms_beta_3.13.18_amd64.deb digilent.waveforms_beta_3.13.18.x86_64.rpm - Logic Analyzer - I2C interpreter remove restart, stop timing requirement - name option for Add Signal dialog - fixing analog curve in idle state and signed representation - fixing first value alignment - Select option for Event view - Cursors view: - name field - positioning plot on cursor row selection - Workspace: - multiple file selection for Extract - Compare tool based on capture device serial number 3.13.17 digilent.waveforms_beta_v3.13.17_64bit.exe Fixing know bugs 3.13.16 digilent.waveforms_beta_v3.13.16_64bit.exe Changed: - Network Analyzer rate improvement, Custom offset sweep - Logic Analyzer allowing large single captures Fixing know bugs 3.13.14 digilent.waveforms_beta_v3.13.14_64bit.exe Changed: - Saving workspace/project to temporary file first - Impedance Analyzer rate improvement Fixing known bugs 3.13.13 digilent.waveforms_beta_v3.13.13_64bit.exe Adding: - Logic Analyzer Import Binary, Script Logic.AddTab Fixing known bugs 3.13.12 digilent.waveforms_beta_v3.13.12_64bit.exe digilent.waveforms_beta_v3.13.12.dmg digilent.waveforms_beta_3.13.12_amd64.deb digilent.waveforms_beta_3.13.12.x86_64.rpm digilent.waveforms_beta_3.13.12_armhf.deb Fixing known bugs - Digital Discovery Logic Analyzer - application arguments 3.13.11 digilent.waveforms_beta_v3.13.11_64bit.exe Added: - FDwfDigitalSpiIdleSet Fixing known bugs 3.13.10 digilent.waveforms_beta_v3.13.10_64bit.exe digilent.waveforms_beta_v3.13.10.dmg digilent.waveforms_beta_3.13.10_amd64.deb digilent.waveforms_beta_3.13.10.x86_64.rpm Added: - Logic Analyzer: - Manchester interpreter - Trigger on CAN data Fixing known bugs 3.13.8 digilent.waveforms_beta_v3.13.8_64bit.exe digilent.waveforms_beta_3.13.8_amd64.deb digilent.waveforms_beta_3.13.8.x86_64.rpm Fixed: - Digital Discovery jitter 3.13.6 digilent.waveforms_beta_v3.13.6_64bit.exe digilent.waveforms_beta_v3.13.6.dmg digilent.waveforms_beta_3.13.6_amd64.deb digilent.waveforms_beta_3.13.6.x86_64.rpm ARM64: digilent.waveforms_beta_3.13.6_arm64.deb digilent.adept.runtime_2.20.0-arm64.deb digilent.adept.utilities_2.3.0-arm64.deb Fixing known bugs 3.13.1 digilent.waveforms_beta_v3.13.1_64bit.exe digilent.waveforms_beta_v3.13.1.dmg Added: - Play mode for Digital Discovery in Logic Analyzer - Protocol/UART Save Raw data Fixed: - Pattern Generator preview 3.11.34 digilent.waveforms_beta_v3.11.34_64bit.exe digilent.waveforms_beta_v3.11.34.dmg digilent.waveforms_beta_3.11.34_amd64.deb digilent.waveforms_beta_3.11.34.x86_64.rpm Fixing known bugs. 3.11.33 digilent.waveforms_beta_v3.11.33_64bit.exe digilent.waveforms_beta_v3.11.33.dmg digilent.waveforms_beta_3.11.33_amd64.deb digilent.waveforms_beta_3.11.33.x86_64.rpm Added: - Protocol: - SPI/I2C frequency filter option - SpiFlash (P5Q, M25P16) interpreter option for Spy - Network: - Radian unit for phase plot Fixing known bugs. 3.11.32 digilent.waveforms_beta_v3.11.32_64bit.exe digilent.waveforms_beta_3.11.32_amd64.deb digilent.waveforms_beta_3.11.32.x86_64.rpm Changed: - Protocol: CAN RX re-synchronization for rate tolerance, +/-10% Fixing known bugs. 3.11.31 digilent.waveforms_beta_v3.11.31_64bit.exe digilent.waveforms_beta_v3.11.31.dmg digilent.waveforms_beta_3.11.31_amd64.deb digilent.waveforms_beta_3.11.31.x86_64.rpm Added: - Script: access to windows, like Scope.window.size = [600, 400] Changed: - Logic: - CAN interpreter re-synchronization to increase rate tolerance - CAN trigger ignore substitute remote request bit - Protocol: using Digital Discovery system frequency adjustment Fixes: - Patterns: preview 3.11.30 digilent.waveforms_beta_v3.11.30_64bit.exe digilent.waveforms_beta_v3.11.30.dmg digilent.waveforms_beta_3.11.30_amd64.deb digilent.waveforms_beta_3.11.30.x86_64.rpm Fixing known bugs 3.11.29 digilent.waveforms_beta_v3.11.29_64bit.exe digilent.waveforms_beta_v3.11.29_32bit.exe digilent.waveforms_beta_v3.11.29.dmg digilent.waveforms_beta_3.11.29_amd64.deb digilent.waveforms_beta_3.11.29.x86_64.rpm Fixing known bugs 3.11.28 digilent.waveforms_beta_v3.11.28_64bit.exe digilent.waveforms_beta_3.11.28_amd64.deb digilent.waveforms_beta_3.11.28.x86_64.rpm Added: - Script: - find and replace - clear output button and function - Ctrl+Tab - Save All, Open multiple files 3.11.27 digilent.waveforms_beta_v3.11.27_64bit.exe digilent.waveforms_beta_v3.11.27.dmg digilent.waveforms_beta_3.11.27_amd64.deb digilent.waveforms_beta_3.11.27.x86_64.rpm Fixes and Help update 3.11.26 digilent.waveforms_beta_v3.11.26_64bit.exe digilent.waveforms_beta_v3.11.26.dmg digilent.waveforms_beta_3.11.26_amd64.deb digilent.waveforms_beta_3.11.26.x86_64.rpm Added: - Script: - multiple files for individual scripts or optional include Fixed: - Logic Analyzer: - keep order in Bus signals 3.11.25 digilent.waveforms_beta_v3.11.25_64bit.exe digilent.waveforms_beta_3.11.25_amd64.deb digilent.waveforms_beta_3.11.25.x86_64.rpm Fixed: - Protocol I2C Read with Script 3.11.24 digilent.waveforms_beta_v3.11.24_64bit.exe digilent.waveforms_beta_v3.11.24.dmg digilent.waveforms_beta_3.11.24_amd64.deb digilent.waveforms_beta_3.11.24.x86_64.rpm Added: - Wavegen: - period setting next to frequency Changed: - Protocol: - AVR programmer speed, functions, script access Fixed: - Network Analyzer: - phase averaging 3.11.22 digilent.waveforms_beta_v3.11.22_64bit.exe digilent.waveforms_beta_v3.11.22.dmg (not certified) digilent.waveforms_beta_3.11.22_amd64.deb digilent.waveforms_beta_3.11.22.x86_64.rpm Added: - Logic Analyzer: - SPI interpreter with MOSI/MOSI - HDMI CEC interpreter, trigger on: start, source, destination - Portocol: - AVR programmed: Flash, EEPROM, Fuse, Lock, Calibration - Scope/Logic remembers as default option: Show Attenuation, Acquire Noise, Multiple Scale - Pattern Generator negative delay option Changed: - Pattern Generator: - clock duty round up 3.11.21 digilent.waveforms_beta_v3.11.21_64bit.exe Fixed: - Patterns preview 3.11.20 digilent.waveforms_beta_v3.11.20_64bit.exe Added: - shared workspace list when running multiple applications Fixed: - Digital Discovery trigger position - Patterns preview for pulse - other minor fixes 3.11.19 digilent.waveforms_beta_v3.11.19_64bit.exe Added: - Patterns Delay option for signal/bus Fixed: - Digital Discovery system frequency adjustment 3.11.18 digilent.waveforms_beta_v3.11.18_64bit.exe Fixed: - Supplies for EExplorer and Analog Discovery 1 - Logic Analyzer Inputs for Digital Discovery 3.11.17 digilent.waveforms_beta_v3.11.17_64bit.exe Added: - Spectrum Units: V/vHz, dBm, dBm/vHz, dBm/vMHz - Digital Discovery: - system frequency (Pattern Generator and Logic Analyzer) fine adjustment from Supplies window 3.11.16 digilent.waveforms_beta_v3.11.16_64bit.exe Added: - Spectrum: - Units: dBm, dBmHz, dBmMHz Fixed: - Wavegen: Sync option 3.11.15 digilent.waveforms_beta_v3.11.15_64bit.exe Added: - SDK: - VB/C# ushort and uinteger modes for FDwfDigitalInStatusData/2/Noise/2 - replacing BOOL and BYTE types - manual update - Logic Analyzer: - 100 MHz limit option for Digital Discovery Fixed: - Spectrum: Persistence view axis labels for log scales - SDK: VB/C# wrappers FDwfAnalogInStatusData16 3.11.14 digilent.waveforms_beta_v3.11.14_64bit.exe digilent.waveforms_beta_3.11.14_amd64.deb digilent.waveforms_beta_3.11.14.x86_64.rpm Added: - Script access to Logic Analyzer measurements - System Monitor in Supplies window for AD1, AD2, DD Fixed: - SDK DwfParamOnClose continue running after re-open 3.11.13 digilent.waveforms_beta_v3.11.13_64bit.exe Added: - Network/Impedance Analyzer usage with constant frequency, start=stop - quick measure, cursors, horizontal axis as percentage 3.11.12 digilent.waveforms_beta_v3.11.12_64bit.exe digilent.waveforms_beta_3.11.12_amd64.deb digilent.waveforms_beta_3.11.12.x86_64.rpm Added: - Import data from file option for Spectrum, Network and Impedance Analyzer - trace toolbar width setting for Impedance Analyzer - AnalogOutIn_PlayRecord.py example playing mono and recording to stereo WAV file - FDwfAnalogImpedanceStatusInput phase normalization Fixed: - Analog Discovery 2 USB power monitor false 1A readings - wrong default reference for dBV in Spectrum Analyzer 3.11.11 digilent.waveforms_beta_v3.11.11_64bit.exe Added: - Logic Analyzer Bus interpreter: - either Clock edge option - sampling delay relative to edge - Events view lists sample for each edge when Clock signal is selected 3.11.10 digilent.waveforms_beta_v3.11.10_64bit.exe Added: - Scope scale for XYZ and Spectrogram 3D views - Export EPS image format - support for multiple transfers in Protocol/I2C/Sensor loop function 3.11.9 digilent.waveforms_beta_v3.11.9_64bit.exe Added: - Scope Spectrogram 3D surface view, for 64bit Windows 3.11.8 digilent.waveforms_beta_v3.11.8_64bit.exe digilent.waveforms_beta_v3.11.8.dmg digilent.waveforms_beta_3.11.8_amd64.deb digilent.waveforms_beta_3.11.8.x86_64.rpm Added: - horizontal cursors for Scope/FFT, Spectrum and Impedance Analyzer - cursor delta as decade for logarithmic scales - Scope: - simple Math channel operations: RMS, ATan - LockIn amplifier as Math channel - XYZ 3D graph, for 64bit Windows Fixed: - Scope/Audio/Tempo option 3.11.7 digilent.waveforms_beta_v3.11.7_64bit.exe digilent.waveforms_beta_v3.11.7.dmg digilent.waveforms_beta_3.11.7_amd64.deb digilent.waveforms_beta_3.11.7.x86_64.rpm minor fixes and improvements 3.11.6 digilent.waveforms_beta_v3.11.6_64bit.exe digilent.waveforms_beta_v3.11.6.dmg digilent.waveforms_beta_3.11.6_amd64.deb digilent.waveforms_beta_3.11.6.x86_64.rpm Added: - Protocol - UART Spy - Max Lines option: log limit to prevent application slowdown - Line Wrap option - tooltips for UI controls listing Script access path - application and script Font options - dark theme support for Script 3.11.5 digilent.waveforms_beta_v3.11.5_64bit.exe Added: - Script open/save text file - application argument: -script myscript.txt/js Fixed: - warnings at low record rates 3.11.4 digilent.waveforms_beta_v3.11.4_64bit.exe Added: - Scope: - set/reset zero offset in each channel option - precision option for measurements Fixed: - Script: access to traces and channels from Instrument.Export - unit conversions V to Ṽ, A to à - I2S 32 bit data 3.11.3 digilent.waveforms_beta_v3.11.3_64bit.exe digilent.waveforms_beta_3.11.3_amd64.deb digilent.waveforms_beta_3.11.3.x86_64.rpm Fixes 3.11.2 digilent.waveforms_beta_v3.11.2_64bit.exe digilent.waveforms_beta_3.11.2_amd64.deb digilent.waveforms_beta_3.11.2.x86_64.rpm Added: - Spectrum, Network and Impedance Analyzer store time data when this view is open Fixed: - runscript argument - loading of docked views geometry 3.11.1 digilent.waveforms_beta_v3.11.1_64bit.exe digilent.waveforms_beta_3.11.1_amd64.deb digilent.waveforms_beta_3.11.1.x86_64.rpm Added: - Scope: out of range warning in measurements - Protocol/UART: - support up to 32bit/word - TX/RX format: text, binary, decimal, hex - Wheel Direction option - Logic Analyzer: option to swap previous/next events - Spectrum Analyzer: allowing higher number of BINs for CZT 3.10.7 digilent.waveforms_beta_v3.10.7_64bit.exe Added: - Spectrum: logarithmic magnitude scale for voltage units - Protocol: datetime stamp for SPI/I2C Spy Fixes 3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom math channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Network Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.
  2. 3 points
    For anyone else out there who's struggling with DDR3 SDRAM on the Arty A7, here's a project for Vivado 2019.2 that builds out-of-box and successfully reads / writes (via the MIG user interface) to / from memory. Hopefully this'll save someone the pain I went through figuring out how to interface with the DDR-SDRAM via Verilog. Arty-SDRAM.zip
  3. 3 points
    Hi everyone, LINX can be installed on the Raspberry Pi 4. The LINX 3.0 Target Manual Install Process (https://www.labviewmakerhub.com/doku.php?id=learn:libraries:linx:misc:target-manual-install) did not work due to changes in the latest version of Raspbian. Here is the procedure that I used to install LINX. The procedure also works on the Raspberry Pi 2B, Pi 3A+, Pi 3B and Pi 3B+ running Raspbian Buster. 1. Setup the Raspberry Pi using the latest Raspbian Buster Image. 2. Change the default password for the Pi account on the Raspberry Pi. 3. Setup a WiFi or Ethernet connection from the Raspberry Pi to your router. 4. Enable SSH on the Raspberry Pi. 5. SSH into the Raspberry Pi or open a terminal window on the Raspberry Pi desktop. 6. Check that the Raspberry Pi can access the Internet by entering the command ping -c 4 raspberrypi.org 7. Enter the commands shown in bold below. Note: The text may wrap due to the web browser window size. I recommend copying the text into a text editor to see the original formatting. The commands are in the attached file linx_install_commands.txt # Enable i2c and spi sudo raspi-config nonint do_i2c 0 sudo raspi-config nonint do_spi 0 # Update Raspbian sudo apt-get update sudo apt-get dist-upgrade -y # Install LINX sudo sh -c 'echo "deb [trusted=yes] http://feeds.labviewmakerhub.com/debian/ binary/" >> /etc/apt/sources.list' sudo apt-get update sudo apt-get install -y lvrt-schroot # Move the nisysserver.service and labview.service files to the systemctl folder sudo mv /etc/systemd/system/multi-user.target.wants/nisysserver.service /lib/systemd/system sudo mv /etc/systemd/system/multi-user.target.wants/labview.service /lib/systemd/system # link liblinxdevice.so to the Raspberry PI device driver file liblinxdevice_rpi2.so sudo schroot -c labview -d /usr/lib -- ln -s liblinxdevice_rpi2.so liblinxdevice.so # Enable the nisysserver.service and labview.service to start on boot sudo systemctl enable nisysserver.service sudo systemctl enable labview.service # Start the nisysserver.service and labview.service sudo systemctl start nisysserver.service sudo systemctl start labview.service You should now be able to connect to the Raspberry Pi from the LabVIEW Project Explorer. Cheers, Andy. linx_install_commands.txt
  4. 3 points
    Ana-Maria Balas

    MTDS PMOD Connection issue

    Hello @WillTx, 1. There is an IP for Pmod MTDS with the drivers you need to make your Pmod MTDS working. It also contains 10 demos from which you can learn a lot. You can find it here : https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodMTDS_v1_0. You need to download the entire vivado-library (from here) then follow the tutorial for using Pmod IP cores in Vivado. 2. Your block design after adding the Pmod MTDS IP: 3. You can use the board flow to automatically connect to JB Pmod connector without a XDC constrain file (as it shows in the tutorial at step 3). You need to install the board files first. If you want to use the Cora-Z7-07S-Master.xdc constraint file, below are the lines corresponding to JB Pmod connector : 4. Please follow the REAME.txt found in drivers/PmodMTDS_v1_0/examples/ Cheers, Ana-Maria
  5. 3 points
    hearos

    FTDI chip not recognized anymore

    I have not had any activity listed when trying the "dmesg" so I went to buy a new cable, and that actually was it. Thank you for the hint!
  6. 3 points
    xc6lx45

    FTDI chip not recognized anymore

    I think it's Linux... Try the "dmesg" command immediately after plugging or unplugging. It should show some related events. The obvious, try with a different computer and a different cable. Especially cables fail often.
  7. 3 points
    Hi, reading between the lines of your post, you're just "stepping up" one level in FPGA design. I don't do long answers but here's my pick on the "important stuff" - Before, take one step back from the timing report and fix asynchronous inputs and outputs (e.g. LEDs and switches). Throw in a bunch of extra registers, or even "false-path" them. The problem (assuming this "beginner mistake") is that the design tries to sample them at the high clock rate. Which creates a near-impossible problem. Don't move further before this is understood, fixed and verified. - speaking of "verified": Read the detailed timing analysis and understand it. It'll take a few working hours to make sense of it but this is where a large part of "serious" design work happens. - Once the obvious problems are fixed, I need to understand what is the so-called "critical path" in the design and improve it. For a feedforward-style design (no feedback loops) this can be systematically done by inserting delay registers. The output is generated e.g. one clock cycle later but the design is able to run at a higher clock so overall performance improves. - Don't worry about floorplanning yet (if ever) - this comes in when the "automatic" intelligence of the tools fails. But, they are very good. - Do not optimize on a P&R result that fails timing catastrophically (as in your example - there are almost 2000 paths that fail). It can lead into a "rabbit's hole" where you optimize non-critical paths (which is usually a bad idea for long-term maintenance) - You may adjust your coding style based on the observations, e.g. throw in extra registers where they will "probably" make sense (even if those paths don't show up in the timing analysis, the extra registers allow the tools to essentially disregard them in optimization to focus on what is important) - There are a few tricks like forcing redundant registers to remain separate. Example, I have a dozen identical blocks that run on a common, fast 32-bit system clock and are critical to timing. Step 1, I sample the clock into a 32-bit register at each block's input to relax timing, and step 2) I declare these register as DONT_TOUCH because the tools would otherwise notice they are logically equivalent and try to use one shared instance. This as an example. - For BRAMs and DSP blocks, check the documentation where extra registers are needed (that get absorbed into the BRAM or DSP using a dedicated hardware register). This is the only way to reach the device's specified memory or DSP performance. - Read the warnings. Many relate to timing, e.g. when the design forces a BRAM or DSP to bypass a hardware register. - Finally, 260 MHz on Artix is already much harder than 130 MHz (very generally speaking). Usually feasible but you need to pay attention to what you're doing and design for it (e.g. a Microblaze with the wrong settings will most likely not make it through timing). - You might also have a look at the options ("strategy") but don't expect any miracles on a bad design. Ooops, this almost qualifies as "long" answer ...
  8. 3 points
    Ciprian

    Digital Twin

    Hi @Kris Persyn, It depends on how you manage your resources, driving immersive visuals on a HDMI display can be done in multiple ways at different resolutions, some are PL taxing others are DDR taxing; you could generate entire frame buffers in PL or PS or you could find a optimal algorithm to change just the previous frame or you could allocate a high number of frame buffers and then run them in a loop. It also depends on how math lab synthesizes the IP you will need to add to your design. If you design your project properly and don't aim for a resolution higher more 720p( I'm being conservative, we managed to drive the HDMI at 1080p with processing filters without a problem) I think it should be enough for what you want to do, resource wise. My suggestion, download and install Vivado, download and install the board files, create and implement your project look at the resource consumption and then buy a board. - Ciprian
  9. 3 points
    In your constraint file, the ddc pins have lowercase "ddc_scl_io" and "ddc_sda_io". Your block design has the port in uppercase "DDC". The case must match. Try editing your constraint file to have "DDC_scl_io" and "DDC_sda_io".
  10. 3 points
    jpeyron

    pmod wifi

    Hi @harika, I believe the HTML web page error is related to the materials on the SD card. 1) Please attach a screen shot of the contents of the Sd card you are using. 2) Please follow the YouTube video here from about 6 minutes and 28 seconds on for how to set up the HTTP server project. Make sure to update the login an password for the router/modem you are using. thank you, Jon
  11. 2 points
    JColvin

    Let me tell you why I HATE Digilent

    I do have to say that I was concerned when I initially clicked on this thread...but I think I'll let it stay. 😉 Please let us know if you have any questions about using the products! Thanks, JColvin P.S. I definitely sent this forum thread to our Scopes and Instruments product manager with minimal context to see what her reaction is.
  12. 2 points
    hamster

    RISC-V RV32I CPU/controller

    I've just posted my holiday project to Github - Rudi-RV32I - https://github.com/hamsternz/Rudi-RV32I It is a 32-bit CPU, memory and peripherals for a simple RISC-V microcontroller-sized system for use in an FPGA. A very compact implementation and can use under 750 LUTs and as little as two block RAMs - < 10% of an Artix-7 15T. All instructions can run in a single cycle, at around 50MHz to 75MHz. Actual performance currently depends on the complexity of system bus. It has full support for the RISC-V RV32I instructions, and has supporting files that allow you to use the RISC-V GNU toolchain (i.e. standard GCC C compiler) to compile programs and run them on your FPGA board. Here is an example of the sort of code I'm running on it - a simple echo test:, that counts characters on the GPIO port that I have connected to the LEDs. // These match the address of the peripherals on the system bus. volatile char *serial_tx = (char *)0xE0000000; volatile char *serial_tx_full = (char *)0xE0000004; volatile char *serial_rx = (char *)0xE0000008; volatile char *serial_rx_empty = (char *)0xE000000C; volatile int *gpio_value = (int *)0xE0000010; volatile int *gpio_direction = (int *)0xE0000014; int getchar(void) { // Wait until status is zero while(*serial_rx_empty) { } // Output character return *serial_rx; } int putchar(int c) { // Wait until status is zero while(*serial_tx_full) { } // Output character *serial_tx = c; return c; } int puts(char *s) { int n = 0; while(*s) { putchar(*s); s++; n++; } return n; } int test_program(void) { puts("System restart\r\n"); /* Run a serial port echo */ *gpio_direction = 0xFFFF; while(1) { putchar(getchar()); *gpio_value = *gpio_value + 1; } return 0; } As it doesn't have interrupts it isn't really a general purpose CPU, but somebody might find it useful for command and control of a larger FPGA project (converting button presses or serial data into control signals). It is released under the MIT license, so you can do pretty much whatever you want with it. Oh, all resources are inferred, so it is easily ported to different vendor FPGAs (unlike vendor IP controllers)
  13. 2 points
    I've spent some time since my first post trying to figure out what's in store for users with Vitis. With Vivado 2019.2 + Vitis you still need a Linux host to develop Petalinux applications. It was a chore, but I did manage to install Petalinux 2019.1 onto a Ubuntu 18.04 VM running in HyperV on my Win10 Pro box. This PC has 32 GB ram so I can allocate 8 GB to the VM. I haven't as yet actually created a project with the Petalinux tool this way yet. My plan is to wait and see how well Xilinx develops the tools with the next release before moving to 2019.2 and the new paradigm. Note that Vivado 2019.2 also breaks even Xilinx IP created in previous versions. For now I'm sticking with VIvado 2019.1 and Petalinux 2019.1. In 2019.2 tools Vivado and Vitis are not integrated. You still have to export hardware but you can't launch Vitis from Vivado. I'm assuming that at some point in the future users will start off in Vitis and launch Vivado from within that IDE. ** It's been my experience that overall performance with Linux VMs in WIn10 is poor unless you start with one of the 'optimized' quick start images from Msoft. Unfortunately, there is no way to change the default disk size of 12 GB, which is way too small do doing anything useful... like even install Petalinux. You can resize the VM disk size after creating the VM but you still need to install a disk management tool like Gparted onto your VM to re-size the Unbuntu partition to make use of the expanded disk size. Needless to say all of this should be done before completely setting up and updating the VM. The whole process of installing Petalinux was rather messy and time consuming. And HyperV is... well Msoft, so get used to frustration, pain and misery.
  14. 2 points
    Hello Frankly and welcome to our forum. Here are 2 patches that can be applied on top of a Petalinux 2019.1 project to allow reading the OTP MAC and configure it to do so. You can try applying them on 2018.2. Message us back if you have any issues. Cosmin 0001-Z7-20-allow-reading-MAC-address-from-OTP.patch 0002-Z7-20-use-OTP-MAC.patch
  15. 2 points
    I own three of FMC equipped boards that you mention and frequently use at least one on a regular basis. Just for arguments sake; lets say that I want to design my own FMC mezzanine card using all of those differential pairs. Where do I find the trace routing report letting me know what the trace lengths are for the Genesys2, Nexys Video and Zedboard?
  16. 2 points
    Hey Paolo, I'm glad you found my videos helpful! I've been working on other projects, but if you have any other ideas for videos that you would find helpful let me know. Kaitlyn
  17. 2 points
    D@n

    FAT32 with Zybo Z7

    @sgandhi, Welcome to data processing. The sad reality is that text files aren't good for this kind of thing. It's not an FPGA particular thing, but rather a basic reality. 1) Text files tend to take up too much space, and 2) they require processing to get the data into a format usable by an algorithm. One way to solve this problem, which I've done in the past with great success, is to rearrange the file so that's it's a binary file containing a large homogeneous area of elements all of the same type. In my case, I wanted a file that could be easily ingested (or produced) by MATLAB. I chose a binary format that had a header, followed by an NxM dimensional matrix of all single-precision floats. (You can choose whatever base type you want, but single-precision floats were useful for my application.) The header started with three fields: 1) First, there was a short marker to declare that this was the file type. I used 4-capital text letters for this marker. That was then followed by the 2) number of columns in the table, and then 3) the offset to the start of the table. This allowed me to place information about the data in further header fields, while still allowing the processor to skip directly from the beginning header to the data in question. Further, because the data was all of the same type, I could just about copy it directly into memory without doing any transformations, and to then operate on it there. It did help that the data was produced on a system with the same endianness as the system it was read from ... Dan
  18. 2 points
    artvvb

    Zybo Z7 Pcam 5C Demo - Warnings

    To add a little bit to what Jon said, these warnings appear to be ignorable. They all relate to design choices made when connecting custom IP in the block design. Typically, even when designing with Xilinx IP, many warnings are seen in the project. These messages are there to help get information on why something may be causing bigger problems later (errors, critical warnings, something not working in actual hardware). Note that even some critical warnings may be ignored. -Arthur
  19. 2 points
    There is no code to draw any shape as you observed since it was/is a work in progress. Thus it was excluded by default from `rootfs`. However it was mentioned by mistake in the first link you mentioned. https://reference.digilentinc.com/reference/software/petalinux/start The issue has been corrected.
  20. 2 points
    Hi, Sorry to barge in, but if anybody can point me to the Hibbert Transformer info I would be very grateful. However, here is an FPGA friendly way to calculate mag = sqrt(x*x+y*y), with about a 99% accuracy. You can easily see the pattern to get whatever accuracy you need. #include <math.h> #include <stdio.h> #define M_SCALE (16) /* Scaling for the magnitude calc */ void cordic_mag(int x,int y, int *mag) { int tx, ty; x *= M_SCALE; y *= M_SCALE; /* This step makes the CORDIC gain about 2 */ if(y < 0) { x = -(x+x/4-x/32-x/256); y = -(y+y/4-y/32-y/256); } else { x = (x+x/4-x/32-x/256); y = (y+y/4-y/32-y/256); } tx = x; ty = y; if(x > 0) { x += -ty/1; y += tx/1;} else { x += ty/1; y += -tx/1;} tx = x; ty = y; if(x > 0) { x += -ty/2; y += tx/2;} else { x += ty/2; y += -tx/2;} tx = x; ty = y; if(x > 0) { x += -ty/4; y += tx/4;} else { x += ty/4; y += -tx/4;} tx = x; ty = y; if(x > 0) { x += -ty/8; y += tx/8;} else { x += ty/8; y += -tx/8;} tx = x; ty = y; if(x > 0) { x += -ty/16; y += tx/16;} else { x += ty/16; y += -tx/16;} *mag = ty/M_SCALE/2; /* the 2 is to remove the CORDIC gain */ } int main(int argc, char *argv[]) { int i; int cases = 300; printf("Irput Calculated CORDIC Error\n"); for(i = 0; i < cases; i++) { float angle = 2*M_PI*i/cases; int x = sin(angle)*20000; int y = cos(angle)*20000; int mag, a_mag = (int)sqrt(x*x+y*y); cordic_mag(x,y, &mag); printf("%6i %6i = %6i vs %6i %4i\n", x, y, a_mag, mag, mag-a_mag); } } Oh, here is the output with a couple more iterations added. Irput Calculated CORDIC Error 0 20000 = 20000 vs 19999 -1 418 19995 = 19999 vs 19995 -4 837 19982 = 19999 vs 20001 2 1255 19960 = 19999 vs 19998 -1 1673 19929 = 19999 vs 19995 -4 2090 19890 = 19999 vs 20001 2 2506 19842 = 19999 vs 19998 -1 2921 19785 = 19999 vs 19996 -3 3335 19719 = 19999 vs 20001 2 3747 19645 = 19999 vs 19998 -1 4158 19562 = 19999 vs 19996 -3 4567 19471 = 19999 vs 20001 2 4973 19371 = 19999 vs 19997 -2 5378 19263 = 19999 vs 19996 -3 5780 19146 = 19999 vs 20001 2 6180 19021 = 19999 vs 19998 -1 6577 18887 = 19999 vs 19999 0 6971 18745 = 19999 vs 20001 2 7362 18595 = 19999 vs 19993 -6
  21. 2 points
    Grimmers

    Analog Discovery 2 vs Raspberry Pi 3

    Szia and Attila I got a Raspberry Pi 4 last week on release day (got the 2GB version as they sold out of 4GB in half a day) . Just got it plugged into the Analog Discovery and it works! Not really tried it for long but it seems to work reliably, but only well on USB3. On USB3 port, first time it wasn't recognised, but tried again after swapping devices around a then it was detected. Maybe it clashed with my wireless mouse dongle When I tried USB2 port, it connected immediately but I found that every few minutes (max 5-10mins) it would throw a device error window and I would have to clear and reconnect. Maybe RPi foundation kept the FTDI chipset for USB2 and used a new one for USB3 (Pi datasheet only says there is one chipset and it's not FTDI). I will try and soak test tomorrow, but looking good on USB3. So far it has been running 23mins with no apparent glitches, and Chromium tabs open. Waveforms taking 13-20% of CPU in task manager.
  22. 2 points
    xc6lx45

    FIR compiler 7.2 stopband

    ... and how about a simple impulse response test (feed a stream of zeroes with an occasional 1 and check that the filter coefficients appear at the output). Just wondering, isn't there a "ready / valid" interface also at the output if you expand the port with "+"?
  23. 2 points
    Hi @NikosFotias, I heard back from our design engineer about this; the recommend input ranges are 0V to 5V, but the absolute maximum ratings for the PWM inputs are -58V to 58V. Thank you, JColvin
  24. 2 points
    Thinking of which... actually I do have a plain-Verilog FIFO around from an old design. It's not a showroom piece but I think it did work as expected (whatever that is...) For 131072 elements you'd set ADDRBITS to 17 and DATABITS to 18 for 18 bit width. module FIFO(i_clk, i_reset, i_push, i_pushData, i_pop, o_popAck, o_popData, o_empty, o_full, o_error, o_nItems, o_nFree); parameter DATABITS = -1; parameter ADDRBITS = -1; localparam ADDR_ZERO = {{(ADDRBITS){1'b0}}}; localparam ADDR_ONE = {{(ADDRBITS-1){1'b0}}, 1'b1}; localparam DATA_X = {{(DATABITS){1'bx}}}; input wire i_clk; input wire i_push; input wire i_reset; input wire [DATABITS-1:0] i_pushData; input wire i_pop; output reg o_popAck = 1'b0; output wire [DATABITS-1:0] o_popData; output reg o_error = 1'b0; output wire [31:0] o_nItems; output wire [31:0] o_nFree; output wire o_empty; output wire o_full; reg popAckB = 1'b0; reg [DATABITS-1:0] mem[((1 << ADDRBITS)-1):0]; reg [ADDRBITS-1:0] pushPtr = ADDR_ZERO; reg [ADDRBITS-1:0] popPtr = ADDR_ZERO; reg [DATABITS-1:0] readReg = DATA_X; reg [DATABITS-1:0] readRegB = DATA_X; wire [ADDRBITS-1:0] nextPushPtr = i_push ? pushPtr + ADDR_ONE : pushPtr; wire [ADDRBITS-1:0] nextPopPtr = i_pop ? popPtr + ADDR_ONE : popPtr; assign o_popData = o_popAck ? readReg : DATA_X; // === items counter === // note: needs extra bit (e.g. 4 slots may hold [0, 1, 2, 3, 4] elements) reg [ADDRBITS:0] nItems; assign o_nItems = {{{31-ADDRBITS-1}{1'b0}}, nItems}; assign o_nFree = (1 << ADDRBITS) - nItems; localparam NITEMS_ONE = {{(ADDRBITS){1'b0}}, 1'b1}; assign o_empty = nItems == 0; assign o_full = nItems == {1'b1, {{ADDRBITS}{1'b0}}}; always @(posedge i_clk) begin // === preliminary assignments === readRegB <= DATA_X; popAckB <= 1'b0; case ({i_push, i_pop}) 2'b10: nItems <= nItems + NITEMS_ONE; 2'b01: nItems <= nItems - NITEMS_ONE; default: begin end endcase o_error <= (i_push && ~i_pop && o_full) || (i_pop && o_empty); // === output register (delay 1) === o_popAck <= popAckB; readReg <= readRegB; pushPtr <= nextPushPtr; popPtr <= nextPopPtr; if (i_push) mem[pushPtr] <= i_pushData; if (i_pop) begin readRegB <= mem[popPtr]; popAckB <= 1'b1; end if (i_reset) begin pushPtr <= ADDR_ZERO; popPtr <= ADDR_ZERO; o_error <= 1'b0; o_popAck <= 1'b0; popAckB <= 1'b0; readReg <= DATA_X; readRegB <= DATA_X; nItems <= 0; end end endmodule
  25. 2 points
    JColvin

    Read from MicroSD in HDL, Write on PC

    Hi @dcc, I'm not certain how you are verifying that the HDL is writing to and then reading back from the SD card in a normal formatting style, but in general FAT32 is a widely used format for SD cards that has existing material for it. I am uncertain why you are using a special tool to write to the SD card though; from what I can tell the tool is Windows compatible, so why not just use the Notepad program which comes with Windows and save a .txt file with the data you are interested in reading to the SD card or just using Windows Explorer (the file manager) to move the file of interest onto the SD card? If you do have a header in your file, you will need to take account for that, though I do not know what you mean by "random file" in this case. Thanks, JColvin
  26. 2 points
    SeanS

    Genesys 2 DDR Constraints

    Hi JColvin, I am definitely not using ISE. I think JPeyron had it correctly. I didn't have my board.Repopaths variable set and so the project wasn't finding the board files. Once I set this variable as suggested, the pin mapping and IO types were auto populated as expected. Kudos, Sean
  27. 2 points
    bogdan.deac

    OpenCV and Pcam5-c

    Hi @Esti.A, SDx, which includes SDSoC (Software Defined System on Chip), is a development environment that allows you to develop a computer vision application, in your case, using C/C++ and OpenCV library. The target of SDx-built applications are Xilinx systems on chip (SoC) (Zynq-7000 or Zynq Ultrascale+). Xilinx SoC architecture has two main components: ARM processor (single or multi core) named Processing System (PS) and FPGA, named Programmable Logic (PL). Using SDx to build an application for SoC allows you to choose which functions from your algorithm are executed in PS and which ones are executed in PL. SDx will generate all data movers and dependencies that you need to move data between PS, DDR memory and PL. The PL is suitable for operations that can be easily executed in parallel. So if you are going to choose a median filter function to be executed in PL, instead of PS, you will obtain a better throughput from your system. As you said, you can use OpenCV to develop your application. You have to take into account that OpenCV library was developed with CPU architecture in mind. So the library was designed to obtain the best performance on some specific CPU architectures (x86-64, ARM, etc.). If you are trying to accelerate an OpenCV function in PL using SDx you will obtain a poor performance. To overcome this issue, Xilinx has developed xfopencv, which is a subset if OpenCV library functions. The functionalities of xfopecv functions and OpenCV functions are the same but the xfopencv functions are implemented having FPGA architecture in mind. xfopencv was developed in C/C++ following some coding guideline. When you are building a project, the C/C++ code is given as input to Xilinx HLS (High Level Synthesis) tool that will convert it to HDL (Hardware Description Language) that will be synthetized for FPGA. The above mentioned coding guideline provides information about how to write C/C++ code that will be implemented efficiently in FPGA. To have a better understanding on xfopencv consult this documentation. So SDx helps you to obtain a better performance by offloading PS and by taking advantage of parallel execution capabilities of PL. Have a look on SDSoC documentation. For more details check this. An SoC is a complex system composed by a Zynq (ARM + FPGA), DDR memory and many types of peripherals. Above those, one can run a Linux distribution (usually Petalinux, from Xilinx) and above the Linux distribution, the user application will run. The user application may access the DDR memory and different types of peripherals (PCam in your case). Also, it may accelerate some functions in FPGA to obtain a better performance. To simplify the development pipeline Xilinx provides an abstract way to interact with, named SDSoC platform. SDSoC platform has two components: Software Component and Hardware Component that describes the system from the hardware to the operating system. Your application will interact with this platform. You are not supposed to know all details about this platform. This was the idea, to abstract things. Usually, the SDSoC platforms are provided by the SoC development boards providers, like Digilent. All you have to do is to download the last SDSoC platform release from github. You have to use SDx 2017.4. You don't have to build your own SDSoC platform. This is a complex task. You can follow these steps in order to build your first project that will use PCam and Zybo Z7 board. The interaction between PCam and the user application is done in the following way: there is an IP in FPGA that acquires live video stream from the camera, the video stream is written into DDR memory. This pipeline is abstracted by the SDSoC platform. The user application can access the video frames by Video4Linux (V4L2). The Live I/O for PCam demo shows you how to do this. I suggest you to read the proposed documentation to obtain a basic knowledge needed for SDSoC projects development. Best regards, Bogdan D.
  28. 2 points
    True. Zygot believes that making you work for knowledge is kinder than giving you solutions that can be used to mindlessly resolve your problem of the hour.... it's just a different philosophical bent...
  29. 2 points
    JColvin

    Pin Mapping for JTAG-SMT3-NC

    Hi @RussGlover, I apologize for the delay; the details you are looking are as follows: TCK - ADBUS0 TDI - ADBUS1 TDO - ADBUS2 TMS - ADBUS3 OEJTAG - ADBUS7 OESRSTN - ACBUS4 Let me know if you have any more questions. Thanks, JColvin
  30. 2 points
    kwilber

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  31. 2 points
    @Ahmed Alfadhel If you installed Vivado then you also installed the Xilinx Document Navigator. If you are serious about developing with FPGA devices you need to know how to find and access the plethora of documents that your vendor provides in order to use their devices properly. Check the box for 7 Series devices to see the list of reference manuals, User's Guides, Datasheets etc. From there you can add all relevant documents to your search and keep up to date. Do the same for ISE or Vivado tools. This is where everyone needs to start their Xilinx FPGA journey. Xilinx makes it easier than other FPGA vendors to obtain knowledge.
  32. 2 points
    The hot plug detect should be on the rx side. The source will see that and will then initiate the DDC conversation.
  33. 2 points
    Ciprian

    Hdmi out from zybo

    Try adding this: &i2c0 { clock-frequency = <100000>; status = "okay"; }; Here: <petalinux_project>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi -Ciprian
  34. 2 points
    The warning you pasted is benign and simply means there are no ILAs present in your design. The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design. Finally, @elodg gives some great troubleshooting information in this thread.
  35. 2 points
    Hi @aliff saad, Welcome to the forums. Here is the resource center for the PmodNAV. Here is a completed INO file, basically a main file, for the PmodNAV and an Arduino. The error is stating that LSM9DS1 is not assigned to a data type I.E. int, char... or in the case of the INO it is a class. Did you also download the SparkFun LSM9DS1 Arduino Library and add the src files to your project? cheers, Jon
  36. 2 points
    HI @yottabyte, I realize (based on the time stamps) that you figured out the answer to your question before you got a response, but do you mind posting your original question and what you found out so any future users with a similar question would be able to see the answer you (and xc6lx45) found out? Thanks, JColvin
  37. 2 points
    Flux

    VGA Pmod Tutorials

    The VGA tutorials have been updated with support for the Basys 3 and Nexys Video as well as Arty: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 I'm currently adding SVGA (800x600) support as well as working on more advanced effects. All the Verilog is available under the MIT license on GitHub: github.com/WillGreen/timetoexplore I look forward to sharing more projects with the community soon. Will
  38. 2 points
    Ciprian

    Zynq book - tutorial 5 Zybo Z7

    Hi @n3wbie, Th working project is attached. what you have to take in to account when using this audio codecs with Digilent products is that you need to configure the codec (using I2C) as well as receive the samples using I2S IP core. Basically one is for the control of the codec and the other one is to receive the samples. I have written a small driver for both the I2S core and the I2C SSM2603 which is in the source files of the SDK project (in the sdk folder) which configures the registers for the codec and I2S IP core; the documentation for the codec can be found here. The IP core has not yet been documented which is the main reason we have not added it to the Digilent vivado-ip library, but it needs a 100MHz input for it to be able to synthesize the 12.228 MHz MCLK and the subsequent clocks for the I2S protocol. The demo project reads the buttons and based on the ones you press it will: BTN0 - Record 1s BTN1 - Set Mic input BTN2 - Set Line In input BTN3 - Playback 1s The project is not really optimized so it uses a variable "RecSamples", allocated to the stack memory which holds the recorded samples(48000 samples representing 1s at a 48KHz sampling rate) and it is also used fro play back, so don't press play back before record. The rest should be easily traceable from the comments in the driver and the main source code. If you have any other questions feel fr to ask. Ciprian ZyboZ7Audio.zip
  39. 2 points
    JColvin

    Arty A7 flash chip

    Hi @[email protected], I believe the new part that is used in the Arty A7 boards (and other A7 boards) is now a Spansion S25FL128SAGMF100; based on old schematics, I believe this was added in Rev D of the Arty A7 (dated August 2017), though I do not know when that particular Rev was then released (or if it even was released) to the public. I confirmed that the Arty S7 also uses this part and I wouldn't be surprised if most of our other Artix 7 based boards use it now as well. I've requested that the chip name and images are updated in any appropriate tutorials and requested that the pdf version of the reference manual (updated wiki) is updated as well. Thanks, JColvin
  40. 2 points
    xc6lx45

    Diving in

    ... a slightly longer answer, if anybody is interested (analog mixing with square wave LO): One way is to look at the Fourier series of the square wave as a sum of sines at frequencies f, 3f, 5f, 7f, ... and to a lesser extent 2f, 4f, 6f from implementation imperfections. Then think of the mixer as linear multiplier, and use superposition (the distributive property of multiplication) for a*(b3+b5+b7+...) = a*b3+a*b5+a*b7+... Hint, if anybody wants to formally go through the math, it gets much less messy with cos(x) = (exp(ix)+exp(-ix))/2 aka DeMoivre. So you really get multiple frequency translations instead of one. What remains to be done is to manage the input signal energy at those frequencies I don't want, with a filter or narrow-band antenna. In the digital world, you'd always use a sine wave.
  41. 2 points
    jpeyron

    iMPACT Settings For SPI Programming

    Hi @bass2, Here is the Nexys 3 reference Manual.In the Memory section it discusses the 16 Mbyte Cellular RAM (Micron part number M45W8MW16) and the parallel PCM device (Micron part number NP8P128A13T1760E) and the 16 Mbyte serial PCM device (Micron part number NP5Q128A13ESFC0E). Here is a xilinx forum thread that discusses using iMPACT with the Nexys 3.Here is a tutorial on creating a .mcs file . cheers, Jon
  42. 2 points
    Hi @NYSD It is under development.
  43. 2 points
    Hi @spri Actually, the FDwfAnalogOutRunStatus returns not only the the remaining run but also the wait time. dwf.FDwfAnalogOutRunSet(hdwf, channel, c_double(2)) dwf.FDwfAnalogOutWaitSet(hdwf, channel, c_double(2)) dwf.FDwfAnalogOutRepeatSet(hdwf, channel, c_int(2)) dwf.FDwfAnalogOutConfigure(hdwf, channel, c_bool(True)) for i in range(10): sts = c_byte() sec = c_double() dwf.FDwfAnalogOutStatus(hdwf, channel, byref(sts)) dwf.FDwfAnalogOutRunStatus(hdwf, channel, byref(sec)) print("State: "+str(int(sts.value))+ " time left: "+ str(sec.value)) time.sleep(1) State: 7 time left: 1.99928738 // wait State: 7 time left: 1.00601063 State: 3 time left: 1.99434336 // run State: 3 time left: 0.97901375 State: 7 time left: 1.97874957 // wait State: 7 time left: 0.97872712 State: 3 time left: 1.9787507 // run State: 3 time left: 0.96878297 State: 2 time left: 0.0 // done @JColvin The *Get function return the configured value by *Set functions, like if you *Set the sample rate to 60MHz, the *Get will return the actually configured 50MHz, since the device can only do 100MHz, 50MHz, 33.3MHz...1uHz The *Status function return the monitorized information.
  44. 2 points
    attila

    Math on FFT traces

    Hi @lab!fyi The Script/Spectrum is added to the Help of beta version. Please use the Help of the application since this is the most up to date resource. https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ You could use Ctrl+Space, code completion: https://forum.digilentinc.com/topic/15433-more-meta-data-wanted/?do=findComment&amp;comment=37724 Beside this the code is JavaScript: http://www.ecma-international.org/publications/standards/Ecma-262.htm https://www.w3schools.com/jsref/jsref_obj_math.asp For next software version added support to set trace data from script.
  45. 2 points
    attila

    Math on FFT traces

    Hi @lab!fyi 1. I think for your experiment you should use the Network Analyzer interface of the WaveForms application. Connect the Scope channel 1 to your filter input and channel 2 to the output. By default, the analyzer plots the magnitude and phase of channel 2 relative to 1. This will give the characteristics of your filter. In the NA under Wavegen gear menu select channel external (let you use external or custom wavegen control) and frequency extended (to let you use up to 50MHz). The Scope Math channel is performed on the time domain data not on the FFT. 2. The persistence view will be update with the next software version to handle curve interpolation option as well the min/max sampling.
  46. 2 points
    @Foisal Ahmed, I'm not sure you understand what you are asking. Uninitialized logic values in Xilinx designs are already 1'b1's. This has caused me no end of grief in the past. Simulations treat initial values differently. Most simulations will treat an uninitialized value as an unknown until it is set. This is industry practice. I know Verilator tries to set unconstrained initial values to be random numbers. This is an exception to the industry practice that is done for performance reasons. The discrepancy between Verilator and Xilinx has been the root of much grief--since uninitialized things that work in Verilator don't always work in Xilinx. Depending upon a default initial value for registers within a design, however, is poor practice. The better approach is to force registers that need initial values to whatever initial value they should have. In Verilog, this is done using an 'initial' statement. In VHDL this can be done in the declaration statement, where the register is declared in the first place. Xilinx FPGA's by design will not release your design from its initial state unless all of your registers have their declared initial values. Were you to force all LUTs in a design to be 1'b1 initially, you would break any vendor supplied IP (i.e. DDR3SDRAM core, etc) you might be working with. Can you explain more of what you are trying to accomplish? Perhaps there's a better solution for what you wish to do. Dan
  47. 2 points
    BogdanVanca

    programming guide of zynq

    Hello @Ram, Please check this link : https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start "This guide will provide a step by step walk-through of creating a Zynq based hardware design using the Vivado IP Integrator that will build over the Getting Started with Zynqguide by making use of the on-board Ethernet port and GPIOs for the Zybo FPGA board.". You can start from here, and use the same hardware logic but different type of application for uart, spi etc. Best Regards, Bogdan Vanca
  48. 2 points
    jpeyron

    Zedboard Zynq 7000 XADC Header

    Hi @farhanazneen, I used the Analog Discovery 2 which has the 2x15 Flywires: Signal Cable Assembly for the Analog Discovery without issue. Each signal wire is 260mm± 20. thank you, Jon
  49. 2 points
    Notarobot

    How to read from SD card on ZYBO

    Hi shahbaz, If you are Ok using micro SD card adapter embedded in Zybo I would recommend to use it with the driver xsdps provided by Xilinx. Please note that it is connected and intended for use by PS not PL. The driver is located in Vivado library \embeddedsw\XilinxProcessorIPLib\drivers\sdps In Vivado the only thing is needed is enabling SD card in the processing system. Everything else is done in SDK. There you will need to add library xilffs to the BSP. File system and functions are described in here Good luck!
  50. 2 points
    Hi Dnappier, The clk wizard and the DVI2rgb both use a mmcm but they are on the same bank (bank 34). So to fix this issue you will need to open the clk_wiz_0 and select clocking options and select pll instead of mmcm. I have attached a fixed project of your design. thank you, Jon simple_project_esc.zip