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  1. 2 points
    Hello @Bryan_S, Here is a demo project for Cmod S6 from https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/start. I looked into the source files and there is clk_gen_50MHz.vhd. You can see in the top.vhd file how the clk_gen_50MHz is instantiated and used. I don't know what is the clk16x in your code, but here are some source files for serial port serialport_v3.zip The sources are for Nexys4 DDR which has a 100 MHz system clock. But in your case, if you use the clk_gen_50MHz, you'll have a 50 MHz clock instead of 100 MHz, 9600 baud rate, as shown in the UART_RX_CTRL.vhd file. The same for UART_TX_CTRL.vhd. I don't know if you'll use the sources from above, but I hope it helps. Best regards, Ana-Maria Balas
  2. 2 points
    Hello @bitslip, Things are a little bit more complicated. Indeed, for changing the resolution you have to rewrite some registers. But you also need to make sure that the Video Trimming controller ip generates the required constants for you resolution. I wouldn't recommend to write all the needed registers from the control interface (it would be agonising) Instead I would go with the existent logic for changing the resolution, which is adding a new structure with all the register values. As an example, you can check the OV5640.H file. I much simple and quicker solution would be to use our video scaller ip. This ip was written in HLS and it was used in the fmc pcam adapter demo for re-scalling the video at a 640x480 resolution. You can check the design in here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-fmc-pcam-adapter-demo/start Best Regards, Bogdan Vanca
  3. 2 points
    Hi @attila Thank you again for all the support you've provided me for the past weeks. I am now capable of receiving more than 409 characters using the Wrapper I created base from your example. It uses the Record acquisition mode and I set the buffer size to 3 million for now. I'll increase it when the need arises. I used 1 UART controller and branched out its Tx pin to 2 DIO pins of the AD2 (DIO #0 & 1). I transmitted 500 characters: (If Record mode is not the acquisition mode, the received result will be blank) For DIO # 0, it received: with a length of: For DIO #1, it received: with a length of: I could not have done it without your guidance, thank you again and more power to you and Digilent Best regards, Lesiastas
  4. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  5. 2 points
    kwilber

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  6. 2 points
    Hi @neocsc, Here is a verified Nexys Video HDMI project updated from Vivado 2016.4 to Vivado 2017.4. You should be able to find the updated project in the proj folder . Here is a GitHub project done in HDL using the clocking wizard, DVI2RGB and RGB2DVI IP Cores for another FPGA. Here is a unverified Nexys Video Vivado 2017.4 HDMI pass through project made from the linked Github project. In the next few days I should have the bandwidth to verify this project. thank you, Jon
  7. 2 points
    The warning you pasted is benign and simply means there are no ILAs present in your design. The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design. Finally, @elodg gives some great troubleshooting information in this thread.
  8. 2 points
    Hi @akhilahmed, In the mentioned video tutorial, the leds are controlled using "xgpio.h" library but the application is standalone. If you want to use a linux based application you have to use linux drivers for controlling. In the current Petalinux build, which is used in SDSoC platform, UIO driver is the best approach. Steps: 1. Vivado project generation: - Extract .dsa archive from /path_to_sdsoc_platform/zybo_z7_20/hw/zybo_z7_20.dsa - Launch Vivado - In Tcl Console: cd /path_to_extracted_dsa/prj - In Tcl Console: source rebuild.tcl - In this point you should have the vivado project which is the hardware component of SDSoC platform. Open Block Design. Change to Address Editor Tab. Here you will find the address for axi_gpio_led IP: 0x4122_0000 2. Petalinux UIO driver: - Launch SDx - Import zybo-z7-20 SDSoC platform - Create a new SDx linux based project using a sample application (e.g. array_zero_copy) - Build the project - Copy the files from /Dubug/sd_card to SD card - Plug the SD card in Zybo Z7. Make sure that the JP5 is set in SD position. Turn on the baord - Use your favorite serial terminal to interact with the board (115200, 8 data bits, 2 stop bits, none parity) - cd to /sys/class/uio - if you run ls you will get something like: uio0 uio1 uio2 uio3 uio4 uio5 - Now you have to iterate through all these directories and to search for the above mentioned axi_gpio_led address: 0x4122_0000 - For example: cat uio0/maps/map0/addr will output: 0x41220000, which means that the axi_gpio_led can be accessed using linux uio driver through uio0 device. - Code: #include <stdio.h> #include <stdlib.h> #include <sys/ioctl.h> #include <sys/mman.h> #include <stdint.h> #include <unistd.h> #include <fcntl.h> #define UIO_MEM_SIZE 65536 #define UIO_LED_PATH "/dev/uio0" void UioWrite32(uint8_t *uioMem, unsigned int offset, uint32_t data) { *((uint32_t*) (uioMem+offset)) = data; } uint32_t UioRead32(uint8_t *uioMem, unsigned int offset) { return *((uint32_t*) (uioMem+offset)); } void led_count_down(uint8_t *ledMem) { uint8_t count = 0xF; uint8_t index = 0; for (index = 0; index < 5; index++) { UioWrite32(ledMem, 0, count); count = count >> 1; sleep(1); } } int main() { // Set Leds as output int led_fd = open(UIO_LED_PATH, O_RDWR); uint8_t *ledMem = (uint8_t *) mmap( 0, UIO_MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, led_fd, (off_t)0); UioWrite32(ledMem, 4, 0x0); // Set all leds as output while(1) { // Start led count-down led_count_down(ledMem); } return 0; } - Build the project and copy the content of Debug/sd_card on SD sd_card - Power on the board and connect to it using a serial terminal - run the following commands: mount mmcblk0p1 /mnt cd /mnt ./project_name.elf - Result: A countdown should be displayed on leds.
  9. 2 points
    JColvin

    Arty A7 flash chip

    Hi @D@n, I believe the new part that is used in the Arty A7 boards (and other A7 boards) is now a Spansion S25FL128SAGMF100; based on old schematics, I believe this was added in Rev D of the Arty A7 (dated August 2017), though I do not know when that particular Rev was then released (or if it even was released) to the public. I confirmed that the Arty S7 also uses this part and I wouldn't be surprised if most of our other Artix 7 based boards use it now as well. I've requested that the chip name and images are updated in any appropriate tutorials and requested that the pdf version of the reference manual (updated wiki) is updated as well. Thanks, JColvin
  10. 2 points
    attila

    Math on FFT traces

    Hi @lab!fyi In the Network Analyzer extended option lets you use Wavegen channels at up to 20MHz and with external up to 50MHz. In the Spectrum Analyzer you can select frequency range up to 10MHz but with auto option lets you set Stop frequency up to 50MHz. Selecting the dB unit will let you specify custom reference, for dBm I think it should be 0.316V
  11. 2 points
    @hamster I was able to run your AXI Slave interface. It works great! It is now very easy to exchange information between PS and PL, and it even supports execute-in-place (e.g. I can put ARM instructions to register file and run PS CPU directly from it). I have some questions about your AXI Slave design: 1) AXI_a*size has no effect on INCR type of burst transactions, but according to AXI protocol: the increment value depends on the size of the transfer. You set it only for WRAP type, is it correct? Thus, burst size is always 0 for INCR type? 2) Do you know how PS initiates INCR burst type? A kind of memset/memcpy need to be used for that or an incrementing pointer will also work? 3) Where WRAP type is necessary? How to use PS to work in WRAP mode? You may also update your wiki page with following: 0) Create provided VHDL files 1) Create a block-diagram and add PS IP core to it 2) Apply configuration provided by your board's pre-settings; this will set all necessary initialization settings for PS (e.g. clock frequencies, DDR bindings, etc.) 3) Press auto-configure (or how it's called) ==> this will connect PS IP to DDR and to fixed IO 4) Add "External ports" to the diagram (create new AXI_CLK and AXI external ports) and connect them to PS ports 5) Generate VHDL wrapping code for this block diagram 6) Put generated system under axi_test_top by renaming it to axi_test_wrapper (default name is design_#_wrapper in my Vivado version) 7) This will auto-connect block-diagram external ports with axi_test_top 8 ) Add constrains file and rename/uncomment external ports where necessary 9) Generate bitstream 10) File->Export->Hardware and create .hwf file which contains PS configuration 11) Open Xilinx SDK and create a new project: select .hwf file as Hardware BSP for this project 12) Now, Xilinx SDK will auto-generate few .c and .h files which contain necessary PS initialization ==> clocks, IRQs, DDR, etc. 13) Add hello_world.c application to the project @hamster Thank you very much. I've learned a bunch of new things thanks to your help!
  12. 2 points
    mohammadhgh

    Zybo z7-20 Zynq Presets

    Hi @Mahesh, As @jpeyron said in the post marked as accepted solution, the Zynq processing system will be configured with the board presets when you first add the Zynq processing system IP core to the block design and run the block automation task from the green message that appears! Just remember to keep the Apply Board Preset option checked as shown in he picture. So this means if you are using the pre-built block design from the example project, a possible solution can be to remove the existing Zynq processing system block and adding a new one!
  13. 2 points
    attila

    Analog Discovery 2 vs Raspberry Pi 3

    FTDI USBs like AD, AD2, DD are not working with RPI model B (1,2,3) data packets/bytes are randomly lost. The EExplorer with different USB controller is working fine on these. All devices are working with other embeddeds: Zed, Zybo, BeagleBone… According reports AD is working with the original RPI model A and probably Zero because it has similar chipset/USB. The problem seems to be with FTDI or RPI B USB, library or hardware. You can find such comments regarding RPI problems with other devices too. Unfortunately we couldn't remediate this problem.
  14. 1 point
    JColvin

    PMODs - Spec 1.2.0

    Hi @andresb, I apologize for the delay. The best way to determine if they are complaint with specification 1.2.0 is by looking at their respect Resource Center (such as the Pmod AD1). On the right-hand side under Electrical, you will see the Specification version that the Pmod is currently compliant with. The Pmod Interface Specification 1.2.0 is available directly here: https://reference.digilentinc.com/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf. Let me know if you have any questions about this. Thanks, JColvin
  15. 1 point
    Hi @sgrobler, I am able to successfully connect to my phones WiFi hotspot on firmware 1.3.0. I get the same message pop-up as you regarding the firmware update required, but I click the "OK" option and then select the Instrument Panel where-upon am I greeted with the same message, choose OK again, and then I am brought to the Instrument Panel where I am able to successfully run the OpenLogger. I do agree though that the pop-up message should not be occurring though. I have reached to @AndrewHolzer to help address this. Thank you for the feedback, JColvin
  16. 1 point
    Hi @Lesiastas As initialization when you application starts, before calling open set the following option to 0/Run: dwf.FDwfParamSet(DwfParamOnClose, c_int(0)) # 0 = run, 1 = stop, 2 = shutdown 2 - open always takes 'long' time (~300ms) since the device is powered down on close and reprogrammed on each opening 1 - device remains powered but the outputs are stopped on close, this takes a few ms on open/close * 0 - device continues the output after close (waveform, pattern generation, supplies), the open/close are fast * *The first open after power up will take 'long' time since the device needs to be programmed.
  17. 1 point
    Hi @P. Fiery The 'replace all' can be undone easily with Ctrl+Z. The 'all files' would require undo in each file, so I have added confirmation for this. Thank you again for your feedback.
  18. 1 point
    D@n

    Verilog

    @Ahmed Alfadhel, Perhaps the most complete tutorial out there is asic-world's tutorial. You might also find it the most vacuous, since although it tells you all the details of the language it doesn't really give you the practice or the tools to move forward from there. There's also a litexsoc (IIRC) by enjoy-digital that I've heard about, but never looked into An alternative might be my own tutorial. Admittedly, it's only a beginner's tutorial. It'll only get you from blinky to a serial port with an attached FIFO. That said, it does go over a lot of FPGA Verilog design practice and principles. It also integrates learning how to use a simulator, in this case Verilator, and a formal verification tool, such as SymbiYosys, into your design process so that you can start learning how to build designs that work the first time they meet hardware. I'm also in the process of working to prepare an intermediate tutorial. For now, if you are interested, you'd need to find most of the information that would be in such a tutorial on my blog. (It's not all there ... yet, although there are articles on how to create AXI peripherals ..) Feel free to check it out. Let me know what you think, Dan
  19. 1 point
    Hi @jfranz-argo, @kharoonian, and @Franky32, I apologize for the delay. I have sent each of you a PM about this. Thanks, JColvin P.S. to other readers, be sure not have Digilent boards attached when you are reprogramming other FTDI devices. A long list of users will tell you it's an easy mistake to accidentally select the wrong device.
  20. 1 point
    Cristian.Fatu

    tera term for two pmods

    Hello, The PmodAD2 communicates over I2C protocol with the main board on which the Pmod is plugged. The PmodAD2 has no UART / USB capabilities. It is the main board that communicates - using its USB-UART capability - with the PC. Connecting the board using a USB cable creates a COM port on the PC. When you open a TeraTerm (or other terminal) connection, you select the COM port. Therefore a possible approach could be to have 2 PmodAD2 connected to a single main board, in different Pmod connectors. The SDK application should gather the AD2 data (measurements), format a text message containing these measurements, and then sending the text message over UART to the PC, to be later visualized in a terminal. What application are you running on the FPGA board ? You should modify it to read the other Pmod as well.
  21. 1 point
    Hi @m72 The preview is further fixed. I hope there are no more issues with this: https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ Here you have the project: EMU_2CH_EACH_V10 (2).dwf3work
  22. 1 point
    You can find newer version 1.0.0.76 in the description of the video: https://www.youtube.com/watch?v=4d3hc-9zBaI
  23. 1 point
    yes, for an application with basic requirements, like receiver gain control this will probably work just fine (it's equivalent to an analog envelope detector). Now it needs a fairly high bandwidth margin between the modulation and the carrier, and that may make it problematic in more sophisticated DSP applications (say "polar" signal processing when I try to reconstruct the signal from the envelope) where the tolerable noise level is orders of magnitude lower.
  24. 1 point
    Hi @dmishins, Welcome to the Digilent Forums! Please attach a screen shot of your Block design. Did you connect the 200 MHz clock to the MIG as instructed in section 10? What did you set the local memory and cache when running clock automation for Microblaze? best regards, Jon
  25. 1 point
    The example I posted would work for Linux or Mac with "common" tools installed. As to Windows... can't really help much there. git's not part of Python, it's used for managing code; you can achieve the same end result here by downloading the ZIP from https://github.com/bdlow/dlog-utils-portable/archive/master.zip and unzipping to a folder. Virtual environment support is a standard part of Python 3; you can skip that if you like but without virtual environments eventually your Python installation will end up like this: https://xkcd.com/1987/ Ah, of course, in Windows `activate` is a batch script not a shell script: https://www.techcoil.com/blog/how-to-create-a-python-3-virtual-environment-in-windows-10/
  26. 1 point
    Hi @Phil_D Try calling to load the workspace and to run script one after the other. subprocess.Popen(['C:/Program Files/Digilent/WaveForms3/WaveForms.exe', 'phase_noise_237.dwf3work']) subprocess.Popen(['C:/Program Files/Digilent/WaveForms3/WaveForms.exe', '-runscript'])
  27. 1 point
    jpeyron

    Nexys 2 - transistor part number

    Hi @CVu, Welcome to the Digilent Forums! Q1 information is below: NTS2101P Single P-Channel Power Mosfet 1.4A, 8VSOT-323 (SC-70) best regards, Jon
  28. 1 point
    Hi @kmesne, We responded to your other question here with some detail, but I will try to elaborate a little bit more here. The Pmod COLOR is not intended to detect colors from any sort of distance, so you would need it next to the red/green light indicator and then have it transmit data to the main controller for the car as opposed to be mounted on the car (unless the red/green indicator was on the car itself). I believe the Pmod COLOR could detect the green in a green cube, but it would need to be fairly well lit up due to the limitations of the sensor itself. As a bit of perspective, this will be a large and non-trivial state machine (especially for first semester project) with a lot of conditions to be covered; is light red or green to control the enable bit on 2+ H-bridge drivers running the motor, which needs to be checked frequently in order to obey traffic laws, as well as the enable bit being toggled as appropriate when changing input directions if the vehicle can go in reverse to avoid burning out the h-bridges, pwm control over the enable pin to allow the vehicle to turn; all done over (presumably) 3 remote systems communicating with each other; the controller with the direction buttons, the color sensor detecting the light change, and the RC vehicle itself. Which system/input will have priority in the state machine and how often will you need to check each input to provide a "smooth driving experience" will all be things that you need to consider. Some good resources for VHDL basics can be found at asic-world.com and fpga4fun.com, as well as this page that discusses state machine construction in VHDL. Thanks, JColvin
  29. 1 point
    kwilber

    Pmod DA3 clocking

    You may not have to build your own. That becomes a design decision that only you can make based on the requirements/specifications your design must meet. If the performance you are getting out of the Digilent IP meets your requirements, there is no reason to roll your own. On the other hand, if you are not able to meet your requirements and you are running up against limitations of the IP, then either look for a more performant IP or consider designing purpose specific logic. According to your measurements, it takes 40 bits sent at a rate of 3.125 Mhz for each update of the DAC. That is at least 12.8 microseconds per update. Take the inverse of that and you have a maximum update rate of 78,125 updates/second. Is that sufficient for your design?
  30. 1 point
    Hi @ebattaglia42, What operating system are you currently on? If you are Windows, can you attach a picture of what is shown in the Windows Device Manager and what you see in the WaveForms Device Manager (it should pop up when you initially connect the EE Board). The other thing I would suggest to try would be to use a different USB cable (make sure it's not just for charging only) and/or USB port on your computer as that is another source of error that is easy to check. Thank you, JColvin
  31. 1 point
    Hi @Amin, I know our content team is planning on updating our Petalinux projects. We currently do not have an ETA for this. Here is the Petalinux Support for Digilent Boards table that shows what Petalinux projects we have for our development boards and has a link to them as well. To use our most recent Petalinux release for the Zybo-Z7-20 I would suggest to download Vivado/SDK and Petalinux 2017.4. I would also suggest reading the Petalinux projects detailed readme as well. thank you, Jon
  32. 1 point
    jpeyron

    Custom Image Processing on Zybo-Z7 20

    Hi @Amin, I have not made a project like this. To get a Zybo-Z7-20 project working with the SD card: Make sure you are using the Digilent board files.Here is the installation tutorial for the board files. Your block design should be the just the Zynq processor with FCLK_CLK0 connected to the M_AXI GP0_ACLK as shown with the attached screen shot. Run block automation as default(board files) when the Digilent board files are being used. Then create a wrapper and generate a bitstream. Next export the hardware including the bitstream and launch SDK. In SDK you should be able to alter the main.c file attache above to work for your needs. If your goal is to use a standalone project i can assist with using the ZYNQ processor with the SD card. I would have to reach out to more experience engineers for assistance using HLS or non-prebuilt SDSoC project. If your project does not need to be standalone then I would suggest using either an embedded linux project like petalinux , a pre-built SDSoC project or the SDSoC reVISION platform. 1) Here is the Petalinux Support for Digilent Boards which has two version releases and a very detailed readme which should help you get the project going. 2) Here is the SDSoC Platforms which has a project completed for the Zybo-Z7-20. 3) Here is the SDSoC reVISION project for the Zybo-Z7-20. thank you, Jon
  33. 1 point
    Hi @Sami Malik, On Monday Ii will make a project and share it on this thread that I believe you are trying to do. thank you, Jon
  34. 1 point
    attila

    external p/s for analog discovery 2

    Szia @GaborG Unfortunately Analog Discovery and Digital Discovery are not working with RaspberryPI.
  35. 1 point
    jpeyron

    Labview with 7-segment display

    Hi @BROLYNE, I have not worked with multisim. I did find Digilent's Programming Digilent FPGA Boards Through Multisim and NI's Getting Started with Digilent Boards in Multisim tutorials that should help with getting the seven segment going. thank you, Jon
  36. 1 point
    Hello @Blake, I've created for you an image that test your FMC-HDMI adapter. It does a basic data transfer between the HDMI output of the ZedBoard and both of the adapter hdmi inputs. Prior to this it also uses all the I2C lines. Please check the .rar attached file. In order to recreate the test, please fallow the fallowing steps: 1.Make sure that you have everything in place, check the bellow instructions and the first image. Connect USB cable from PC to ZED USB PROG port (J17) Connect USB cable from PC to ZED UART port (J14) Connect FMC-HDMI board to FMC connector J1 (of ZED) Connect Power cable to J20 (of ZED) Set mode jumpers for JTAG programming (all to GND) Set J18 (of ZED) jumpers to 3V3 or 2V5. I'v tested both variants. Create a loop between HDMI-OUT J9(ZED) and FMC-HDMI IN1 of the adapter. Turn ZED board on 2. Open Vivado (I used Vivado 2017.4). Open Vivado, and click on Open Hardware Manager within the Welcome Page. After this click on Auto-Connect. You should see the Zed into the upper left panel.Check the image bellow. 3. Add Configuration Memory Device Right click on xc7z020_1 and choose "Add Configuration Memory Device". Check image bellow. 4. Choose the right memory device for ZED. Please choose "s25fl256s-3.3v-qspi-x1-dual_stacked" from the list. Click to program the device. Check images bellow. 5.Program the device with the files attached to this message. For "Configuration file" you choose BOOT.bin. For "Zynq Fsbl" you choose fsbl.elf. Click OK. 6. Wait until it gets programmed. After finish, you click OK. 7. Prepare the board for testing. Open a serial terminal, termite, putty, teraterm etc. Find the COM port and choose 115200 for baud rate. Set jumpers for QSPI programming (MIO5 on 3V3 and SIG, the others on 3V3 and GND). Power OFF the Board. Power ON the Board. The image should boot. See the image bellow. 8.Do the actually test. Make sure that the HDMI-OUT (ZED) is connected to HDMI-IN1 of the FMC-HDMI adapter. Press ENTER. Wait for the test to finalize. Make sure that the HDMI-OUT (ZED) is connected to HDMI-IN2 of the FMC-HDMI adapter. Make sure that your adapter is not loose. Press ENTER. Wait for the test to finalize. 9.Check the results, and give me an update . image.rar
  37. 1 point
    Hi @armin, Sorry for the confusion. I am suggesting that you program your Arty-A7 as you would normally through the usb uart. The program on the Arty-A7 should be a UART controller using pin E15 and E16 on Pmod Port JB for the TX and RX of the project. cheers, Jon
  38. 1 point
    Szia András, 1. The Spectrum Analyzer captures a buffer worth of data before processing it. For 200Hz it needs 400Hz capture of 8192 samples which takes 20 seconds. Reducing the number of samples to 1024 it will take 2.5 seconds. For slow progressive analysis you could use the FFT view in Scope with Scan Shift capture. 2. You can find the transparency option under WaveForms/Settings/Options. Also choosing light analog color might help in transparency. 3. You could do with a script like this eeg.dwf3work const neeg = 4 // sections const ceeg = 100 // history var rghistory = new Array(neeg); // history array for (var i = 0; i < neeg; i++) { // initialize array rghistory[i] = new Array(100); for(var j = 0; j < ceeg; j++) { rghistory[i][j] = 0 } } { // configure plot plot1.X.Units.text = "" plot1.X.Offset.value = -ceeg/2 plot1.X.Range.value = ceeg plot1.Y1.AutoScale.checked = false plot1.Y2.AutoScale.checked = false plot1.Y3.AutoScale.checked = false plot1.Y4.AutoScale.checked = false const vmax = 20 plot1.Y1.Offset.value = -vmax/2 plot1.Y2.Offset.value = -vmax/2 plot1.Y3.Offset.value = -vmax/2 plot1.Y4.Offset.value = -vmax/2 plot1.Y1.Range.value = vmax plot1.Y2.Range.value = vmax plot1.Y3.Range.value = vmax plot1.Y4.Range.value = vmax } Scope1.run() while(wait(0.5)){ // 0.5 second update rate var rgmag = Scope1.Channel1.fftmagnitude var rghz = Scope1.Channel1.fftfrequency var c = rgmag.length var rgeeg = [0,0,0,0] for(var i = 0; i < c; i++){ // calculate section power var hz = rghz[i] if(hz<4) rgeeg[0] += rgmag[i] else if(hz<7.5) rgeeg[1] += rgmag[i] else if(hz<12) rgeeg[2] += rgmag[i] else if(hz<30) rgeeg[3] += rgmag[i] } for(var i = 0; i < neeg; i++){ // shift history arrays rghistory[i].shift() rghistory[i].push(rgeeg[i]) } print(rgeeg[0],rgeeg[1],rgeeg[2],rgeeg[3]) plot1.Y1.data = rghistory[0] // yellow plot1.Y2.data = rghistory[1] // blue plot1.Y3.data = rghistory[2] // red plot1.Y4.data = rghistory[3] // green }
  39. 1 point
    Antonio Fasano

    Arty Z7 DRAM Memory

    Hi, Jon, I made a small software to test how big an array of char can be in SDK and still assign and read correct values on the ARTY-Z7-20 DRAM Memory. I found out that it goes all to way to 500 MB. I did not check further, but that is a hell of a memory capacity !!! Very good !!! Regards, Antonio
  40. 1 point
    Hi, @remalytics It can be definitely done by preparing custom software using Python, LabVIEW, etc...
  41. 1 point
    I should have known that you'd be around as I got this thread started. I'm thrilled to see a reply as I submit the first post. To answer you question; no I haven't but I promise to check out what you've been up to. If this venue fails to show interest I'd be happy to conspire with you to create one that does.
  42. 1 point
    shahbaz

    How to read from SD card on ZYBO

    hi @jpeyron, I followed the guide at GitHub under Readme in PMODSD. can you please guide me step wise on how to start from block design and than going to SDK and running the demo. I have added the pmodsd and zynq PS IPs, after auto connection and running the generate bitstream I get following error. I need your guidance at this
  43. 1 point
    Hi @aerbey, The following development boards should fit the hdmi and i/o needs for your application: the Arty-Z7-20 here with sink and source hdmi , 2 pmod ports and the Arduino/Chipkit header for i/o, the Genesys 2 here with sink and source hdmi ,4 pmod ports and the HPC FMC for i/o and the Nexys Video here with sink and source hdmi, 3 pmod ports and a LPC FMC for i/o. We would not have any suggestions for who to contact about making a custom pcb and housing solutions. thank you, Jon
  44. 1 point
    xc6lx45

    PmodHB5

    I'm sure it's possible to "drive" it at any rate. What I don't know is the amount and color of the magic smoke coming out :-) This is a fairly basic power electronics question: Each switching event dissipates energy because there is voltage across the transistor while current is nonzero. The question is, how much energy dissipation can you tolerate. With a 2A transistor you can probably feel with your finger whether or not it runs hot. In similar applications, PWM frequencies of 15 kHz or more are possible (search for "brushless ESC") but I doubt the motor will run any smoother.
  45. 1 point
    StijnVM

    CMOD A7 Unable to program

    Thank you Jpeyron! I reprogrammed the eeprom with your tool and now Vivado can find the CMOD A7 No idea how it went wrong in the first place however.. If I find something, I will let you know. Thanks everyone!
  46. 1 point
    Hi @Javier Romo, I have added an English translation to your post and moved it to a more appropriate section of the Forum. We have a demo for the Nexys 4 DDR that is available on it's Resource Center, https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start, that uses the seven segment displays available here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-gpio-demo/start. Let me know if you have any questions. Thanks, JColvin
  47. 1 point
    They are very robust. Xilinx is a bit shy in telling numbers, but their posts indicate that they are short circuit proof. https://forums.xilinx.com/t5/Virtex-Family-FPGAs/Effect-of-short-circuit-on-V6-outputs/m-p/227493#M13565 https://www.xilinx.com/support/answers/23277.html I got the impression that reports of failed voltage regulators are more common than busted FPGAs (expect that blowing one pin kills the whole IO bank).
  48. 1 point
    jacobfeder

    Arty Z7 USB

    Thanks!! This did it (firmware files were already present in my host machine's /lib/firmware). I also had to enable wpa-supplicant and wpa-supplicant-cli in the rootfs in order to connect to the wireless network. Thanks again. Cheers, Jacob
  49. 1 point
    jpeyron

    SDSoC - couple of questions

    Hi @theUltimateSource, Download the reVISION-Zybo-Z7-20-2017.4-2.zip from here. Once you have unzipped the folder the live io can be found in the samples folder(zybo_z7_20\samples). thank you, Jon