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  1. 2 points
    Hi @attila Thank you again for all the support you've provided me for the past weeks. I am now capable of receiving more than 409 characters using the Wrapper I created base from your example. It uses the Record acquisition mode and I set the buffer size to 3 million for now. I'll increase it when the need arises. I used 1 UART controller and branched out its Tx pin to 2 DIO pins of the AD2 (DIO #0 & 1). I transmitted 500 characters: (If Record mode is not the acquisition mode, the received result will be blank) For DIO # 0, it received: with a length of: For DIO #1, it received: with a length of: I could not have done it without your guidance, thank you again and more power to you and Digilent Best regards, Lesiastas
  2. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  3. 2 points
    kwilber

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  4. 2 points
    Hi @neocsc, Here is a verified Nexys Video HDMI project updated from Vivado 2016.4 to Vivado 2017.4. You should be able to find the updated project in the proj folder . Here is a GitHub project done in HDL using the clocking wizard, DVI2RGB and RGB2DVI IP Cores for another FPGA. Here is a unverified Nexys Video Vivado 2017.4 HDMI pass through project made from the linked Github project. In the next few days I should have the bandwidth to verify this project. thank you, Jon
  5. 2 points
    The warning you pasted is benign and simply means there are no ILAs present in your design. The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design. Finally, @elodg gives some great troubleshooting information in this thread.
  6. 2 points
    Hi @akhilahmed, In the mentioned video tutorial, the leds are controlled using "xgpio.h" library but the application is standalone. If you want to use a linux based application you have to use linux drivers for controlling. In the current Petalinux build, which is used in SDSoC platform, UIO driver is the best approach. Steps: 1. Vivado project generation: - Extract .dsa archive from /path_to_sdsoc_platform/zybo_z7_20/hw/zybo_z7_20.dsa - Launch Vivado - In Tcl Console: cd /path_to_extracted_dsa/prj - In Tcl Console: source rebuild.tcl - In this point you should have the vivado project which is the hardware component of SDSoC platform. Open Block Design. Change to Address Editor Tab. Here you will find the address for axi_gpio_led IP: 0x4122_0000 2. Petalinux UIO driver: - Launch SDx - Import zybo-z7-20 SDSoC platform - Create a new SDx linux based project using a sample application (e.g. array_zero_copy) - Build the project - Copy the files from /Dubug/sd_card to SD card - Plug the SD card in Zybo Z7. Make sure that the JP5 is set in SD position. Turn on the baord - Use your favorite serial terminal to interact with the board (115200, 8 data bits, 2 stop bits, none parity) - cd to /sys/class/uio - if you run ls you will get something like: uio0 uio1 uio2 uio3 uio4 uio5 - Now you have to iterate through all these directories and to search for the above mentioned axi_gpio_led address: 0x4122_0000 - For example: cat uio0/maps/map0/addr will output: 0x41220000, which means that the axi_gpio_led can be accessed using linux uio driver through uio0 device. - Code: #include <stdio.h> #include <stdlib.h> #include <sys/ioctl.h> #include <sys/mman.h> #include <stdint.h> #include <unistd.h> #include <fcntl.h> #define UIO_MEM_SIZE 65536 #define UIO_LED_PATH "/dev/uio0" void UioWrite32(uint8_t *uioMem, unsigned int offset, uint32_t data) { *((uint32_t*) (uioMem+offset)) = data; } uint32_t UioRead32(uint8_t *uioMem, unsigned int offset) { return *((uint32_t*) (uioMem+offset)); } void led_count_down(uint8_t *ledMem) { uint8_t count = 0xF; uint8_t index = 0; for (index = 0; index < 5; index++) { UioWrite32(ledMem, 0, count); count = count >> 1; sleep(1); } } int main() { // Set Leds as output int led_fd = open(UIO_LED_PATH, O_RDWR); uint8_t *ledMem = (uint8_t *) mmap( 0, UIO_MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, led_fd, (off_t)0); UioWrite32(ledMem, 4, 0x0); // Set all leds as output while(1) { // Start led count-down led_count_down(ledMem); } return 0; } - Build the project and copy the content of Debug/sd_card on SD sd_card - Power on the board and connect to it using a serial terminal - run the following commands: mount mmcblk0p1 /mnt cd /mnt ./project_name.elf - Result: A countdown should be displayed on leds.
  7. 2 points
    JColvin

    Arty A7 flash chip

    Hi @D@n, I believe the new part that is used in the Arty A7 boards (and other A7 boards) is now a Spansion S25FL128SAGMF100; based on old schematics, I believe this was added in Rev D of the Arty A7 (dated August 2017), though I do not know when that particular Rev was then released (or if it even was released) to the public. I confirmed that the Arty S7 also uses this part and I wouldn't be surprised if most of our other Artix 7 based boards use it now as well. I've requested that the chip name and images are updated in any appropriate tutorials and requested that the pdf version of the reference manual (updated wiki) is updated as well. Thanks, JColvin
  8. 2 points
    attila

    Math on FFT traces

    Hi @lab!fyi In the Network Analyzer extended option lets you use Wavegen channels at up to 20MHz and with external up to 50MHz. In the Spectrum Analyzer you can select frequency range up to 10MHz but with auto option lets you set Stop frequency up to 50MHz. Selecting the dB unit will let you specify custom reference, for dBm I think it should be 0.316V
  9. 2 points
    @hamster I was able to run your AXI Slave interface. It works great! It is now very easy to exchange information between PS and PL, and it even supports execute-in-place (e.g. I can put ARM instructions to register file and run PS CPU directly from it). I have some questions about your AXI Slave design: 1) AXI_a*size has no effect on INCR type of burst transactions, but according to AXI protocol: the increment value depends on the size of the transfer. You set it only for WRAP type, is it correct? Thus, burst size is always 0 for INCR type? 2) Do you know how PS initiates INCR burst type? A kind of memset/memcpy need to be used for that or an incrementing pointer will also work? 3) Where WRAP type is necessary? How to use PS to work in WRAP mode? You may also update your wiki page with following: 0) Create provided VHDL files 1) Create a block-diagram and add PS IP core to it 2) Apply configuration provided by your board's pre-settings; this will set all necessary initialization settings for PS (e.g. clock frequencies, DDR bindings, etc.) 3) Press auto-configure (or how it's called) ==> this will connect PS IP to DDR and to fixed IO 4) Add "External ports" to the diagram (create new AXI_CLK and AXI external ports) and connect them to PS ports 5) Generate VHDL wrapping code for this block diagram 6) Put generated system under axi_test_top by renaming it to axi_test_wrapper (default name is design_#_wrapper in my Vivado version) 7) This will auto-connect block-diagram external ports with axi_test_top 8 ) Add constrains file and rename/uncomment external ports where necessary 9) Generate bitstream 10) File->Export->Hardware and create .hwf file which contains PS configuration 11) Open Xilinx SDK and create a new project: select .hwf file as Hardware BSP for this project 12) Now, Xilinx SDK will auto-generate few .c and .h files which contain necessary PS initialization ==> clocks, IRQs, DDR, etc. 13) Add hello_world.c application to the project @hamster Thank you very much. I've learned a bunch of new things thanks to your help!
  10. 2 points
    mohammadhgh

    Zybo z7-20 Zynq Presets

    Hi @Mahesh, As @jpeyron said in the post marked as accepted solution, the Zynq processing system will be configured with the board presets when you first add the Zynq processing system IP core to the block design and run the block automation task from the green message that appears! Just remember to keep the Apply Board Preset option checked as shown in he picture. So this means if you are using the pre-built block design from the example project, a possible solution can be to remove the existing Zynq processing system block and adding a new one!
  11. 2 points
    attila

    Analog Discovery 2 vs Raspberry Pi 3

    FTDI USBs like AD, AD2, DD are not working with RPI model B (1,2,3) data packets/bytes are randomly lost. The EExplorer with different USB controller is working fine on these. All devices are working with other embeddeds: Zed, Zybo, BeagleBone… According reports AD is working with the original RPI model A and probably Zero because it has similar chipset/USB. The problem seems to be with FTDI or RPI B USB, library or hardware. You can find such comments regarding RPI problems with other devices too. Unfortunately we couldn't remediate this problem.
  12. 1 point
    Hey Paolo, I'm glad you found my videos helpful! I've been working on other projects, but if you have any other ideas for videos that you would find helpful let me know. Kaitlyn
  13. 1 point
    You can start with the following tutorials: http://www.ni.com/tutorial/14871/en/ https://reference.digilentinc.com/learn/programmable-logic/tutorials/program_fpgas_through_multisim/start
  14. 1 point
    Hi @cfatt7 Yes, you can use the FDwfAnalogOutConfigure(..., -1, ...) to start channels synchronized. You can also use the FDwfAnalogOutMasterSet to specify the master channel, then starting master channel will also start the slave channels. This is important in case you are using external triggering or cross-triggering with other instruments. Specifying a finite run length is useful to keep different frequencies phase aligned, using the minimum frequency or greatest common divisor. Like 1kHz might be generate as 0.9999999kHz and 2kHz as 2.000000001kHz, which could shift slowly over time. In this case use 1ms (1/1kHz) run time. FDwfAnalogOutRunSet(..., ..., 1.0/min_freq); FDwfAnalogOutRepeatSet(..., ..., 0); See the WF SDK/ samples/ py/ AnalogOut_Sync.py examples
  15. 1 point
    zygot

    Using tera term for two pmods

    Well I think that this is better stated as saying that most serial terminal applications can only connect to one COM port at a time. It is possible to mave multiple UARTs in your FPGA design and connect to multiple serial terminal applications. I like Putty myself, but there are other options. Another possibility is to look around in the Digilent Project Vault and see at least 3 project with source code that might accomplish what you want to do. If you instantiate your own UART you can access any number of internal registers or memory.
  16. 1 point
    Hi @Lesiastas You should use higher sample rate to capture raw data than the UART rate. Otherwise due to clock jitter and signal slew rate the capture could be wrong. Imagine on sample could be captured exactly on bit start and next bit on the end of the same bit, instead of next bit start... Anyway, here I have modified the decodeUart to work with sample rate = uart rate, see the lines marked with ' ' ' ' Module Module1 Function decodeUart(ByRef rgData() As UShort, ByVal cSamplePerBit As Integer, ByVal pin As Integer) As List(Of Byte) Dim pData As Boolean Dim fData As Boolean = False Dim cSamples = rgData.Length Dim rgUart As New List(Of Byte) For i As Integer = 0 To cSamples - 1 Dim s = rgData(i) pData = fData fData = 1 And (s >> pin) If pData <> 0 And fData = 0 Then Dim bValue As Integer = 0 For b = 0 To 7 Dim ii = Math.Round(i + (1.499 + b) * cSamplePerBit) ''''' If ii >= cSamples Then Exit For End If s = rgData(ii) fData = 1 And (s >> pin) If fData Then bValue += (1 << b) End If Next rgUart.Add(bValue) i += cSamplePerBit * 9.499 - 1 ''''' 1 start + 8 bits + 0.5 stop -1 because For will increment End If Next Return rgUart End Function Sub Main() Dim hdwf As Long If FDwfDeviceOpen(-1, hdwf) = False Then Dim szError As String FDwfGetLastErrorMsg(szError) System.Console.WriteLine("Device open failed" & vbCrLf & szError, vbExclamation + vbOKOnly) End End If Const hzUart = 9600 Const hzRate = hzUart * 3 ''''' Const cSamples = 1000 Dim hzDI As Double FDwfDigitalInInternalClockInfo(hdwf, hzDI) FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDetectorDigitalIn) FDwfDigitalInTriggerSet(hdwf, 0, 0, 0, &HFFFF) 'any falling edge 'FDwfDigitalInTriggerAutoTimeoutSet(hdwf, 10.0) FDwfDigitalInDividerSet(hdwf, hzDI / hzRate) FDwfDigitalInSampleFormatSet(hdwf, 16) FDwfDigitalInBufferSizeSet(hdwf, cSamples) FDwfDigitalInTriggerPositionSet(hdwf, cSamples - 10) FDwfDigitalInConfigure(hdwf, 1, 1) Dim sts As Byte While True If FDwfDigitalInStatus(hdwf, 1, sts) = 0 Then Return End If If sts = DwfStateDone Then Exit While End If End While FDwfDigitalInDividerGet(hdwf, hzRate) ' get the actual rate Const cSamplePerBit = hzRate / hzUart Dim rgData(cSamples) As UInt16 FDwfDigitalInStatusDataUShort(hdwf, rgData, 2 * rgData.Length) Call FDwfDeviceCloseAll() Dim rg0 = decodeUart(rgData, cSamplePerBit, 0) System.Console.Write("Hex 0: ") For i = 0 To rg0.Count - 1 System.Console.Write(" 0x" + Conversion.Hex(rg0(i))) Next System.Console.WriteLine() System.Console.WriteLine("Text 0: " + System.Text.Encoding.ASCII.GetString(rg0.ToArray)) End Sub End Module
  17. 1 point
    Cristian.Fatu

    tera term for two pmods

    Hello, The PmodAD2 communicates over I2C protocol with the main board on which the Pmod is plugged. The PmodAD2 has no UART / USB capabilities. It is the main board that communicates - using its USB-UART capability - with the PC. Connecting the board using a USB cable creates a COM port on the PC. When you open a TeraTerm (or other terminal) connection, you select the COM port. Therefore a possible approach could be to have 2 PmodAD2 connected to a single main board, in different Pmod connectors. The SDK application should gather the AD2 data (measurements), format a text message containing these measurements, and then sending the text message over UART to the PC, to be later visualized in a terminal. What application are you running on the FPGA board ? You should modify it to read the other Pmod as well.
  18. 1 point
    Hi @m72 The pulse preview is not correct. I will look into this. Thank you for the observations. You could use a custom bus or signals to easily create/modify such patterns.
  19. 1 point
    jpeyron

    GPS Pmod

    Hi @cepwin, I'm glad you we able to get to the bottom of the issue. Thank you for sharing what happened. cheers, Jon
  20. 1 point
    Hi, I just have opened a new terminal and launch minicom through the new terminal which works the same way as SDK terminal but I have to close the SDK terminal before connecting to minicom. Thanks @D@n and @jpeyron
  21. 1 point
    Hi, For sw part I use Xilinx DMA driver (interface to VDMA IP core) and modified ADI AXI HDMI DRM driver for exposing frame buffer device to GUI sw (e.g. Qt). You can see driver bindings in above attached zyboz7-20.devicetree-1.zip (pl.dtsi). All video memory transfers to FPGA are managed by this two drivers.
  22. 1 point
    Hi @ahmedengr.bilal, Like I mentioned in the previous post there is no HDMI output from the Linux side, neither the embedded rootFS provided by petalinux nor the kernel configuration we give out is set to accommodate this feature. Regarding the missing media-ctl and v4l2-ctl, you have not activated the v4l-utils in the rootfs configuration of the petalinux. to do this you need to navigate to your petalinux project folder and run: petalinux-config -c rootfs Once the menu appears you need to go to Filesystem Packages->misc->v4l-utils and activate: v4l-utils, libv4l, media-ctl. Rebuild the whole project and it should be working now. -Ciprian
  23. 1 point
    Yep, seen that they were back online. Thanks, Jon
  24. 1 point
    jomoengineer

    Howdy from NorCal

    Thanks Jon. And thanks for the links. Cheers, Jon
  25. 1 point
    @longboard, Yeah, that's really confusing isn't it? At issue is the fact that many of these chips are specified in Mega BITS not BYTES. So the 1Gib is mean to refer to a one gigabit memory, which is also a 128 megabyte memory. That's what the parentheses are trying to tell you. Where this becomes a real problem is that I've always learned that a MiB is a reference to a million bytes, 10^6 bytes, rather than a mega byte, or 2^20 bytes. The proper acronyms, IMHO, should be Gb, GB, Mb, and MB rather than GiB or MiB which are entirely misleading. As for the memory, listed as 16 Meg x 8 x 8, that's a reference to 8-banks of 16-mega words or memory, where each word is 8-bits wide. In other words, the memory has 16MB*8 or 128MB of storage. You could alternatively say it had 1Gb of memory, which would be the same thing, but this is often confused with 1GB of memory--hence the desire for the parentheses again. Dan
  26. 1 point
    Hi @Phil_D The gain switch is adjusted automatically based on the selected scope range. At 500mV/div (5Vpk2pk ~0.3mV resolution) or lower the high gain is used with and above this the low gain (50Vpk2pk w ~3mV resolution). In case you specify trigger level out of the screen (5Vpk2pk) or offset higher/lower than +/- 2.5V the low gain will be used for the trigger source channel. This will be noted on the screen with red warning text. The attenuation is a different thing. This option lets you specify the external attenuation or amplification on the signals which enter the scope inputs and the data is scaled accordingly. Like, if you use a 10x scope probe, the scope input will actually get 1/10th of the original signal, but specifying 10x attenuation the signal is scaled to show values on the probe. In this case the 500mV/div (5Vpk2pk) low/high gain limit moves up to 5V/div (50Vpk2pk) and the low gain up to 50V/div If you have an external 100x amplifier on the scope input you can specify 0.01x attenuation. With this you will have 5mV/div (50mVpk2pk ~0.003mV resolution) for high gain.
  27. 1 point
    HI xc6lx45: Well, to my surprise, when I got home and loaded the .BIT file onto the board...it works perfectly. [1:0]sw is changing the frequency the the led is blinking at properly. So this tells me that I don't quite have my testbed code done properly. I tried to attach it into this text but it kept getting reformatted so I've simply attached the actual file. If somebody could look at it and tell me what (if anything) I've done wrong I'd greatly appreciate it. THANKS! NOTE: In the actual module code, above, I had changed the CASE choices to the 0, 1st, 2nd and 3rd flip-flops in order to better see the led changing value on the wave panel. However I've changed the code back to the actual flip-flops I wanted; the 26th, 25th, 24th and 23rd flip-flops. As I said...the board is working perfectly now and the switch setting are appropriately changing the led blinking frequency. It HAS to be something wrong with the TestBench code...or me not using the simulator properly. THANKS MUCH! clock_divider.tb
  28. 1 point
    Hi @Jaraqui Peixe, Unfortunately, Digilent does not have the ability to obtain these licenses for you with regards to Xilinx negotiations. I do not doubt that the Spartan 3E Starter Boards you have are as good as new and work as such, but the reality is that last variant of ISE 14.7 that could support the FPGA chips on the Basys 2 and the Spartan 3E (both over 10 years old), was released by Xilinx back in 2013, so active support on these boards is limited as the required software will not install on newer OS's (at least the Windows variants anyway). As @xc6lx45, it is possible to make it work though. What I would probably recommend is looking into the newer 7 series boards, such as the Basys 3 (the most similar to the Basys 2) or if you would want access to more memory than is provided in BRAM, both the Arty A7 and the Nexys A7 have on-board DDR memory. All of these boards work with Microblaze and are supported by the free Vivado WebPACK from Xilinx (which is license-free if that is a factor for you and includes Microblaze). Naturally, there is no guarantee that the Vivado software that supports these Artix 7 FPGA chips will become end-of-life'd, but I can at least say from Digilent's end that I have not heard of this happening in the near future. Thanks, JColvin
  29. 1 point
    You might have a look at Trenz Electronics "Zynqberry". I think they managed to get one of the cameras to work (not sure). What I do remember is that the board has some custom resistor circuitry to additional pins for the required low-speed signaling.
  30. 1 point
    jpeyron

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, In section 2 Interfacing with the Pmod on page 1 of the reference manual for the Pmod DA3 here it states the pmod should use spi mode 0. thank you, Jon
  31. 1 point
    Hi @hello.parth, The Ethernet IP cores use the AXI BUS. You would need to implement the AXI BUS communication to interact with the Ethernet IP Cores. This is not an easy task. You do not need to use Microblaze or the Ethernet IP Cores to use the ethernet on the Nexys Video. Here is a community members( @hamster) VHDL GigabitTX project using the Nexys Video. thank you, Jon
  32. 1 point
    Well that's a pretty horrible looking 5 MHz signal coming directly out of an MMCM. It does remind me of the characteristic response of a particular passive component to a pulse, from decades ago when I took my intro electronics course. What do you think? Remind you of anything? I didn't mention the idea of scope probe compensation. It sure doesn't look like something that even a cheapo compensated probe would present for a low frequency signal out of a functioning FPGA pin into a high impedance load. Past that there are a number of usual suspects... but something is fundamentally wrong with your test setup.
  33. 1 point
    xc6lx45

    FFT / iFFT / RS - Basys3

    OK that starts to make more sense. So one channel is reference signal e.g. transmitted signal, one channel the received reflection. Capture both, FFT, multiply (don't forget the conjugate), iFFT. On the bright side, in this specific case you can solve the circularity issues mentioned above with sufficient zero padding on the transmit signal (rule of thumb: Add enough zeros until all reflections have died down to negligible level). This may be easier said than done with a hardware FFT, though... Resolution is limited to the sample rate. If you want to do better, you can interpolate by stealing lines 315..345 here . Needless to say, this calculation needs to be done on a microcontroller or the like. In double precision it's usually accurate to 1 % of a sample. For a reference algorithm, have a look here (this is more complex and somewhat heuristic but has proven itself over the years). With noise-free data this can be accurate to about one nanosample.
  34. 1 point
    Hi @jli853, I reached out to one of our design engineers about this forum thread. They responded that "Unless you do a non-blocking (overlapped) transfer the time it takes to execute the function will include not only the time to transfer the data over USB but also to shift it onto the JTAG scan chain. When the function returns all data has been transferred to the target JTAG device. How long that takes is going to very with the TCK frequency, as well as the PC side hardware and operating system. I don’t have any measured data to provide." thank you, Jon
  35. 1 point
    jpeyron

    Zedboard WiFi usage

    Hi @harika, Glad to hear you were able to get the bitstream to generate. cheers, Jon
  36. 1 point
    jpeyron

    Zedboard DMA Audio Demo problem

    Hi @Brinda, You want to download the release version of Zedboard DMA project here. I was able to generate a bitstream without issues in vivado 2016.4. Unfortunately, Vivado projects are version specific. This project was made in and works with Vivado 2016.4 without having to make alterations to the project. What version of Vivado are you using? cheers, Jon
  37. 1 point
    Hi! Check page 45 in https://www.xilinx.com/support/documentation/boards_and_kits/zc706/ug954-zc706-eval-board-xc7z045-ap-soc.pdf It stated: N8 MGTREFCLK0P_112 PCIE_CLK_QO_P A13 (1) N7 MGTREFCLK0N_112 PCIE_CLK_QO_N A14 (1) So just create clock input pins in your block diagram with any names. After that define constraints in xdc file which connects your clk names to N7/N8 pins.
  38. 1 point
    Hi @armin, Sorry for the confusion. I am suggesting that you program your Arty-A7 as you would normally through the usb uart. The program on the Arty-A7 should be a UART controller using pin E15 and E16 on Pmod Port JB for the TX and RX of the project. cheers, Jon
  39. 1 point
    attila

    Frequency profile generation with script

    Szia @Andras The Network Analyzer by default takes controls over the Wavegen channel 1 and configures the required frequency for each step. You could select NA/Wavegen/Channel/External but to be able the control the Wavegen manually, but in this case the previous Script solution won't work. The Insert/Local lists specific variables and is available in other scriptable places, like scope custom math, measurements, logging, network analyzer custom plots In each script editor including the Script tool you can use the Ctrl+Space to list available objects, variables... or child objects, properties, functions..
  40. 1 point
    Antonio Fasano

    Arty Z7 DRAM Memory

    Hi, Jon, I made a small software to test how big an array of char can be in SDK and still assign and read correct values on the ARTY-Z7-20 DRAM Memory. I found out that it goes all to way to 500 MB. I did not check further, but that is a hell of a memory capacity !!! Very good !!! Regards, Antonio
  41. 1 point
    Hi @Ictinike, Have you resolved your issue, or found anything new? You mentioned this issue began when you updated the firmware; have you tried rolling back to a previous version and seeing if things work properly? If you are still having issues, I can help you troubleshoot and find the real issue at cause here. Regards, AndrewHolzer
  42. 1 point
    shahbaz

    How to read from SD card on ZYBO

    hi @jpeyron, I followed the guide at GitHub under Readme in PMODSD. can you please guide me step wise on how to start from block design and than going to SDK and running the demo. I have added the pmodsd and zynq PS IPs, after auto connection and running the generate bitstream I get following error. I need your guidance at this
  43. 1 point
    Darryl Ring

    Arty7 xemacp undeclared

    This appears to be a known issue in 2018.2: https://www.xilinx.com/support/answers/71330.html. It appears that support for the emaclite driver got missed in a change (https://github.com/Xilinx/embeddedsw/commit/16c05f56fcb860513d34b83a1a301fa185e06316). Their patch can't actually be applied to Xilinx/SDK/2018.2/data/embeddedsw, but the changes are small and easy to make. I've attached the file here. It should replace ThirdParty/sw_services/lwip202_v1_1/src/contrib/ports/xilinx/netif/xadapter.c. Then you can regenerate the BSP sources and it will compile. xadapter.c
  44. 1 point
    @sbobrowicz, Thanks for your help. Unfortunately, your link doesn't work; do you instead mean https://github.com/Digilent/Arty-Z7-20-base-linux? When I initially posted, I didn't follow mentioned points 3 and 4 (and 5, but thats seem to be optional) . After searching a bit through other posts, changing device tree file remains somehow "black magic". So I didn't touch it for the moment. Is there addional information somewhere on the meaning of these entries?
  45. 1 point
    attila

    Digital Discovery SPI interface

    Hi @Sung The WaveForms application can be used in demo mode to explore the features. In demo mode the protocol signals are not generated properly but you can see the options a real device would provide. 1. You can use the Logic Analyzer to capture and decode communication. This is mostly useful for debugging protocol like for timing, glitches... 2. You can use the Protocol interface to send or to capture data and save in text file. You can also use JS code to automate communication in Custom tab or Script interface. 3. You can use the WaveForms SDK to create custom application/script.
  46. 1 point
    @Adriann, As I recall the minimum source/sink current for the Spartan 3 is 12ma ( it might be 6 ma ). But it it up to you to get the datasheet, look in the DC characteristics and verify this. Always take this advice even if someone offers and answer. As to how much current you can safely drive on multiple outputs the answer is more complicated. It depends on a lot of things like which bank they are on, how many IOs are switching simultaneously, how well the FPGA is connected to a thermal sink, etc. Again, whether or not you want to set the IO to maximum current requires some knowledge of the specification for your part and analysis.
  47. 1 point
    @rpickeri Thanks for posting your solution. Did you get the prebuilt image working too? I will investigate the problem further if not.
  48. 1 point
    OK thanks. Yes, updating that tutorial would save a lot of time and confusion. I later noticed that Xilinx's page for 2017.2 has a bit more description relating to free WebPACK than the page for 2017.3, though it's still not clear how to invoke the free aspect. Further confusion is added by the Xilinx page you arrive at from Vivado's License Manager, as that page omits the Activation-based licenses, and the licenses it does show include a Free one for pre-2015, as though you can't license 2016 and later for free. Evidently that doesn't mean you can't use 2016 and later, it means that no license is required, and you don't need to be using the License Manager at all!
  49. 1 point
    hamster

    MMCM dynamic clocking

    I feel a bit bad about posting a minor novel here, but here is an example of going from "5 cycles on, 5 off" (i.e. divide by 10) to "10 on, 10 off" (device by 20). The VCO is initially to 800 MHz with CLK0 being VCO divide by 8.... so after config you get 100MHz. Push the button and you get 800/20 = 40MHz, release the button and you get 80MHz. It is all really hairy in practice! EDIT: Through experimentation I just found that you don't need to reset the MMCM if you are not changing the VCO frequency. So the 'rst' signal in the code below isn't needed (and LOCKED will stay asserted). -------------------------------------------------------------------------------------------------------- -- Playing with the MMCM DRP ports. -- see https://www.xilinx.com/support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf -- for the Dynamic Reconviguration Port addresses -------------------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity mmcm_reset is Port ( clk_100 : in STD_LOGIC; btn_raw : in STD_LOGIC; led : out STD_LOGIC_VECTOR (15 downto 0)); end mmcm_reset; architecture Behavioral of mmcm_reset is signal btn_meta : std_logic := '0'; signal btn : std_logic := '0'; signal speed_select : std_logic := '0'; signal counter : unsigned(26 downto 0) := (others => '0'); signal debounce : unsigned(15 downto 0) := (others => '0'); signal clk_switched : std_logic := '0'; signal clk_fb : std_logic := '0'; type t_state is (state_idle_fast, state_go_slow_1, state_go_slow_2, state_go_slow_3, state_idle_slow, state_go_fast_1, state_go_fast_2, state_go_fast_3); signal state : t_state := state_idle_fast; ----------------------------------------------------------------------------- --- This is the CLKOUT0 ClkReg1 address - the only register to be played with ----------------------------------------------------------------------------- signal daddr : std_logic_vector(6 downto 0) := "0001000"; signal do : std_logic_vector(15 downto 0) := (others => '0'); signal drdy : std_logic := '0'; signal den : std_logic := '0'; signal di : std_logic_vector(15 downto 0) := (others => '0'); signal dwe : std_logic := '0'; signal rst : std_logic := '0'; begin MMCME2_ADV_inst : MMCME2_ADV generic map ( BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW) CLKFBOUT_MULT_F => 8.0, -- Multiply value for all CLKOUT (2.000-64.000). CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000). -- CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). CLKIN1_PERIOD => 10.0, CLKIN2_PERIOD => 0.0, -- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128) CLKOUT1_DIVIDE => 1, CLKOUT2_DIVIDE => 1, CLKOUT3_DIVIDE => 1, CLKOUT4_DIVIDE => 1, CLKOUT5_DIVIDE => 1, CLKOUT6_DIVIDE => 1, CLKOUT0_DIVIDE_F => 8.0, -- Divide amount for CLKOUT0 (1.000-128.000). -- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.01-0.99). CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT2_DUTY_CYCLE => 0.5, CLKOUT3_DUTY_CYCLE => 0.5, CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5, CLKOUT6_DUTY_CYCLE => 0.5, -- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000). CLKOUT0_PHASE => 0.0, CLKOUT1_PHASE => 0.0, CLKOUT2_PHASE => 0.0, CLKOUT3_PHASE => 0.0, CLKOUT4_PHASE => 0.0, CLKOUT5_PHASE => 0.0, CLKOUT6_PHASE => 0.0, CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE) COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL DIVCLK_DIVIDE => 1, -- Master division value (1-106) -- REF_JITTER: Reference input jitter in UI (0.000-0.999). REF_JITTER1 => 0.0, REF_JITTER2 => 0.0, STARTUP_WAIT => FALSE, -- Delays DONE until MMCM is locked (FALSE, TRUE) -- Spread Spectrum: Spread Spectrum Attributes SS_EN => "FALSE", -- Enables spread spectrum (FALSE, TRUE) SS_MODE => "CENTER_HIGH", -- CENTER_HIGH, CENTER_LOW, DOWN_HIGH, DOWN_LOW SS_MOD_PERIOD => 10000, -- Spread spectrum modulation period (ns) (VALUES) -- USE_FINE_PS: Fine phase shift enable (TRUE/FALSE) CLKFBOUT_USE_FINE_PS => FALSE, CLKOUT0_USE_FINE_PS => FALSE, CLKOUT1_USE_FINE_PS => FALSE, CLKOUT2_USE_FINE_PS => FALSE, CLKOUT3_USE_FINE_PS => FALSE, CLKOUT4_USE_FINE_PS => FALSE, CLKOUT5_USE_FINE_PS => FALSE, CLKOUT6_USE_FINE_PS => FALSE ) port map ( -- Clock Outputs: 1-bit (each) output: User configurable clock outputs CLKOUT0 => clk_switched, CLKOUT0B => open, CLKOUT1 => open, CLKOUT1B => open, CLKOUT2 => open, CLKOUT2B => open, CLKOUT3 => open, CLKOUT3B => open, CLKOUT4 => open, CLKOUT5 => open, CLKOUT6 => open, -- Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs PSDONE => open, -- Feedback Clocks: 1-bit (each) output: Clock feedback ports CLKFBOUT => clk_fb, CLKFBOUTB => open, -- Status Ports: 1-bit (each) output: MMCM status ports CLKFBSTOPPED => open, CLKINSTOPPED => open, LOCKED => open, -- Clock Inputs: 1-bit (each) input: Clock inputs CLKIN1 => clk_100, CLKIN2 => '0', -- Control Ports: 1-bit (each) input: MMCM control ports CLKINSEL => '1', PWRDWN => '0', -- 1-bit input: Power-down RST => rst, -- 1-bit input: Reset -- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports DCLK => clk_100, -- 1-bit input: DRP clock DO => DO, -- 16-bit output: DRP data DRDY => DRDY, -- 1-bit output: DRP ready -- DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports DADDR => DADDR, -- 7-bit input: DRP address DEN => DEN, -- 1-bit input: DRP enable DI => DI, -- 16-bit input: DRP data DWE => DWE, -- 1-bit input: DRP write enable -- Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs PSCLK => '0', PSEN => '0', PSINCDEC => '0', -- Feedback Clocks: 1-bit (each) input: Clock feedback ports CLKFBIN => clk_fb ); speed_change_fsm: process(clk_100) begin if rising_edge(clk_100) then di <= (others => '0'); dwe <= '0'; den <= '0'; case state is when state_idle_fast => if speed_select = '1'then state <= state_go_slow_1; -- High 10 Low 10 di <= "0001" & "001010" & "001010"; dwe <= '1'; den <= '1'; end if; when state_go_slow_1 => if drdy = '1' then state <= state_go_slow_2; end if; when state_go_slow_2 => rst <= '1'; state <= state_go_slow_3; when state_go_slow_3 => rst <= '0'; state <= state_idle_slow; when state_idle_slow => di <= (others => '0'); if speed_select = '0' and drdy = '0' then state <= state_go_fast_1; -- High 5 Low 5 di <= "0001" & "000101" & "000101"; dwe <= '1'; den <= '1'; end if; when state_go_fast_1 => if drdy = '1' then state <= state_go_fast_2; end if; when state_go_fast_2 => rst <= '1'; state <= state_go_fast_3; when state_go_fast_3 => rst <= '0'; state <= state_idle_fast; end case; end if; end process; dbounce_proc: process(clk_100) begin if rising_edge(clk_100) then if speed_select = btn then debounce <= (others => '0'); elsif debounce(debounce'high) = '1' then speed_select <= not speed_select; else debounce <= debounce + 1; end if; -- Syncronise the button btn <= btn_meta; btn_meta <= btn_raw; end if; end process; show_speed_proc: process(clk_switched) begin if rising_edge(clk_switched) then counter <= counter + 1; led(7 downto 0) <= std_logic_vector(counter(counter'high downto counter'high-7)); end if; end process; led(15) <= speed_select; end Behavioral;
  50. 1 point
    lukeswr

    Adept library to use in visual .net c#

    I have an excellent example of interfacing with non-managed libraries using an internal sealed class. I have attached the file. I copied this foot print from another interface class regarding a USB interface. This example is nowhere near complete, but it provides the building block. using System; using System.IO; using System.Runtime.InteropServices; namespace Linear.common.lap.Digilent.Adept2 { /// <summary> /// This class library provides the 64-bit interface to the Digilent Inc. Adept2 dmgr library. /// </summary> internal sealed class StaticDmgr : IDisposable { // ReSharper disable InconsistentNaming /// <summary> /// The following value is passed to DmgrGetTransResult to specify /// wait until the transfer completes. /// </summary> public const UInt32 tmsWaitInfinite = 0xFFFFFFFF; // Handle to our DLL - used with GetProcAddress to load all of our functions private IntPtr hDMGR = IntPtr.Zero; // Declare pointers to each of the functions we are going to use in DMGR.DLL // These are assigned in our constructor and freed in our destructor. private readonly IntPtr pDmgrGetVersion = IntPtr.Zero; private readonly IntPtr pDmgrEnumDevices = IntPtr.Zero; private readonly IntPtr pDmgrGetDvc = IntPtr.Zero; private readonly IntPtr pDmgrIsEnumFinished = IntPtr.Zero; private readonly IntPtr pDmgrStopEnum = IntPtr.Zero; private readonly IntPtr pDmgrFreeDvcEnum = IntPtr.Zero; internal StaticDmgr() { // If DMGR.DLL is NOT loaded already, load it if (hDMGR == IntPtr.Zero) { // Load our DEPP.DLL library hDMGR = LoadLibrary(@"DMGR.DLL"); if (hDMGR == IntPtr.Zero) { // Failed to load our DEPP.DLL library from System32 or the application directory // Try the same directory that this Adept2 DLL is in hDMGR = LoadLibrary(@Path.GetDirectoryName(GetType().Assembly.Location) + "\\DMGR.DLL"); } } if (hDMGR == IntPtr.Zero) throw new ApplicationException("Cannot locate the driver's DMGR.DLL interface library."); // If we have succesfully loaded the library, get the function pointers set up // Set up our function pointers for use through our exported methods pDmgrGetVersion = GetProcAddress(hDMGR, "DmgrGetVersion"); pDmgrEnumDevices = GetProcAddress(hDMGR, "DmgrEnumDevices"); pDmgrGetDvc = GetProcAddress(hDMGR, "DmgrGetDvc"); pDmgrIsEnumFinished = GetProcAddress(hDMGR, "DmgrIsEnumFinished"); pDmgrStopEnum = GetProcAddress(hDMGR, "DmgrStopEnum"); pDmgrFreeDvcEnum = GetProcAddress(hDMGR, "DmgrFreeDvcEnum"); InitializeDelegates(); } private void InitializeDelegates() { if (pDmgrGetVersion == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrGetVersion."); if (pDmgrEnumDevices == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrEnumDevices."); if (pDmgrIsEnumFinished == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrIsEnumFinished."); if (pDmgrStopEnum == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrStopEnum."); if (pDmgrFreeDvcEnum == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrFreeDvcEnum."); DmgrGetVersion = (tDmgrGetVersion)Marshal.GetDelegateForFunctionPointer(pDmgrGetVersion, typeof(tDmgrGetVersion)); DmgrEnumDevices = (tDmgrEnumDevices)Marshal.GetDelegateForFunctionPointer(pDmgrEnumDevices, typeof(tDmgrEnumDevices)); DmgrGetDvc = (tDmgrGetDvc)Marshal.GetDelegateForFunctionPointer(pDmgrGetDvc, typeof(tDmgrGetDvc)); DmgrIsEnumFinished = (tDmgrIsEnumFinished)Marshal.GetDelegateForFunctionPointer(pDmgrIsEnumFinished, typeof(tDmgrIsEnumFinished)); DmgrStopEnum = (tDmgrStopEnum)Marshal.GetDelegateForFunctionPointer(pDmgrStopEnum, typeof(tDmgrStopEnum)); DmgrFreeDvcEnum = (tDmgrFreeDvcEnum)Marshal.GetDelegateForFunctionPointer(pDmgrFreeDvcEnum, typeof(tDmgrFreeDvcEnum)); } #region Instantiated Function Delegates internal tDmgrGetVersion DmgrGetVersion; internal tDmgrEnumDevices DmgrEnumDevices; internal tDmgrGetDvc DmgrGetDvc; internal tDmgrIsEnumFinished DmgrIsEnumFinished; internal tDmgrStopEnum DmgrStopEnum; internal tDmgrFreeDvcEnum DmgrFreeDvcEnum; #endregion #region IDisposable Methods /// <summary> /// Destructor for the D2XX class. /// </summary> ~StaticDmgr() { if (hDMGR != IntPtr.Zero) { // FreeLibrary here - we should only do this if we are completely finished FreeLibrary(hDMGR); hDMGR = IntPtr.Zero; } } public void Dispose() { if (hDMGR != IntPtr.Zero) { // FreeLibrary here - we should only do this if we are completely finished FreeLibrary(hDMGR); hDMGR = IntPtr.Zero; } } #endregion #region Marshalling Methods to Unmanaged DMGR /// <summary> /// Built-in Windows API functions to allow us to dynamically load our own DLL. /// Will allow us to use old versions of the DLL that do not have all of these functions available. /// </summary> [DllImport("kernel32.dll")] private static extern IntPtr LoadLibrary(string dllToLoad); [DllImport("kernel32.dll")] private static extern IntPtr GetProcAddress(IntPtr hModule, string procedureName); [DllImport("kernel32.dll")] private static extern bool FreeLibrary(IntPtr hModule); // Definitions for DMGR functions [UnmanagedFunctionPointer(CallingConvention.StdCall)] internal delegate int tDmgrGetVersion(byte[] szVersion); //OPEN & CLOSE functions internal delegate int tDmgrOpen(ref int phif, byte[] szSel); internal delegate int tDmgrOpenEx(ref int phif, byte[] szSel, int dtpTable, int dtpDisc); internal delegate int tDmgrClose(int hif); //ENUMERATION functions internal delegate int tDmgrEnumDevices(ref int pcdvc); //internal delegate int tDmgrEnumDevicesEx(ref int pcdvc, int dtpTable, int dtpDisc, int dinfoSel); //internal delegate int tDmgrStartEnum(ref int pcdvc); internal delegate int tDmgrIsEnumFinished(); internal delegate int tDmgrStopEnum(); //internal delegate int tDmgrGetEnumCount(ref int pcdvc); internal delegate int tDmgrGetDvc(int pcdvc, byte [] dvc); internal delegate int tDmgrFreeDvcEnum(); #endregion } }