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Showing content with the highest reputation since 02/22/18 in all areas

  1. 3 points
    @thobie, the bare-metal purchase option for the Zybo was done to enable a lower price point for those who do not require the accessories. For the rest of our customers, adding the Accessory Kit is recommended during the purchase process. You are not the first and the last to complain about version compatibility. It is economically unfeasible for us to update all support projects, IP and support packages provided for free four times per year for each Vivado version. Instead we made a commitment to consider the last Vivado release in each year stable and do a once-a-year update cycle. In that regard, 2017.4 is the version we are upgrading projects to. There is a question whether OOB designs should be updated at all, or kept at the version which generated the binary image shipped with the board. The board presets are not versioned for Vivado (no version-specific releases in our git repo), because these should be forward-compatible with Vivado versions. The critical warning itself related to CK-to-DQS delays being negative appears starting with 2017.4. The negative values are due to CK trace being shorter than any of the four DQS traces. In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Zybo was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Zybos shipped to customers are functionally tested and pass the DDR3 calibration process. Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. Since these delays are board-dependent, we would need to re-design the board to make the delay positive. This is impossible with the current form-factor. Another option would be modifying the board preset file and forcing a zero value instead of the actual delay. The tools seem to be using zero anyway for calibration. This will have to be thoroughly verified first.
  2. 3 points
    Hello, I've posted the next part in my FPGA graphics series using the Arty + VGA Pmod or Basys 3. It shows you how to make use of double buffering to animate sprites using simple Verilog. https://timetoexplore.net/blog/arty-fpga-vga-verilog-03 Feedback very welcome, Will PS. I'll add the source to GitHub shortly.
  3. 3 points

    WaveForms beta download

    3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Netowrk Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.
  4. 2 points

    VGA Pmod Tutorials

    Hello, I've been having a lot of fun with the VGA Pmod. I thought other forum members might appreciate a couple of tutorials I've produced with it. Part 1: Intro to VGA and basic animation: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 Part 2: Bitmap display using your own image: https://timetoexplore.net/blog/arty-fpga-vga-verilog-02 Both are written in pure Verilog, so it's (hopefully) easy to understand what's going on and adapt for your own projects. Feedback welcome, Will
  5. 2 points

    programming guide of zynq

    Hello @Ram, Please check this link : https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start "This guide will provide a step by step walk-through of creating a Zynq based hardware design using the Vivado IP Integrator that will build over the Getting Started with Zynqguide by making use of the on-board Ethernet port and GPIOs for the Zybo FPGA board.". You can start from here, and use the same hardware logic but different type of application for uart, spi etc. Best Regards, Bogdan Vanca
  6. 2 points

    Zedboard Zynq 7000 XADC Header

    Hi @farhanazneen, I used the Analog Discovery 2 which has the 2x15 Flywires: Signal Cable Assembly for the Analog Discovery without issue. Each signal wire is 260mm± 20. thank you, Jon
  7. 2 points
    @hamster I was able to run your AXI Slave interface. It works great! It is now very easy to exchange information between PS and PL, and it even supports execute-in-place (e.g. I can put ARM instructions to register file and run PS CPU directly from it). I have some questions about your AXI Slave design: 1) AXI_a*size has no effect on INCR type of burst transactions, but according to AXI protocol: the increment value depends on the size of the transfer. You set it only for WRAP type, is it correct? Thus, burst size is always 0 for INCR type? 2) Do you know how PS initiates INCR burst type? A kind of memset/memcpy need to be used for that or an incrementing pointer will also work? 3) Where WRAP type is necessary? How to use PS to work in WRAP mode? You may also update your wiki page with following: 0) Create provided VHDL files 1) Create a block-diagram and add PS IP core to it 2) Apply configuration provided by your board's pre-settings; this will set all necessary initialization settings for PS (e.g. clock frequencies, DDR bindings, etc.) 3) Press auto-configure (or how it's called) ==> this will connect PS IP to DDR and to fixed IO 4) Add "External ports" to the diagram (create new AXI_CLK and AXI external ports) and connect them to PS ports 5) Generate VHDL wrapping code for this block diagram 6) Put generated system under axi_test_top by renaming it to axi_test_wrapper (default name is design_#_wrapper in my Vivado version) 7) This will auto-connect block-diagram external ports with axi_test_top 8 ) Add constrains file and rename/uncomment external ports where necessary 9) Generate bitstream 10) File->Export->Hardware and create .hwf file which contains PS configuration 11) Open Xilinx SDK and create a new project: select .hwf file as Hardware BSP for this project 12) Now, Xilinx SDK will auto-generate few .c and .h files which contain necessary PS initialization ==> clocks, IRQs, DDR, etc. 13) Add hello_world.c application to the project @hamster Thank you very much. I've learned a bunch of new things thanks to your help!
  8. 2 points

    Where download 2015.4

    Hello @Bien, Please check this link : https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/sdx-development-environments/archive.html. Best Regards, Bogdan Vanca
  9. 2 points

    vivado 2017.4

    Thank-you melisha ,,it is working Ram
  10. 2 points
    Hi Jon, Just want to give you an update. I got it working using the PL AXI Quad SPI controller after I fixed my IO constraints. And I did contact the Avnet support you mentioned above. Here is the thread if you are interested. Again thank you very much for your help on my project. -Iris
  11. 2 points

    Beginner DSP Projects

    Yes Dan he certainly would agree with your advice. Test, verify, test, verify. Let it be your mantra. Test and verify the main result that you are looking for. Test and verify all of the component parts ( particularly in logic ) in case you want to reuse any modules or components. Test and verify corner cases. Test and verify consistency of results between all of the implementations. For the logic implementation there will be more subtle and complicated aspects to consider and test for. Assume nothing. If all of this doesn't sound like fun ( I'm taking the long view by using that word) ... perhaps consider a different way to spend your free time. Oh, and I forgot to mention the most important part. Don't do it for self-defense. You can learn a lot more during the test and verification stages... you know, the part where most people have gone on to other things assuming that everything works, than you can learn during the basic design processes. Testing and verification generally requires another level of awareness to issues not obvious in the original conceptual stages. That's my experience.
  12. 2 points
    Hi, I'm sure there will be some long follow-up answers. I specialize in short answers, so here we go 🙂 Engineers are frighteningly unsystematic. What engineers are good at is cutting corners. Either you're completely in over your head, or you are facing an easy problem. For easy problems, engineers do a quick sketch on a paper napkin (skip if no napkin is available) and start coding. So what you need is the Verilog skills to write down a FSM. Essentially, it might look like this reg [7:0] state = 8'd0 always @(posedge clk) begin switch (state) case 8'd0: if (something) then begin ... state <= 8'd1; end case 8'd1: if (something) then begin ... state <= 8'd2; end endcase // this must be at the bottom of the enclosing begin...end block if (synchronousReset) begin state <= 8'd0; ... set everything else to init values end end It might look completely different (matter of style) but avoid e.g. asynchronous reset as commonly found in pre-FPGA tutorials. Then write down what you think it should do. Simulate. Figure out why it does something else. Rinse and repeat and also update your understanding of what you think it should do... Oops. It wasn't that short.
  13. 2 points
    Piotr Rzeszut

    Analog Discovery 2 vs NI myDAQ

    Hi, NI myDAQ has an input sample rate of 200 kSPS and bandwidth of 400kHz, where AD2 has 100MSPS and 30MHz+ (with adapter) => point for AD2 NI myDAQ has maximum input voltage +-10V, where AD2 has +-25V => point for AD2 NI myDAQ has an output sample rate of 200 kSPS, where AD2 has 100MSPS => point for AD2 NI myDAQ has maximum output voltage of +-10V, where AD2 has +-5V => point for NI myDAQ NI myDAQ has a built-in multimeter (so it is able to measure in addition to voltage, also resistance, current, diode voltage without any additional adapters) AD2 requires separate adapters for such measurements => point for NI myDAQ NI myDAQ has fixed +-15V supplies (32 mA) and +5V (100mA), where AD2 has 0...5V and 0...-5V voltage outputs (700mA max with external power supply) => point for ??? Ni myDAQ has 8 digital IO, where AD2 has 16 of them. Also AD2 IOs can be controlled much faster than ones in myDAQ => point for AD2 This is a fast comparison of a key features. Full documentation of each device are available here: https://reference.digilentinc.com/reference/instrumentation/analog-discovery-2/reference-manual http://www.ni.com/pdf/manuals/373061f.pdf Summing up all above (in my opinion): AD2 is a better choice for debugging fast analog and analog/digital circuits. A software adds a great value by allowing various measurements and tools without any need of programming. Also an interface for python scripting allows designing own applications. There is also LabVIEW interface provided. You can always see all these functions in interactive demo - just download recent Waveforms software. https://reference.digilentinc.com/reference/software/waveforms/waveforms-3/start NI myDAQ offers much slower I/O and less digital channels. At the other hand it can be used as off-the-shelf multimeter`. It also includes basic software and interface for LabVIEW, but lacks for example interface control (I2C, SPI, ...). http://www.ni.com/tutorial/11431/en/ Also AD2 can be purchased in reduced price for academic use. This is of course my private opinion on these devices - you have to decide which one to buy by analyzing use cases.
  14. 2 points
    Hi, @sbobrowicz, Thank you for your reply. I found the cause of the problem and solved it. The ssm2603 driver was the cause. I found the link below with Google search. https://www.spinics.net/lists/alsa-devel/msg75416.html If you have a problem like me, try applying the patch above. (I am using Petalinux 2017.2 and Zybo-Z7-10. Linux version 4.9.0-xilinx) Thanks, Namio
  15. 2 points

    OpenCL on Zybo

    @mohammadhgh Unfortunately that platform does not support openCL. We hope to add it in a future release of the Zybo Z7 SDSoC platforms. It might be possible to add OpenCL support to that platform by just adding OpenCL as a "Supported Runtime". See UG1146 from Xilinx for info on how to do this.
  16. 2 points

    Zybo z7-20 Zynq Presets

    Hi @Mahesh, As @jpeyron said in the post marked as accepted solution, the Zynq processing system will be configured with the board presets when you first add the Zynq processing system IP core to the block design and run the block automation task from the green message that appears! Just remember to keep the Apply Board Preset option checked as shown in he picture. So this means if you are using the pre-built block design from the example project, a possible solution can be to remove the existing Zynq processing system block and adding a new one!
  17. 2 points
    Hi @Hiroki Tamakoshi See the Scope/ Add Channel/ Math/ Filter
  18. 2 points
    Thanks) It solved the problem)
  19. 2 points

    Zybo board repair

    Thanks @jpeyron. I am tempted to short R281 and power it though usb to check if it would work before i order the fuse. any suggestions. Ok I couldn't wait so I shorted the fuse and the PGOOD light came on.I haven't carried out any further test. I will wait until the fuse arrives. Thanks once again. Asim
  20. 2 points
    Apparently the problem was in github. Using git config --global url."https://".insteadOf git:// Seems to fix the issue. I had already modified the problematic .bb files by hand in a previous attempt, but then it didn´t work
  21. 2 points

    Query on schematic of CRII board

    Hi @Arvind Gupta, We reached out to one of our design engineers and they responded that the 200 ohm resistors are protection against drive conflicts between an offboard programmer attached to header J8 and the onboard USB controller. The pull-ups are there so that the TMS and SS lines idle in the inactive states. thank you, Jon
  22. 2 points

    rgb2dvi IP customization Part 2

    Hello @dgottesm, If you look into rgb2dvi module you will found out, on line 36 this sintax: "kClkPrimitive : string := "PLL"; -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true". So, by default the clock primitive is instantieted as an PLL. For an 27 Mhz it is impossible to respect the minimum value for the PLL VCO frequency. Please check table 38 from the attached document. But, it is possible to do it if you instantiante the clk primitive as an MMCM. In this case the low boundery for the MMCM VCO frequency is 600.00 Mhz. For more details you can check the Table 37 from the same document. So, you need to chose the value "5" for the "kClkRange", because that will outputs you an 675 Mhz frequency for the VCO (20 x 25). And that value respects the MMCM constraints and also the project constraints. Also, don't forget to set the 27 Mhz into the xdc file. A strong recommendation for you is to do all the modification manually into the vhdl's modules. And after that, if everything looks ok and you want go further into the block-design, you can do the same stuff there with the help of the "edit in ip packager" option. Answers for your questions: 1) Thats the minimum value if you instantiate the kClkPrimitive as an PLL. 2) For this question, you can take as an answer the above text. I hope I was clearly enough. I look forward to hearing from you. Best Regards, Bogdan Vanca ds181_Artix_7_Data_Sheet.pdf
  23. 2 points
    I've just finished reinstalling the WF32 bootloader onto two of my WF32s, and I'm still getting the "Unable to signon, this does not look like a bootloader" error. I downloaded the bootloader from here: https://reference.digilentinc.com/reference/microprocessor/wf32/start I used chipKIT programmer, and programmed using the MPLAB IPE. The IPE claims that the bootloader was verified, so I'm wondering if there's maybe a problem with the bootloader I'm using. Either that or maybe the FTDI is busted? EDIT: I've figured out the problem and of course it was something stupid. While programming the bootloader, I had the VV Select jumper set to something other than UART. That's all. I've reprogrammed the bootloader and now everything works fine. Thanks for the help @james!
  24. 2 points
    Hi @BYTEMAN, Feel free to put up your dropbox link to your project if you so wish; I know we had communicated about this earlier, but for the interest of letting other users know that they may put dropbox links or google drive or something similar links to their project if the Vivado project gets too big to upload. Alternatively, pictures can be uploaded via the Gallery which doesn't have the same upload restrictions as putting the image directly into the post. Thank you, JColvin
  25. 2 points

    Analog Discovery 2 vs Raspberry Pi 3

    FTDI USBs like AD, AD2, DD are not working with RPI model B (1,2,3) data packets/bytes are randomly lost. The EExplorer with different USB controller is working fine on these. All devices are working with other embeddeds: Zed, Zybo, BeagleBone… According reports AD is working with the original RPI model A and probably Zero because it has similar chipset/USB. The problem seems to be with FTDI or RPI B USB, library or hardware. You can find such comments regarding RPI problems with other devices too. Unfortunately we couldn't remediate this problem.