here is another version of the script i am working on, it does both channel it does scale the frequencies logarithmically it does the averaging if trace 1 type allows count to be enabled. it saves to a desktor CSV file for data manipulation in a speadsheet. I made some modifications to the spreadsheet I use in hope it will be more generic and useful to others. I also wrote some short instructions on how to proceed, but I am afraid it won't be clear for beginners. I also made a drawing of dummy load and possible attenuator for interconnection with the Analog Discovery. I thd1watt.bmp there were errors in the files, new files will be posted in an other post.
Hi @etownsend, There is the option of adding a 100 MHz oscillator to the Cmod A7. Here is a forum thread that discusses this option. The oscillator would be added to IC4. You can see this in the schematic here on the bottom of page 3. This is a more complicated processes and requires removing R80 along with adding the oscillator to IC4. I would not suggest this option. The other two suggestions @sLowe referred to are different ways to generate a 100 MHz clock one using the Xilinx Clocking wizard here(my suggestion as well). The other is referring to @D@n suggestion of using a PLL(phase-locked loop) to generate a 100 MHz clock. Here is another forum thread that discusses generating a different clock using MMCM dynamic clocking(a much more complicated way). cheers, Jon
@cnun999, Well, if you can't share your code, then there's not much I can do to fix it. Sorry. You might find it valuable though to take pieces out of it, and see if that helps you narrow down the problem--but I'm repeating myself to say this at this point. You might also considering entering into a contract arrangement with a more experienced designer, working some non-disclosure agreements through the legal team, and trying again. I'd offer my services to that end but ... I don't use system designer much. So, again, I'm sorry I can't be of much more help. Dan