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  1. 3 points
    An FPGA can be a useful "swiss army knife", but all the nice features aren't easily accessible. Enter "LabToy": A batteries-included collection of utilities, just double-click and go. As the name implies, this isn't meant to compete against "real" test equipment. The main selling point is like a pocket knife - this fits into a shirt pocket and the power tools don't. And speaking of "selling points", it's free to use. So what do we have here: - Digital data: Shows the input state of all pins - Analog data: Readings from the two ADCs, up to about 700 ksps sustained (XADC "simultaneous sampling" mode, phase-accurate between channels) - Streaming data logger: Both analog and digital data can be written to a .vcd file, to be shown in gtkwave. There is no limit to the capture length. - Analog signal generator: 8 fully independent channels, sine, square wave, the usual suspects. Well, the DACs won't win any audiophile awards, but they are usable. - "Programmable" digital LED mode: Configurable pulse width to suppress short glitches, or edge detect with a built-in pulse generator to highlight them. - Analog LED mode: Shows the input value of the ADC in real time Some screenshots: 1k sine / cosine from DAC jumpered to ADC (in gtkwave) The digital signal is the generator's sync output that can be recorded as a digital input. Realtime display of the inputs. With pocket knives in mind ("this button will unlock the large blade, allowing it to be manually returned to its folded position") I decided to keep the screen uncluttered and put descriptions into tooltips. The large displays are the average voltage readings from the ADC. The smaller ones show the digital inputs in groups of four. Generator controls (frequency, minimum voltage, maximum voltage, phase). The voltage scaling is a bit unusual (typically there is "AC magnitude" and "DC offset") but I chose this approach because it shows clearly the limitations of the 0..3.3V output range. Most people will probably leave all this at the default values for a full-scale signal. Data capture Example: The output in gtkwave after I touched a jumper cable to the digital inputs on the DIL connector. +++ DO NOT USE THE +5V OUTPUT P24 FOR THIS KIND OF TEST +++ (3.3 V is available on the PMOD connector, bottom row) The red "undefined" marks flag the first input in an 8-bit group. In this example, they aren't too meaningful, but they can alert me to the fact that no data events have been observed yet. LED control The two numbers give the number of consecutive 1 or 0 samples (at 125 MHz) before a signal change is propagated to the LED. E.g. put 125 million there and it'll take one second after changing the input state for the LED to light / go dark. Those can be used interactively to study an unknown signal. "Level": no further processing ("level" mode and 1 / 1 sample counts is equivalent to directly connecting the LED to the physical input) "Edge" mode generates a brief pulse on signal changes, the LED is dark otherwise. "Invert" flips the input right next to the pin (0 becomes 1, black becomes white and man gets himself killed on the next zebra crossing -DA). How to get it: The file is attached: labToy0v1_beta.exe The installer unpacks a single .exe. Happy hacking! Requirements: Windows 64 bit (!) .NET 4.5 FTDI libraries CMOD A7 35 T (not 15 T). Warnings: Direct access to digital IO pins is an inherently dangerous activity. "PROVIDED WITHOUT WARRANTY OF ANY KIND" means Just That. And beware of the +5V pin. PS: If you try it, kindly let me know whether it works, or what goes wrong.
  2. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  3. 2 points
    kwilber

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  4. 2 points
    Hi @neocsc, Here is a verified Nexys Video HDMI project updated from Vivado 2016.4 to Vivado 2017.4. You should be able to find the updated project in the proj folder . Here is a GitHub project done in HDL using the clocking wizard, DVI2RGB and RGB2DVI IP Cores for another FPGA. Here is a unverified Nexys Video Vivado 2017.4 HDMI pass through project made from the linked Github project. In the next few days I should have the bandwidth to verify this project. thank you, Jon
  5. 2 points
    The warning you pasted is benign and simply means there are no ILAs present in your design. The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design. Finally, @elodg gives some great troubleshooting information in this thread.
  6. 2 points
    Hi @akhilahmed, In the mentioned video tutorial, the leds are controlled using "xgpio.h" library but the application is standalone. If you want to use a linux based application you have to use linux drivers for controlling. In the current Petalinux build, which is used in SDSoC platform, UIO driver is the best approach. Steps: 1. Vivado project generation: - Extract .dsa archive from /path_to_sdsoc_platform/zybo_z7_20/hw/zybo_z7_20.dsa - Launch Vivado - In Tcl Console: cd /path_to_extracted_dsa/prj - In Tcl Console: source rebuild.tcl - In this point you should have the vivado project which is the hardware component of SDSoC platform. Open Block Design. Change to Address Editor Tab. Here you will find the address for axi_gpio_led IP: 0x4122_0000 2. Petalinux UIO driver: - Launch SDx - Import zybo-z7-20 SDSoC platform - Create a new SDx linux based project using a sample application (e.g. array_zero_copy) - Build the project - Copy the files from /Dubug/sd_card to SD card - Plug the SD card in Zybo Z7. Make sure that the JP5 is set in SD position. Turn on the baord - Use your favorite serial terminal to interact with the board (115200, 8 data bits, 2 stop bits, none parity) - cd to /sys/class/uio - if you run ls you will get something like: uio0 uio1 uio2 uio3 uio4 uio5 - Now you have to iterate through all these directories and to search for the above mentioned axi_gpio_led address: 0x4122_0000 - For example: cat uio0/maps/map0/addr will output: 0x41220000, which means that the axi_gpio_led can be accessed using linux uio driver through uio0 device. - Code: #include <stdio.h> #include <stdlib.h> #include <sys/ioctl.h> #include <sys/mman.h> #include <stdint.h> #include <unistd.h> #include <fcntl.h> #define UIO_MEM_SIZE 65536 #define UIO_LED_PATH "/dev/uio0" void UioWrite32(uint8_t *uioMem, unsigned int offset, uint32_t data) { *((uint32_t*) (uioMem+offset)) = data; } uint32_t UioRead32(uint8_t *uioMem, unsigned int offset) { return *((uint32_t*) (uioMem+offset)); } void led_count_down(uint8_t *ledMem) { uint8_t count = 0xF; uint8_t index = 0; for (index = 0; index < 5; index++) { UioWrite32(ledMem, 0, count); count = count >> 1; sleep(1); } } int main() { // Set Leds as output int led_fd = open(UIO_LED_PATH, O_RDWR); uint8_t *ledMem = (uint8_t *) mmap( 0, UIO_MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, led_fd, (off_t)0); UioWrite32(ledMem, 4, 0x0); // Set all leds as output while(1) { // Start led count-down led_count_down(ledMem); } return 0; } - Build the project and copy the content of Debug/sd_card on SD sd_card - Power on the board and connect to it using a serial terminal - run the following commands: mount mmcblk0p1 /mnt cd /mnt ./project_name.elf - Result: A countdown should be displayed on leds.
  7. 2 points
    JColvin

    Arty A7 flash chip

    Hi @D@n, I believe the new part that is used in the Arty A7 boards (and other A7 boards) is now a Spansion S25FL128SAGMF100; based on old schematics, I believe this was added in Rev D of the Arty A7 (dated August 2017), though I do not know when that particular Rev was then released (or if it even was released) to the public. I confirmed that the Arty S7 also uses this part and I wouldn't be surprised if most of our other Artix 7 based boards use it now as well. I've requested that the chip name and images are updated in any appropriate tutorials and requested that the pdf version of the reference manual (updated wiki) is updated as well. Thanks, JColvin
  8. 2 points
    @hamster I was able to run your AXI Slave interface. It works great! It is now very easy to exchange information between PS and PL, and it even supports execute-in-place (e.g. I can put ARM instructions to register file and run PS CPU directly from it). I have some questions about your AXI Slave design: 1) AXI_a*size has no effect on INCR type of burst transactions, but according to AXI protocol: the increment value depends on the size of the transfer. You set it only for WRAP type, is it correct? Thus, burst size is always 0 for INCR type? 2) Do you know how PS initiates INCR burst type? A kind of memset/memcpy need to be used for that or an incrementing pointer will also work? 3) Where WRAP type is necessary? How to use PS to work in WRAP mode? You may also update your wiki page with following: 0) Create provided VHDL files 1) Create a block-diagram and add PS IP core to it 2) Apply configuration provided by your board's pre-settings; this will set all necessary initialization settings for PS (e.g. clock frequencies, DDR bindings, etc.) 3) Press auto-configure (or how it's called) ==> this will connect PS IP to DDR and to fixed IO 4) Add "External ports" to the diagram (create new AXI_CLK and AXI external ports) and connect them to PS ports 5) Generate VHDL wrapping code for this block diagram 6) Put generated system under axi_test_top by renaming it to axi_test_wrapper (default name is design_#_wrapper in my Vivado version) 7) This will auto-connect block-diagram external ports with axi_test_top 8 ) Add constrains file and rename/uncomment external ports where necessary 9) Generate bitstream 10) File->Export->Hardware and create .hwf file which contains PS configuration 11) Open Xilinx SDK and create a new project: select .hwf file as Hardware BSP for this project 12) Now, Xilinx SDK will auto-generate few .c and .h files which contain necessary PS initialization ==> clocks, IRQs, DDR, etc. 13) Add hello_world.c application to the project @hamster Thank you very much. I've learned a bunch of new things thanks to your help!
  9. 2 points
    mohammadhgh

    Zybo z7-20 Zynq Presets

    Hi @Mahesh, As @jpeyron said in the post marked as accepted solution, the Zynq processing system will be configured with the board presets when you first add the Zynq processing system IP core to the block design and run the block automation task from the green message that appears! Just remember to keep the Apply Board Preset option checked as shown in he picture. So this means if you are using the pre-built block design from the example project, a possible solution can be to remove the existing Zynq processing system block and adding a new one!
  10. 2 points
    BogdanVanca

    rgb2dvi IP customization Part 2

    Hello @dgottesm, If you look into rgb2dvi module you will found out, on line 36 this sintax: "kClkPrimitive : string := "PLL"; -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true". So, by default the clock primitive is instantieted as an PLL. For an 27 Mhz it is impossible to respect the minimum value for the PLL VCO frequency. Please check table 38 from the attached document. But, it is possible to do it if you instantiante the clk primitive as an MMCM. In this case the low boundery for the MMCM VCO frequency is 600.00 Mhz. For more details you can check the Table 37 from the same document. So, you need to chose the value "5" for the "kClkRange", because that will outputs you an 675 Mhz frequency for the VCO (20 x 25). And that value respects the MMCM constraints and also the project constraints. Also, don't forget to set the 27 Mhz into the xdc file. A strong recommendation for you is to do all the modification manually into the vhdl's modules. And after that, if everything looks ok and you want go further into the block-design, you can do the same stuff there with the help of the "edit in ip packager" option. Answers for your questions: 1) Thats the minimum value if you instantiate the kClkPrimitive as an PLL. 2) For this question, you can take as an answer the above text. I hope I was clearly enough. I look forward to hearing from you. Best Regards, Bogdan Vanca ds181_Artix_7_Data_Sheet.pdf
  11. 2 points
    xc6lx45

    Cmod A7 oscillator question

    PS: Reading the above post: I suggest you DO use the IP wizard, not calculate it manually. Pain does not equal gain.
  12. 2 points
    xc6lx45

    Vivado slowness reality check

    For comparison: My labToy project on CMOD A7 35 builds in 3:40 min (excluding clock IP, measured on my wristwatch by resetting synthesis, then "generate bitstream"). It's not a large project - about 20 % of DSP used and slices touched - but not trivial either. A hello-world project compiles in maybe 1 min, give or take some. But my desktop was built for the job (water-cooled i7 4930 @ 4.5G, 32G quad-channel RAM, M2 SSD). Most of this doesn't help with a one-LED design, but there are a number of things that will slow down the run considerably: - Use correct timing constraints: For example, a LED driven from logic clocked at 200 MHz can be very difficult to route (but at the 12 MHz crystal frequency it shouldn't matter much). A simple set_false_path -to [get_ports LED] makes it "don't-care". - Throw in extra registers where appropriate, especially between blocks (which tend to be physically separate). Most of the time, it does not matter whether the signal arrives one or two clock cycles late, and some spare registers will simplify implementation. This is especially useful for register rebalancing. - For the extra registers, it may make sense to use a "don't touch" attribute. E.g. in Verilog: (* DONT_TOUCH = "TRUE" *)reg [5:0] wa [1:NWRDELAY]; (* DONT_TOUCH = "TRUE" *)reg [17:0] wd [1:NWRDELAY]; (* DONT_TOUCH = "TRUE" *)reg we [1:NWRDELAY]; When I have multiple, parallel instances of a timing-critical block, the input registers are logically equivalent, get optimized away, and then P&R takes ages because timing is so difficult. The "don't touch" attribute" keeps them separate, possibly using a couple of FFs more than strictly necessary. - Removal of redundant logic can take a long time. For example, when I simulate pipelined DSP like the "labToy" generators I simply carry all data all the way through the pipeline, even though most of it isn't needed. Optimization will eventually remove it, but the cost is runtime. The LabToy example includes 8 instances each with a 6-lane 14-cycle 18-bit wide pipeline, and it adds minutes to the synthesis time if I don't remove the unused ends of delay chains in the source code. - Read and understand every warning, and read the timing report. "The compiler is my friend" For example, with PLL blocks it is easy to create duplicate clocks with the same frequency (one from the constraints file, one from the IP block). Timing analysis tries to (and will eventually) sort out all possible interactions, but it takes a lot of time and can create meaningless but difficult routing constraints. - Fix "critical warnings" related to timing. Even if common sense tells the design will work e.g. classroom demo with buttons, Vivado will waste a lot of time trying the impossible.
  13. 2 points
    I solved my ethernet problem and the specific connections to make it work. I didn't have I2C enabled on the Zynq7 customisation. so I also enabled I2C over EMIO. I think this hampered it's ability to communicate with the address chip I changed in the Zynq 7 processor MIO configuration - the ENET0 MDIO device is now MDIO pins MIO 52-53.
  14. 2 points
    @Shuvo Sarkar What exactly needs to be done depends on what you mean by "region of interest" and "binary mask". I will assume that you are trying to replace some area of what is being displayed on the screen with a rectangular image. A good starting point would be to take the input stream and output it with modifications. The DemoScaleFrame function in video_demo.c does this. The resolution scaling being done by this function also may or may not be desirable for your project. The Bilinear interpolation function implemented on line 473 of the original source is the primary point of interest here. The three variables required to tell what is being written to in the destination frame are the index, i, which can be used to determine the color channel being written to, and the destination coordinate variables xcoDest and ycoDest. A good starting point to be able to see changes being made would be to add extra code to black out a rectangular area of the screen. This can be accomplished by wrapping the destFrame[iDest] statement within an if statement, that either writes a zero to destFrame[iDest] or runs the bilinear interpolation of the source frame, depending on the coordinates of the target pixel in the destination frame. How you store, access, and process the binary mask (overlay image?) is a large topic that I would need more details to provide information on. Let us know if you have more questions. -Arthur
  15. 2 points
    attila

    Analog Discovery 2 vs Raspberry Pi 3

    FTDI USBs like AD, AD2, DD are not working with RPI model B (1,2,3) data packets/bytes are randomly lost. The EExplorer with different USB controller is working fine on these. All devices are working with other embeddeds: Zed, Zybo, BeagleBone… According reports AD is working with the original RPI model A and probably Zero because it has similar chipset/USB. The problem seems to be with FTDI or RPI B USB, library or hardware. You can find such comments regarding RPI problems with other devices too. Unfortunately we couldn't remediate this problem.
  16. 2 points
    @Sam_a Should be fixed this time. Thanks for your patience, Arthur
  17. 1 point
    zygot

    Using tera term for two pmods

    Well I think that this is better stated as saying that most serial terminal applications can only connect to one COM port at a time. It is possible to mave multiple UARTs in your FPGA design and connect to multiple serial terminal applications. I like Putty myself, but there are other options. Another possibility is to look around in the Digilent Project Vault and see at least 3 project with source code that might accomplish what you want to do. If you instantiate your own UART you can access any number of internal registers or memory.
  18. 1 point
    jpeyron

    GPS Pmod

    Hi @cepwin, I'm glad you we able to get to the bottom of the issue. Thank you for sharing what happened. cheers, Jon
  19. 1 point
    Hi, I just have opened a new terminal and launch minicom through the new terminal which works the same way as SDK terminal but I have to close the SDK terminal before connecting to minicom. Thanks @D@n and @jpeyron
  20. 1 point
    attila

    Scope custom math channel limitations?

    Hi @P. Fiery You could use the View/Logging/Script to create an up-sampled reference channel like this: var rg = [] var v2 = 0 Scope.Channel1.data.forEach(function(v1){ rg.push((v1+v2)/2) rg.push(v1) v2 = v1 }) // upsampling by 2 doubles the sample rate Scope.Ref1.setData(rg, 2*Scope.Time.Rate.value)
  21. 1 point
    SmashedTransistors

    BASYS3 and Axoloti

    Thanks @OvidiuD, I'll take one step after another and the forums are quite a good source of knowledge. So far, I plan to start with very basic schemes in order to understand how Vivado works. Then I will work on communicating with the Axoloti through SPI. Best regards
  22. 1 point
    attila

    Logic Analyzer Counter Function

    Hi @Lars Lindner You can perform a recording and see the pulses using quick measurements or measurements like this:
  23. 1 point
    Hi, >> We are forced to work in assembly with picoblaze. you might have a look at the ZPU softcore CPU with GCC. The CPU is just a few hundred lines of code but most of its functionality is in software in the crt.o library in RAM. I understand it's quite well tested and has been used in commercial products. Not surprisingly, using an FPGA to implement a processor that then kinda emulates itself in software (aka RISC :) ) is maybe not the most efficient use of silicon - I'm sure it has many strong points but speed is not among them... Unfortunately, the broken-ness of Xilinx' DATA2MEM utility (to update the bitstream with a new .elf file) spoils the fun, at least when I tried in ISE14.7 (segfaults). When it works, the compile/build cycle takes only a second or two. Long-term, porting the processor to a new platform would be straightforward, or even fully transparent if using inferred, device-independent memory. This would also work for a bootloader that is hardcoded into default content in inferred RAM. I might consider this myself as a barebone "hackable" CPU platform strictly for educational purposes.
  24. 1 point
    You might have a look at Trenz Electronics "Zynqberry". I think they managed to get one of the cameras to work (not sure). What I do remember is that the board has some custom resistor circuitry to additional pins for the required low-speed signaling.
  25. 1 point
    Hi @bklopp, Here is a completed Nexys Video UART interrupt project in Vivado 2018.2 that uses interrupts in microblaze. thank you, Jon
  26. 1 point
    Hi @jli853, I reached out to one of our design engineers about this forum thread. They responded that "Unless you do a non-blocking (overlapped) transfer the time it takes to execute the function will include not only the time to transfer the data over USB but also to shift it onto the JTAG scan chain. When the function returns all data has been transferred to the target JTAG device. How long that takes is going to very with the TCK frequency, as well as the PC side hardware and operating system. I don’t have any measured data to provide." thank you, Jon
  27. 1 point
    jpeyron

    Labview with 7-segment display

    Hi @BROLYNE, I have not worked with multisim. I did find Digilent's Programming Digilent FPGA Boards Through Multisim and NI's Getting Started with Digilent Boards in Multisim tutorials that should help with getting the seven segment going. thank you, Jon
  28. 1 point
    Hi @sungsik, Those symbols show that the pins are differentially paired. The nomenclature of the pins also describe positive and negative. cheers, Jon
  29. 1 point
    jpeyron

    Zedboard WiFi usage

    Hi @harika, Glad to hear you were able to get the bitstream to generate. cheers, Jon
  30. 1 point
    jpeyron

    ADXL345 with SPI and LabView

    Hi @billskar23, The Pmod ACL here uses the adxl345. Here and here are forum threads that might be helpful. Here is an instructable on how to use spi in the linx platform. Here is spi open. Here is the plug and play instructable for linx. Here is another instructable using the Pmod ACL. Unfortunately, both of the instructables use the Pmod ACL in I2C and not SPI. Here is the adxl345 datasheet. On page 23 is the register map table. Page 15 describes how to use the spi communications. Clearing the SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31) selects 4-wire mode. cheers, Jon
  31. 1 point
    attila

    Frequency profile generation with script

    Szia @Andras The Network Analyzer by default takes controls over the Wavegen channel 1 and configures the required frequency for each step. You could select NA/Wavegen/Channel/External but to be able the control the Wavegen manually, but in this case the previous Script solution won't work. The Insert/Local lists specific variables and is available in other scriptable places, like scope custom math, measurements, logging, network analyzer custom plots In each script editor including the Script tool you can use the Ctrl+Space to list available objects, variables... or child objects, properties, functions..
  32. 1 point
    attila

    Math on FFT traces

    Hi @lab!fyi In the Network Analyzer extended option lets you use Wavegen channels at up to 20MHz and with external up to 50MHz. In the Spectrum Analyzer you can select frequency range up to 10MHz but with auto option lets you set Stop frequency up to 50MHz. Selecting the dB unit will let you specify custom reference, for dBm I think it should be 0.316V
  33. 1 point
    Hi @jma_1 See the help of the application: The Protocol interface uses the device Digital Pattern Generator and Logic Analyzer resources to transfer data using UART, SPI, and I2C protocols. When the Debug option is enabled, the Logic Analyzer can be used to investigate the signals. In this case, the Protocol instrument will not receive data, it will only send data.
  34. 1 point
    Hi @remalytics, I have moved you forum thread to a section where more experienced WaveForms/AD2 engineers look. thank you, Jon
  35. 1 point
    Notarobot

    How to read from SD card on ZYBO

    shahbaz, Typically src folder contains C-code written by the person who design the project. It should contain the main function. You can try attached Xilinx test code. It's rudimentary but you can change it to your needs. Also you don't need to copy Xilinx files into src folder, they will be added to your project from the BSP. TestSD.c
  36. 1 point
    attila

    Digital Discovery SPI interface

    Hi @Sung The WaveForms application can be used in demo mode to explore the features. In demo mode the protocol signals are not generated properly but you can see the options a real device would provide. 1. You can use the Logic Analyzer to capture and decode communication. This is mostly useful for debugging protocol like for timing, glitches... 2. You can use the Protocol interface to send or to capture data and save in text file. You can also use JS code to automate communication in Custom tab or Script interface. 3. You can use the WaveForms SDK to create custom application/script.
  37. 1 point
    One thing I realized in the course of mulling this question: Part of my early resistance to splitting pio[...] into pioA, pioB and pioC was that I wanted to implement a bus that would span those ranges, and had a mental block about how to achieve that. It's not very difficult, but in case someone else has the same hiccup, I'll post an example solution here: module top( input sysclck, output [1:0] led, input [14:1] pioA, input [23:17] pioB, input [48:26] pioC ); wire [8:1] mybus; assign mybus[4:1] = pioA[14:11]; assign mybus[8:5] = pioB[20:17]; assign led[0] = &mybus; assign led[1] = &pioA[10:1]; endmodule I should note in passing that the supplied xdc file has another problem. In the supplied xdc file, pio[1]..pio[9] are written as pio[01]..pio[09], as in: set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports { pio[01] }]; #IO_L8N_T1_AD14N_35 Sch=pio[01] The xdc file is a TCL language file, and it may not be evident what the { pio[01] } actually means. It looks like it would be an array pio, with index 01, which one might assume is an integer, and thus equivalent to plain 1. In fact, the {...} is syntax to enclose a string, which is not to be interpolated (no substitutions made). So the result of { pio[01] } is the string: " pio[01] " ... including the spaces! In short, the string " pio[01] " is used verbatim as a string key for some array/hashtable/dictionary. It does not imply that there's an array called "pio", from which this code fetches the item at index 1. But then how does this match up to a particular port object declared in module top's declaration (where pio[14:1] treats the numbers in the index range as integers). There is some mechanism in get_ports or somewhere that must match this string index ("key") to top's port declaration. So the {...} string as written in the xdc file has to follow the pattern that the matching algorithm uses, which pio[01] does not, apparently. Consequently, xdc's pio[01] fails to match top.v's pio[1], etc. (And Vivado will give some obtuse error message about "Unspecified I/O Standard", and fails to generate bitstream.) Instead, you have to edit the xdc file for all the cases where pio[xx] has a leading zero, and remove it. So, for example, { pio[01] } should be edited to { pio[1] }. This does satisfy the matching algorithm. For further illumination on this syntax, you might like to try the following code: set result A append result { pioA[01] } append result B puts $result ... at an online TCL interpreter, like: https://www.tutorialspoint.com/execute_tcl_online.php This prints a result "A pioA[01] B", demonstrating that the action of the {...} syntax used in the xdc file is simply to produce a string, which is used verbatim as an argument to get_ports.
  38. 1 point
    Hi, I split it into pioA, pioB and pioC groups, as follows: module top(input wire CLK12, output wire [1:0] LED, output wire RGB0_Red, output wire RGB0_Green, output wire RGB0_Blue, input wire [14:1] pioA, // 14 input wire [23:17] pioB, // 7 input wire [48:26] pioC, // 23 inout wire [7:0] ja, // 8 input wire [1:0] BTN, input wire [1:0] xa_n, input wire [1:0] xa_p); and the constraints file: ... set_property PACKAGE_PIN L1 [get_ports {pioA[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {pioA[13]}] set_property PULLDOWN true [get_ports {pioA[13]}] set_property PACKAGE_PIN L2 [get_ports {pioA[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {pioA[14]}] set_property PULLDOWN true [get_ports {pioA[14]}] set_property PACKAGE_PIN M1 [get_ports {pioB[17]}] set_property IOSTANDARD LVCMOS33 [get_ports {pioB[17]}] set_property PULLDOWN true [get_ports {pioB[17]}] set_property PACKAGE_PIN N3 [get_ports {pioB[18]}] set_property IOSTANDARD LVCMOS33 [get_ports {pioB[18]}] set_property PULLDOWN true [get_ports {pioB[18]}] ... Not pretty, but at least I don't need to renumber.
  39. 1 point
    xc6lx45

    FPGA audio - ADC and DAC

    If I take it to extremes, the answer is surprisingly complex (this is how it's done inside the clock management tiles or a cellphone, for example). For household use, take (e.g.) a 32 bit counter and add "delta" at a high frequency, e.g. 100 MHz. Don't check for overflow, it will wrap around cyclically (which is the "correct" way to behave in this application. E.g. 0xFFFFFFFF + 3 becomes 0x00000002) For example, at 100 MHz clock, a delta of 1 gives a cycle time of 42.9 seconds (2^32 / 100e6). A delta of 43 gives a cycle time of one second. A delta of 42950 gives a cycle time of exactly 1 ms => 1 kHz. Now we've got a 32 bit number. Take the highest bits (as many as the DAC needs), voilà, a sawtooth generator. Plug that into your wavetable (you'll have to recalculate for a 0..31 range if using five ramp bits). Simple lookup from a block RAM (aka "nearest-neighbor / zero-order interpolation") will give abysmal audio quality, or the wavetable grows so large that it doesn't fit into the FPGA. So I need higher-order interpolation or a different algorithm (e.g. CORDIC for sine), and things get messy. PS: When working with signed numbers, check Verilog's "signed" keyword. It's not mandatory, but makes life easier.
  40. 1 point
    jpeyron

    HOW TO PERMANENTLY PROGAM NEXY4 DDR

    Hi @flexible111, I apologize, I was out of the office the last couple of days and did not have access to a Nexys 4DDR. I will get to this as soon as I can. I am sorry for the inconvenience. It may be a couple of days due to activity on the forums. thank you, Jon
  41. 1 point
    freakuency

    Zybo Z7-20: FTDI DOA?

    Solved by this: /opt/Xilinx/Vivado/2017.4/data/xicom/cable_drivers/lin64/install_script/install_drivers
  42. 1 point
    Hi @zuleikha, Here is an Avnet forum thread that goes through a few possibilities and some solutions to the "No Target with ID 64 in the System" error. I would also suggest to go through Getting Started with Zynq tutorial. Here is our resource center for the zedboard as well cheers, Jon
  43. 1 point
    I searched for inactive driver in the Windows device manager and found out that there appear 2 x USB Serial Converter A and 2 x USB Serial Converter B. I deleted all of them and powered the board. Now both boards work.
  44. 1 point
    D@n

    cmods6 pinS

    @jvalls, You picked a good platform. I love my CMod-S6. It has taught me to appreciate every logic unit on the board. You can see what I did with mine here: a home-made CPU running a fully multi-tasking O/S! I personally never used the I/O planner. I instead found the master UCF file and edited it for my own purposes. (I must be crusty--I trust text files that I can edit over anything I can point-and-click with a mouse). For the most part, all I ever did was to change the names of the pins I wanted to use and commented pins I wasn't using. You may need to use the schematic to trace the pins from their I/O connections all the way to the FPGA names used in the UCF file. It can be annoying, but it's quite doable. Hope this helps, Dan
  45. 1 point
    Yes, I used the weighted method for converting to gray scale. I did it using integer math, which makes it a bit more complicated, but basically I just multiply each color by (W*256), then divide the result by 256. This allows the avoidance of floating point arithmetic.
  46. 1 point
    JColvin

    Save an acquisition

    Hi @jpnbino, I don't necessarily have the answer to your question, but just as a clarification question so that we ensure we understand what you are looking for, you want to be able to: - capture data with logic analyzer - save the data - reopen the data from inside the logic analyzer tool itself so you can scroll and zoom and use the cursors as you please Is that accurate? Thank you, JColvin
  47. 1 point
    Natsu

    FPGA based PWM generation

    Hello! I don't know much about PWM or PDM, so maybe I've misinterpreted everything but I was under the impression that the blog post wasn't intended to be the ultimate solution for everything. I don't disagree that engineering should be replicated by other people to help ensure it all works rather than accepting stuff blindly, especially if it's vital for a projects success, but it looked like D@n was looking for better audio quality rather than launching rockets... On a different note, it looks like from his main blog page that D@n was at some conference these past few days so maybe he hasn't looked at this thread in the meantime? I'm just a little confused since it seems like you were aware of this in one of your posts with the "across the pond" statement but then proceeded to reply several more times with some apparent confusion as to why he hasn't responded. Then again, I'm neither D@n nor you nor a contributor for this Forum, so I'm probably just putting words in people's mouths. Sorry if I've offended anybody. ~Natsu
  48. 1 point
    In the template, you can find a few relevant areas when it comes to customization: First, the place to put any parameters you want to add. //Users to add parameters here Second, the place to put any additional ports you want to add. For instance, if you wanted to connect LEDs to your IP. // Users to add ports here output [3:0] led, If you wanted to connect to switches. input [3:0] sw, If you want ports and/or parameters to the IP, you need to add them to the port maps of both <myip>_v1_0.v and <myip>_v1_0_S00_AXI_inst. Make sure to edit the instantiation of the "Axi Bus Interface S00_AXI" as well. Relevant code in myip_v1_0_S00_AXI: If you want to configure one of the register addresses to communicate from PL to PS, you will need to edit the synchronous process on lines 211-261 of this file. Comment out lines referring to the slv_reg# that you want to replace. If you want to change the name of the slv_reg#, make sure to replace it in lines 365-368 as well. The slave register can be replaced with a wire output of a verilog module you want to instantiate, for instance. This is key to getting communication set up: If you want a particular address to be written from the processor: use the slv_reg with the appropriate number (with 32 bit wide registers, slv_reg1 would be located at BASEADDR+4 when you are using Xil_Out32) in code added in the section at line 392 (Add user logic here). If you want a particular address to be read from the processor: replace all instances of that slave register's name when it appears on the right hand side of an assignment in the _S00_AXI file with your own signal. Comment out all instances where that slave register appears on the left hand side of an assignment. Do not touch any other predefined signals in either file, unless you really know what you are doing. You can basically do whatever you want in the Add user logic here area, as long as you keep in mind how your IP will be communicating with the rest of your design. AXI lets you communicate with the processor (one bit at a time), additional ports let you communicate with other IP, instantiated modules in the block design, and external ports, parameters let you reconfigure the IP while designing, so that you don't need to edit the IP again later (hopefully), and so that you can reuse it in different situations.
  49. 1 point
    To allow software developers to be able to easily get the computational benefits of FPGAs we created Hastlayer: it turns software written for the .NET platform into an equivalent (VHDL) hardware description. It does this while also handling everything in the background to allow the usage of the resulting hardware in the same way as the original software was run - basically where there was a function call there's still a function call but now it really executes on an FPGA, as logic hardware. Here's a demo video of how it works: And why do I post it here? You can also see from the above thumbnail that you can use Hastlayer with Nexys 4 DDR boards! Connecting the board to a host PC via USB as well as Ethernet is supported. You can even use multiple boards simultaneously if you use the latter. Do you own a Nexys 4 DDR? You can get access to Hastlayer, just ask! (And you can get access to it otherwise too!)
  50. 1 point
    lukeswr

    Adept library to use in visual .net c#

    I have an excellent example of interfacing with non-managed libraries using an internal sealed class. I have attached the file. I copied this foot print from another interface class regarding a USB interface. This example is nowhere near complete, but it provides the building block. using System; using System.IO; using System.Runtime.InteropServices; namespace Linear.common.lap.Digilent.Adept2 { /// <summary> /// This class library provides the 64-bit interface to the Digilent Inc. Adept2 dmgr library. /// </summary> internal sealed class StaticDmgr : IDisposable { // ReSharper disable InconsistentNaming /// <summary> /// The following value is passed to DmgrGetTransResult to specify /// wait until the transfer completes. /// </summary> public const UInt32 tmsWaitInfinite = 0xFFFFFFFF; // Handle to our DLL - used with GetProcAddress to load all of our functions private IntPtr hDMGR = IntPtr.Zero; // Declare pointers to each of the functions we are going to use in DMGR.DLL // These are assigned in our constructor and freed in our destructor. private readonly IntPtr pDmgrGetVersion = IntPtr.Zero; private readonly IntPtr pDmgrEnumDevices = IntPtr.Zero; private readonly IntPtr pDmgrGetDvc = IntPtr.Zero; private readonly IntPtr pDmgrIsEnumFinished = IntPtr.Zero; private readonly IntPtr pDmgrStopEnum = IntPtr.Zero; private readonly IntPtr pDmgrFreeDvcEnum = IntPtr.Zero; internal StaticDmgr() { // If DMGR.DLL is NOT loaded already, load it if (hDMGR == IntPtr.Zero) { // Load our DEPP.DLL library hDMGR = LoadLibrary(@"DMGR.DLL"); if (hDMGR == IntPtr.Zero) { // Failed to load our DEPP.DLL library from System32 or the application directory // Try the same directory that this Adept2 DLL is in hDMGR = LoadLibrary(@Path.GetDirectoryName(GetType().Assembly.Location) + "\\DMGR.DLL"); } } if (hDMGR == IntPtr.Zero) throw new ApplicationException("Cannot locate the driver's DMGR.DLL interface library."); // If we have succesfully loaded the library, get the function pointers set up // Set up our function pointers for use through our exported methods pDmgrGetVersion = GetProcAddress(hDMGR, "DmgrGetVersion"); pDmgrEnumDevices = GetProcAddress(hDMGR, "DmgrEnumDevices"); pDmgrGetDvc = GetProcAddress(hDMGR, "DmgrGetDvc"); pDmgrIsEnumFinished = GetProcAddress(hDMGR, "DmgrIsEnumFinished"); pDmgrStopEnum = GetProcAddress(hDMGR, "DmgrStopEnum"); pDmgrFreeDvcEnum = GetProcAddress(hDMGR, "DmgrFreeDvcEnum"); InitializeDelegates(); } private void InitializeDelegates() { if (pDmgrGetVersion == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrGetVersion."); if (pDmgrEnumDevices == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrEnumDevices."); if (pDmgrIsEnumFinished == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrIsEnumFinished."); if (pDmgrStopEnum == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrStopEnum."); if (pDmgrFreeDvcEnum == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrFreeDvcEnum."); DmgrGetVersion = (tDmgrGetVersion)Marshal.GetDelegateForFunctionPointer(pDmgrGetVersion, typeof(tDmgrGetVersion)); DmgrEnumDevices = (tDmgrEnumDevices)Marshal.GetDelegateForFunctionPointer(pDmgrEnumDevices, typeof(tDmgrEnumDevices)); DmgrGetDvc = (tDmgrGetDvc)Marshal.GetDelegateForFunctionPointer(pDmgrGetDvc, typeof(tDmgrGetDvc)); DmgrIsEnumFinished = (tDmgrIsEnumFinished)Marshal.GetDelegateForFunctionPointer(pDmgrIsEnumFinished, typeof(tDmgrIsEnumFinished)); DmgrStopEnum = (tDmgrStopEnum)Marshal.GetDelegateForFunctionPointer(pDmgrStopEnum, typeof(tDmgrStopEnum)); DmgrFreeDvcEnum = (tDmgrFreeDvcEnum)Marshal.GetDelegateForFunctionPointer(pDmgrFreeDvcEnum, typeof(tDmgrFreeDvcEnum)); } #region Instantiated Function Delegates internal tDmgrGetVersion DmgrGetVersion; internal tDmgrEnumDevices DmgrEnumDevices; internal tDmgrGetDvc DmgrGetDvc; internal tDmgrIsEnumFinished DmgrIsEnumFinished; internal tDmgrStopEnum DmgrStopEnum; internal tDmgrFreeDvcEnum DmgrFreeDvcEnum; #endregion #region IDisposable Methods /// <summary> /// Destructor for the D2XX class. /// </summary> ~StaticDmgr() { if (hDMGR != IntPtr.Zero) { // FreeLibrary here - we should only do this if we are completely finished FreeLibrary(hDMGR); hDMGR = IntPtr.Zero; } } public void Dispose() { if (hDMGR != IntPtr.Zero) { // FreeLibrary here - we should only do this if we are completely finished FreeLibrary(hDMGR); hDMGR = IntPtr.Zero; } } #endregion #region Marshalling Methods to Unmanaged DMGR /// <summary> /// Built-in Windows API functions to allow us to dynamically load our own DLL. /// Will allow us to use old versions of the DLL that do not have all of these functions available. /// </summary> [DllImport("kernel32.dll")] private static extern IntPtr LoadLibrary(string dllToLoad); [DllImport("kernel32.dll")] private static extern IntPtr GetProcAddress(IntPtr hModule, string procedureName); [DllImport("kernel32.dll")] private static extern bool FreeLibrary(IntPtr hModule); // Definitions for DMGR functions [UnmanagedFunctionPointer(CallingConvention.StdCall)] internal delegate int tDmgrGetVersion(byte[] szVersion); //OPEN & CLOSE functions internal delegate int tDmgrOpen(ref int phif, byte[] szSel); internal delegate int tDmgrOpenEx(ref int phif, byte[] szSel, int dtpTable, int dtpDisc); internal delegate int tDmgrClose(int hif); //ENUMERATION functions internal delegate int tDmgrEnumDevices(ref int pcdvc); //internal delegate int tDmgrEnumDevicesEx(ref int pcdvc, int dtpTable, int dtpDisc, int dinfoSel); //internal delegate int tDmgrStartEnum(ref int pcdvc); internal delegate int tDmgrIsEnumFinished(); internal delegate int tDmgrStopEnum(); //internal delegate int tDmgrGetEnumCount(ref int pcdvc); internal delegate int tDmgrGetDvc(int pcdvc, byte [] dvc); internal delegate int tDmgrFreeDvcEnum(); #endregion } }