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Showing content with the highest reputation on 06/10/17 in all areas

  1. 1 point

    This darn simulator...

    Dear @Tickstart I might be too late to bring this but hope not. 1. It is typical to use switch - case construct for designing finite state machines. Xilinx even included synthesizable language templates. When you are in the VHDL design window you can see it the Vivado help (click light bulb icon), see the snapshot of it. Using flip-flop seems to be the hardest way to me, however, it is a matter of choice. 2. There is a Digilent project called Active Power Meter reference design with an example of SPI using FSM posted here I would suggest to simulate it for better understanding. Good luck!
  2. 1 point

    PMODAD5 bipolar mode

    Hey @SkeptoLogic, Testing the configuration and mode settings you provided, I am getting similar outputs to what you stated you were reading (if I am understanding your post correctly). I am currently working on a library for the pmodAD5, so as I finish it up I should be able to give you some more definitive answers. In my recent experience with the AD5 though, and having read through the datasheet as well, I too have been having some difficulty deciphering differences between certain actual outputs and my expectations. Sorry for not having a whole lot of info for you at the moment, but I should have something more next week as I look into this further (and hopefully a library to share). Regards, Nate
  3. 1 point
    Final Report merged (2).pdf
  4. 1 point
    Hello Digilent Community, I am now officially done with my term and I want to share what my experience was like, as per @[email protected]'s question. I would like to attach our final report here (we got an 86 on it, so please understand that it won't be the rest report haha). It was quite rushed since my partner and I were travelling during the last few days before the turn in date and the code in the appendices are quite scuffed. Vivado won't print PDFs in color and I haven't figured out how to fix the sizing or formatting, which is really inconvenient because it looks bad and not easy to read. If anyone has any questions about the code or writing at all, please feel free to private message me or just respond on this forum by tagging me! The idea behind how we wanted it to work, what it actually became, the struggles we had, and our theory on why it did not work again are included in the report along with our VHDL files and some testbench images. If they end up being too small of pictures, just let me know and i can attach the original ones here so it's easier to see. Thank you all for your help and consideration; it means to the world to me now and it meant the world to me before while I was working on this project.