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  1. 5 points
    attila

    WaveForms beta download

    3.11.6 digilent.waveforms_beta_v3.11.6_64bit.exe digilent.waveforms_beta_v3.11.6.dmg digilent.waveforms_beta_3.11.6_amd64.deb digilent.waveforms_beta_3.11.6.x86_64.rpm Added: - Protocol - UART Spy - Max Lines option: log limit to prevent application slowdown - Line Wrap option - tooltips for UI controls listing Script access path - application and script Font options - dark theme support for Script 3.11.5 digilent.waveforms_beta_v3.11.5_64bit.exe Added: - Script open/save text file - application argument: -script myscript.txt/js Fixed: - warnings at low record rates 3.11.4 digilent.waveforms_beta_v3.11.4_64bit.exe Added: - Scope: - set/reset zero offset in each channel option - precision option for measurements Fixed: - Script: access to traces and channels from Instrument.Export - unit conversions V to Ṽ, A to à - I2S 32 bit data 3.11.3 digilent.waveforms_beta_v3.11.3_64bit.exe digilent.waveforms_beta_3.11.3_amd64.deb digilent.waveforms_beta_3.11.3.x86_64.rpm Fixes 3.11.2 digilent.waveforms_beta_v3.11.2_64bit.exe digilent.waveforms_beta_3.11.2_amd64.deb digilent.waveforms_beta_3.11.2.x86_64.rpm Added: - Spectrum, Network and Impedance Analyzer store time data when this view is open Fixed: - runscript argument - loading of docked views geometry 3.11.1 digilent.waveforms_beta_v3.11.1_64bit.exe digilent.waveforms_beta_3.11.1_amd64.deb digilent.waveforms_beta_3.11.1.x86_64.rpm Added: - Scope: out of range warning in measurements - Protocol/UART: - support up to 32bit/word - TX/RX format: text, binary, decimal, hex - Wheel Direction option - Logic Analyzer: option to swap previous/next events - Spectrum Analyzer: allowing higher number of BINs for CZT 3.10.7 digilent.waveforms_beta_v3.10.7_64bit.exe Added: - Spectrum: logarithmic magnitude scale for voltage units - Protocol: datetime stamp for SPI/I2C Spy Fixes 3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom mathematic channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Netowrk Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.
  2. 3 points
    zygot

    A UART Based Debugger Tool

    Here's a utility for debugging and testing your code in hardware and uses any IO pin to send an ASCII representation of any signal through a hardware UART interface. If you don't have a UART on you FPGA board there are TTL USB UART breakout boards and cables that allow any spare IO pin to become a UART interface. This code is functionally the same as one recently released by Hamster but developed independently for the Fast Data Interface project. I recommend comparing the different coding styles. I decided to release this as a separate project as there are likely more people interested in this one that the other. This project contains test bench code. UartDebuggerR3.zip
  3. 3 points
    Ciprian

    Digital Twin

    Hi @Kris Persyn, It depends on how you manage your resources, driving immersive visuals on a HDMI display can be done in multiple ways at different resolutions, some are PL taxing others are DDR taxing; you could generate entire frame buffers in PL or PS or you could find a optimal algorithm to change just the previous frame or you could allocate a high number of frame buffers and then run them in a loop. It also depends on how math lab synthesizes the IP you will need to add to your design. If you design your project properly and don't aim for a resolution higher more 720p( I'm being conservative, we managed to drive the HDMI at 1080p with processing filters without a problem) I think it should be enough for what you want to do, resource wise. My suggestion, download and install Vivado, download and install the board files, create and implement your project look at the resource consumption and then buy a board. - Ciprian
  4. 3 points
    In your constraint file, the ddc pins have lowercase "ddc_scl_io" and "ddc_sda_io". Your block design has the port in uppercase "DDC". The case must match. Try editing your constraint file to have "DDC_scl_io" and "DDC_sda_io".
  5. 3 points
    jpeyron

    pmod wifi

    Hi @harika, I believe the HTML web page error is related to the materials on the SD card. 1) Please attach a screen shot of the contents of the Sd card you are using. 2) Please follow the YouTube video here from about 6 minutes and 28 seconds on for how to set up the HTTP server project. Make sure to update the login an password for the router/modem you are using. thank you, Jon
  6. 3 points
    @thobie, the bare-metal purchase option for the Zybo was done to enable a lower price point for those who do not require the accessories. For the rest of our customers, adding the Accessory Kit is recommended during the purchase process. You are not the first and the last to complain about version compatibility. It is economically unfeasible for us to update all support projects, IP and support packages provided for free four times per year for each Vivado version. Instead we made a commitment to consider the last Vivado release in each year stable and do a once-a-year update cycle. In that regard, 2017.4 is the version we are upgrading projects to. There is a question whether OOB designs should be updated at all, or kept at the version which generated the binary image shipped with the board. The board presets are not versioned for Vivado (no version-specific releases in our git repo), because these should be forward-compatible with Vivado versions. The critical warning itself related to CK-to-DQS delays being negative appears starting with 2017.4. The negative values are due to CK trace being shorter than any of the four DQS traces. In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Zybo was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Zybos shipped to customers are functionally tested and pass the DDR3 calibration process. Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. Since these delays are board-dependent, we would need to re-design the board to make the delay positive. This is impossible with the current form-factor. Another option would be modifying the board preset file and forcing a zero value instead of the actual delay. The tools seem to be using zero anyway for calibration. This will have to be thoroughly verified first.
  7. 3 points
    Hello, I've posted the next part in my FPGA graphics series using the Arty + VGA Pmod or Basys 3. It shows you how to make use of double buffering to animate sprites using simple Verilog. https://timetoexplore.net/blog/arty-fpga-vga-verilog-03 Feedback very welcome, Will PS. I'll add the source to GitHub shortly.
  8. 3 points
    An FPGA can be a useful "swiss army knife", but all the nice features aren't easily accessible. Enter "LabToy": A batteries-included collection of utilities, just double-click and go. As the name implies, this isn't meant to compete against "real" test equipment. The main selling point is like a pocket knife - this fits into a shirt pocket and the power tools don't. And speaking of "selling points", it's free to use. So what do we have here: - Digital data: Shows the input state of all pins - Analog data: Readings from the two ADCs, up to about 700 ksps sustained (XADC "simultaneous sampling" mode, phase-accurate between channels) - Streaming data logger: Both analog and digital data can be written to a .vcd file, to be shown in gtkwave. There is no limit to the capture length. - Analog signal generator: 8 fully independent channels, sine, square wave, the usual suspects. Well, the DACs won't win any audiophile awards, but they are usable. - "Programmable" digital LED mode: Configurable pulse width to suppress short glitches, or edge detect with a built-in pulse generator to highlight them. - Analog LED mode: Shows the input value of the ADC in real time Some screenshots: 1k sine / cosine from DAC jumpered to ADC (in gtkwave) The digital signal is the generator's sync output that can be recorded as a digital input. Realtime display of the inputs. With pocket knives in mind ("this button will unlock the large blade, allowing it to be manually returned to its folded position") I decided to keep the screen uncluttered and put descriptions into tooltips. The large displays are the average voltage readings from the ADC. The smaller ones show the digital inputs in groups of four. Generator controls (frequency, minimum voltage, maximum voltage, phase). The voltage scaling is a bit unusual (typically there is "AC magnitude" and "DC offset") but I chose this approach because it shows clearly the limitations of the 0..3.3V output range. Most people will probably leave all this at the default values for a full-scale signal. Data capture Example: The output in gtkwave after I touched a jumper cable to the digital inputs on the DIL connector. +++ DO NOT USE THE +5V OUTPUT P24 FOR THIS KIND OF TEST +++ (3.3 V is available on the PMOD connector, bottom row) The red "undefined" marks flag the first input in an 8-bit group. In this example, they aren't too meaningful, but they can alert me to the fact that no data events have been observed yet. LED control The two numbers give the number of consecutive 1 or 0 samples (at 125 MHz) before a signal change is propagated to the LED. E.g. put 125 million there and it'll take one second after changing the input state for the LED to light / go dark. Those can be used interactively to study an unknown signal. "Level": no further processing ("level" mode and 1 / 1 sample counts is equivalent to directly connecting the LED to the physical input) "Edge" mode generates a brief pulse on signal changes, the LED is dark otherwise. "Invert" flips the input right next to the pin (0 becomes 1, black becomes white and man gets himself killed on the next zebra crossing -DA). How to get it: The file is attached: labToy0v1_beta.exe The installer unpacks a single .exe. Happy hacking! Requirements: Windows 64 bit (!) .NET 4.5 FTDI libraries CMOD A7 35 T (not 15 T). Warnings: Direct access to digital IO pins is an inherently dangerous activity. "PROVIDED WITHOUT WARRANTY OF ANY KIND" means Just That. And beware of the +5V pin. PS: If you try it, kindly let me know whether it works, or what goes wrong.
  9. 3 points
    attila

    Using script with Spectrum on AD2

    Hi @tomtektest, @abzza With WaveForms Script THD and other measurement logging and plotting can be automated, like this: function doTHD(){ var rgTHD = [] var rgFreq = [] for(var idx = 1; idx <= 100; idx++){ Wavegen1.Channel1.Simple.Frequency.value = 1000*idx Wavegen1.run() // start AWG wait(0.01) // settle time for the external circuit, expressed in seconds Spectrum1.Frequency.Stop.value = 20*Wavegen1.Channel1.Simple.Frequency.value // adjust analyzer stop frequency Spectrum1.single() // start acquisition if(!Spectrum1.wait()){ // wait to finish return; } rgFreq.push(Spectrum1.Trace1.measureFreq("FF")) rgTHD.push(Spectrum1.Trace1.measure("THD")) } Wavegen1.stop() print(rgFreq, rgTHD) // print data for copy paste // draw in plot1, View / Add plot plot1.X.Units.text = "Hz" plot1.Y1.Units.text = "dBc" plot1.X.data = rgFreq plot1.Y1.data = rgTHD } doTHD();
  10. 3 points
    zygot

    Rants about FPGA tool chain(s)

    @D@n , Here's a secret; I'm whispering because this is just between you and me: At places where they do a lot of quality FPGA development work no one ever brings up a GUI for anything. All of the toolchain invocation is done using Perl and TCL/TKL. Shhhh. Don't tell anyone....
  11. 3 points
    A few reasons are... a - The introduction of logic hazards can cause glitches : https://en.wikipedia.org/wiki/Hazard_(logic) b - Routing of clocks is very complex - It is hard to ensure that the same clock edge appears all over the FPGA at almost exactly the same time. Sometimes this is achieved with 'slight of hand' (e.g. using a on-chip PLL to advance phase of the clock, so that by the time it reaches the edge of the chip is in back phase with the original signal). Low-skew paths also exist, but are restricted to small areas of the FPGA, and the clock has to be connected to the correct pin to be placed and routed correctly. c - FPGAs and their tools are designed to behave predictably under the "synchronous digital design" paradigm (something like https://hps.hs-regensburg.de/scm39115/homepage/education/courses/red/2_SynchronousDigitalCircuitDesignRules.pdf). If you work outside the paradigm you will be fighting against the tools and their assumptions. d - There is almost nothing that you are unable to code in an FPGA friendly way, but there are infinitely many ways to write FPGA-hostile code. If you want your FPGA to place nice with you, you have to play nice with it. So you can either add an RC filter to debounce you switch, or you can sample it using a reliable clock.
  12. 3 points
    D@n

    Just for fun: Frequency Resolution challenge

    Hello everybody! Since I was sharing this image with others, I thought I'd share it here at Digilent as well. The attached image shows the frequency response of several FFT windows, including the well-known rectangle and Hanning windows. The blue window is one I've put together, but haven't shared the FPGA source code used to implement it. I challenge anyone to do better. Oh, and one other comment ... all but the Hanning window can be used in an invertible FFT process. Dan
  13. 3 points
    Tempest2k8

    OpenScope Mechanical STL Files

    Printed out on the Form Labs at my local TechShop.
  14. 3 points
    jpeyron

    Cmod A7 35T GPIO demo Error

    Hi @coloradosensors, I just generated bitstream on this project in Vivado 2015.4. You need to right click on the clocking wizard and remove it. Then under project manager click on ip catalog and re-add the clocking wizard with default settings. This will fix your issues with using an older version of Vivado for this project. cheers, Jon
  15. 3 points
    D@n

    Lots of fun UART testing code

    Hello Digilent Community! I just finished putting the finishing touches on a UART demonstration project that you can find here. The project was originally intended to share a C++ class that could work with Verilator to prove that anyone's UART implementation was working. However, after I got into it, I realized the project had a lot of value that others might appreciate. As an example, consider this post by @martin16. Had he used any of the testing mechanisms listed below, he might have known which side of the RS232 port he was working with was at fault. The core contains a complete implementation of both a transmit and receive UART encoder/decoder. These can be easily taken from my project and placed within your own. (Subject, of course, to the limits of the GPL v3) The core also contains a (fairly) generic FIFO implementation. For those wondering how to implement a FIFO, you may find this valuable as well. For those who would rather interact with a serial port over a bus, such as the wishbone bus, there are two approaches within the project that can be used to hook it up to a wishbone bus. One can be used within a larger wishbone slave module, the second as a standalone module. Both are Wishbone B4 compliant, and both use the pipeline mode--allowing you to read/write multiple values on consecutive clocks from/to the controller. Of course, this only really makes sense when using the FIFO. Those might be valuable enough on their own, but you can probably find without too much additional work other implementations of the above. Therefore this project includes some even more valuable files: It includes a series of test programs/configurations that can be used to determine if the hardware on your board is working properly. If you are like me, you've struggled every time you've tried to get a serial port working on a new board. Should you connect your output to the TX or to the RX line? Do you have the UART set up properly, at the right baud rate? Can you handle more than just single values at once? How fast can you transmit/receive? To help you answer these questions, the project file contains the following test configurations: Hello World: You know, that old fashioned hello world program? I would recommend trying this program on your board after you can blink an LED at your favorite rate, or equivalently after you know that your clock works. This particular project is so simple that it depends upon only the clock input and the UART transmit output. Getting this program running on your board will demonstrate that you understand your clock, and that you can modify your I/O constraint file properly, and that you know how to connect a terminal program to your board in order to observe the results. Line Test: Once you've got a hello world program running, so that you know the output UART pin works, then it is time to test the input UART pin. This is the purpose of the line test testing program. It works by reading a line of data (either until a newline or 80--characters), and then dumping that line to the output. (Don't forget to turn off hardware flow control, and be aware of the differences between a new line and a carriage return!) SpeechFifo: Finally, there's a program that can be used to test the FIFO capabilities found within the wishbone UART peripheral. This program uses the FIFO capability to make certain the transmitter stays fully loaded for over a thousand characters of output bytes. (No, this isn't computer speech generation, but rather a computer dumping a Abraham Lincoln's Gettysburg Address across the UART port.) Each of these configurations has a corresponding Verilator simulation file associated with it, allowing you to simulate the functionality within them as part of Verilator. The project includes, like I mentioned above, a C++ class that can be used to determine if your own UART is transmitting correctly under a Verilator simuation. This class can also be used generate UART signaling in order to test if your RTL can receive it properly. (See the line test C++ harness discussed below for an example of this.) As complements to each of the testing configurations above, the project contains C++ files to drive each of those within a Verilator context. Some unique features include: The Line Test C++ test harness automatically generates a linetest.vcd file that can be used together with GTKwave to study how the core works. Further, it can be run in either an interactive or an automated mode. The Speech Test C++ test harness can be used in an automated mode, or with the -i switch in a more interactive mode. In this latter mode, the speech test program generates a speechtrace.vcd file that can be used with GTK wave to understand how the UART transmitter, FIFO, the wishbone bus decoder, or even the test harness itself. I hope you find these as valuable as I have. Please feel free to post any questions or comments you might have about this project below. Dan
  16. 3 points
    LariSan

    Birth of an OpenScope!

    We got a series of photos of the OpenScope going through the manufacturing line. Unfortunately, Kickstarter didn't allow me to load all of them onto the update.
  17. 3 points
    D@n

    Nexys 4 DDR

    @gnicholls, Wow, what a good and thorough question. You've hit the nail on the head, and you are asking something a lot of users are asking. So in answer, may I reply, Welcome to the wonderful world of FPGA design! DDR memory is hard. I mean, really hard. I tried for about two solid months to get a DDR3 memory up and running, and eventually moved on because it was taking too much time to do. You can still find the project here, though--and I still hope to return to it--eventually. Xilinx has written a variety of App notes describing how they've gone about creating their reference solution. For 7-series devices, you can find their note here--but it just doesn't tell you much. I've found the most useful information in their note from a couple generations back, found here for a Virtex-5. Bottom line: it's *really* hard--most people only use the reference solution, and then make the reference solution work for their design. I love the examples found at fpga4fun.com. They tend to work through many of the basic I/Os that FPGAs need to work with, and how to build controllers for each of them. Another useful website is Asic-World--it's just not one I've ever gotten into. Xilinx has tried to make your problem easier with their platform studio and now its Vivado replacement--allowing you to connect via point and click various different Xilinx components together to make one of many (fairly) pre-canned designs. Many of the Digilent based "tutorials" or "examples" are of this type. I personally find them wanting, for many reasons: They are "too easy"--offering you no insight for how they are accomplished internally. They are so much of a black box that you cannot examine what they did or how they did it in order to modify it, debug it, or even learn from it. It can be difficult to integrate your own work with their components. They are all focused on how to use someone else's components, but offer little in the way of teaching you how to build your own. In the end, they leave you stuck with Xilinx solutions. Any components you create/develop will only ever work with Xilinx. This leaves you forever wedded to the Xilinx platform, or forced to relearn all you have learned. Verilog (and <gasp> even VHDL) is a better language than that--capable of doing a lot more. And if that's not enough, your design that works with one version of Vivado may well break when the next one comes out because ... they changed something. (This is an ongoing problem, and a thorn in Digilent's side--suggestions are always welcome.) I have personally been trying to work to create somewhat of a solution to your problem, but I'll admit my own designs are perhaps far from the professor's materials that you are looking for. You can find many of my Verilog designs on github here. A recent design I've put together for both beginners and more experienced types alike can be found here. It contains examples of how to create a serial port, both transmitter and receiver, together with some top level designs that use such a port. As the task of figuring out which pin is which on any board is fairly common--even among experienced users, these offer examples you can work with to make sure you have your serial port working. My efforts have gone so far as to even build my own CPU, flash controller(s), SD-card controller, GPS controller, real-time clock, 7-segment controller, FFT, VGA controller, etc. I mean, why when you buy a board would you only learn to work with some of it, right? You can find a fairly complete design here, using a CMod-S6, that places a CPU onto the S6 with a minimal multi-tasking "operating system". I'm also working on a more complicated design for the Arty here--this one uses the Xilinx generated MIG DDR3 SDRAM, such as you have on your Nexys 4 DDR. This design is currently somewhat on hold, as I am trying to update the CPU within it to a more mainstream CPU that will even support the C-library. (Today's success: I managed to get newlib to compile for it! This is after updating the assembler, linker, GCC compiler backend, etc.) If you are a hard-core VHDL type, Xess.com has put together a fascinating library of VHDL routines to demo how to use their boards. To my knowledge though, the tutorial information within their libraries is ... a bit harder to follow than the simple point and click designs Xilinx peddles. One of the things I've noticed about many (most, all?) of the more complicated FPGA designs I've come across is that they all depend upon some form of internal bus by which things can be connected. Once you get past learning about how to build the simple peripherals fpga4fun wishes to teach you, you're next step is really to learn about that bus structure. Why? If for no other reason than memories seem to be best accessed via a bus, so anything using a DDR type of memory tends to send its requests over a bus. This can easily become a bottleneck to your design, but ... it sort of comes with the territory. You can build other memories and distribute them throughout your FPGA, but the amount of block RAM memory you will get within any FPGA tends to be ... never enough. Hence you are often stuck with the external memory chip(s). Xilinx uses the AXI bus protocol. You can find the specification for it here. I haven't found any good tutorials on how to use it, but there's a way you can get Vivado to generate a sample AXI-lite design that you can interface with. (I can google it if you are interested--I just don't have it at my fingertips.) I've personally used the Wishbone Bus protocol, version B4, pipelined mode. Many others use version B3. I find that I can transfer data 3x faster using B4. To get from the Wishbone Bus to a DDR memory, controlled via Xilinx's Memory Interface Generated AXI controller, I built a wishbone-AXI bridge. Others of these also exist. There's an open source package manger out there called fusesoc which was designed to facilitate composing solutions from many different FPGA components together. In particular, the OpenRISC team has put a lot of work into making sure their CPU's, peripherals, and board designs can be built using this package manager. (These tend to connect to each other via the wishbone B3 standard.) If you dig into this, you can probably find many, many examples of working peripherals for various boards--although that community does tend to focus more on the Altera boards than the Xilinx boards, and Verilog more than VHDL. So ... when I build a new design, how do I do it? For every board of Digilent's that I have bought, I start with the reference page, look up the schematic to see how the components are connected, and then google the part numbers on the schematic. Those will contain the instructions you need to access the various chips on your board. They are usually where things pick up next after you leave the canned tutorials and examples. I hope I haven't overwhelmed you, but really ... where you go next is up to you. What would you like to do? Dan P.S.: My favorite description of RTL design for those who know nothing about FPGA's is, "Infuriatingly complex in its simplicity." Everything you do will be simple--like the clock divider. But too many of these very "simple" components can become so complex that it very quickly gets under your skin.
  18. 3 points
    hamster

    Welcome!

    My name is Mike, and I've developed a bit of an obsession with FPGAs. You might be able to find some project ideas or inspiration on my WIki at http://hamsterworks.co.nz/mediawiki/index.php/FPGA_Projects I'm always happy to talk FPGAs, so feel free to drop me an email sometime
  19. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  20. 2 points
    True. Zygot believes that making you work for knowledge is kinder than giving you solutions that can be used to mindlessly resolve your problem of the hour.... it's just a different philosophical bent...
  21. 2 points
    kwilber

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  22. 2 points
    Hi, Abdul, Here are my notes/recommendations: 1. Open your block diagram in Vivado where you created BRAM configuration and then check the address editor. You should see whether the BRAM address was assigned. If you find assigned see axi_bram_ctrl_0 OffsetAdress and the Range then the BRAM was created and mapped to the memory. 2. Writing and reading from BRAM requires a clock signal. Check Xilinx templates for BRAM which you can access inside the Vivado. I am not sure that the code you've used to write into BRAM does anything. 3. You don't use an absolute address in your HDL when BRAM created in Vivado. Vivado maps the address 0x4000_0000 to 0. So you can start from the address 0 and it will be the lowest address of the BRAM. If your don't use Vivado then you will need to define your block in HDL and include addresses, and many other parameters. 4. The C-code in SDK should use BRAM address from the file parameters.h. You just need to use XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR as the begining of the BRAM address space. 5. You can treat BRAM as RAM meaning that all read/write operators are the same. For example you can copy BRAM content into the RAM: for(i = 0 ; i < BRAM_SIZE ; i++) *(destination + i) = *(source + i); where source = XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR Disclaimer: always read documentation, whatever you find on Internet might not be correct. Good luck!
  23. 2 points
    >> having about 60uF of ceramic decoupling goodness Maybe it's even more a question of ESR than capacitance. Ceramic if money doesn't matter (e.g. Mouser: 22 µF: €4..6). The typical solution are staggered capacitors, with a quick look at the datasheet for the self resonance frequency in the impedance curve. I do this for RF (try to get a quality short at n GHz...) but if I had to make a blind guess, I'd use two orders of magnitude, e.g. 10 µ, 100n, 1n and with a nervous glance at my Voodoo doll, 10p. The CMOD A7 is reported quite frequently (possibly because it's one of the most attractive boards) but I can tell that I've run into the same issues with FTDI's reference module for the 2232H. The chip just shuts down if it doesn't like what it sees on VCC. It took a long Friday night in the lab to prove without doubt that our system is sensitive to USB cables. We changed the design and shipped with non-detachable cable. Zero issues so far.
  24. 2 points
    xc6lx45

    Diving in

    ... a slightly longer answer, if anybody is interested (analog mixing with square wave LO): One way is to look at the Fourier series of the square wave as a sum of sines at frequencies f, 3f, 5f, 7f, ... and to a lesser extent 2f, 4f, 6f from implementation imperfections. Then think of the mixer as linear multiplier, and use superposition (the distributive property of multiplication) for a*(b3+b5+b7+...) = a*b3+a*b5+a*b7+... Hint, if anybody wants to formally go through the math, it gets much less messy with cos(x) = (exp(ix)+exp(-ix))/2 aka DeMoivre. So you really get multiple frequency translations instead of one. What remains to be done is to manage the input signal energy at those frequencies I don't want, with a filter or narrow-band antenna. In the digital world, you'd always use a sine wave.
  25. 2 points
    awang735

    PMOD DA1 to zedboard

    Nevermind, i downloaded the digilent board files from https://reference.digilentinc.com/learn/software/tutorials/vivado-board-files/start?redirect=1 and was able to connect the pmod ip via the board tab in ip integrator like it says in the walkthrough
  26. 2 points
    zygot

    Beginner DSP Projects

    Yes Dan he certainly would agree with your advice. Test, verify, test, verify. Let it be your mantra. Test and verify the main result that you are looking for. Test and verify all of the component parts ( particularly in logic ) in case you want to reuse any modules or components. Test and verify corner cases. Test and verify consistency of results between all of the implementations. For the logic implementation there will be more subtle and complicated aspects to consider and test for. Assume nothing. If all of this doesn't sound like fun ( I'm taking the long view by using that word) ... perhaps consider a different way to spend your free time. Oh, and I forgot to mention the most important part. Don't do it for self-defense. You can learn a lot more during the test and verification stages... you know, the part where most people have gone on to other things assuming that everything works, than you can learn during the basic design processes. Testing and verification generally requires another level of awareness to issues not obvious in the original conceptual stages. That's my experience.
  27. 2 points
    @tnet, Let me try to add to what @xc6lx45 just said. I've seen several design processes. The typical student design process is This ends up quite confusing for the student. What @xc6lx45 is recommending would look more like, I've argued in the past that this approach only makes sense if you have a means of properly viewing what's going on within the FPGA. If you have no way of viewing the logic within an FPGA, then I'll argue that should be your first task. You can read about the problem that results when you don't have that ability here. This process, however, will not work for ASIC flows. (FPGA flows typically teach students the design methods that they'll get paid more for when working for ASIC companies ... ) In an ASIC flow, the design *must* work right the first time (if you want to keep your job). There's a *HEAVY* dependence on simulation and so forth. Broken designs aren't allowed by the boss to go to the next step. My own design process has morphed a bit since I first wrote the article on this topic. I've now picked up formal methods as a means of building designs, using the free and open source tool yosys with SymbiYosys as the driver. With every new bug I find using them, I get hooked all the more. As a result, my new development approach for something like this would be: Scribble out some code Add a property package, like the one for the wishbone bus. (I also have packages for Avalon and AXI available for sale, at least until I blog about them and then they will be public) Add some other ad-hoc assertions (or assumptions about inputs) based upon my own estimation of my code Apply the formal tools View the VCD waveform in gtkwave. Compare it to the trace I'm trying to match. Create a cover property once the tools stop producing failing traces. Lather rinse repeat until the code matches Create a simulation component for the hardware I am attempting to interact with Create a design including this component, and test via simulation At this point ... the yellow figure above now applies again. You can read my ramblings on how this works here if you'd like. Hopefully that helps, if not then I've just rambled on for longer than @xc6lx45! Dan
  28. 2 points
    attila

    Analog Discovery 2 vs Raspberry Pi 3

    Hi @Phil_D @rprr The problem is that the USB IN packets/bytes are randomly lost/altered. I tried various kernel options, limiting the USB transfer rates but had no luck. The data corruption reduced from one in 1-60 seconds to one in 10-60 minutes, which it is still not good... It seems that the root of the problem is in the low level FTDI library, kernel or USB modules, or between them... The Analog Discovery is working fine with other SOCs but not with the RPi. I also notice issue with the USB keyboard I use with the RPi, time to time key presses are not received. You can find many similar RPi issues on the net: https://www.raspberrypi.org/forums/viewtopic.php?f=28&amp;t=5249&amp;sid=8839659cb92b7475fa196b2fad775d9f&amp;start=250 http://www.ftdicommunity.com/index.php?topic=40.0
  29. 2 points
    sage

    Zybo board repair

    Thanks @jpeyron. I am tempted to short R281 and power it though usb to check if it would work before i order the fuse. any suggestions. Ok I couldn't wait so I shorted the fuse and the PGOOD light came on.I haven't carried out any further test. I will wait until the fuse arrives. Thanks once again. Asim
  30. 2 points
    @Riteshkakkar, That's a much longer topic, and well beyond the bounds of this forum. While you may find some folks here who have worked on satellites built for radio communication, the full topic of how to do so is ... typically beyond the ability of any one individual. You should also know that the space environment isn't very friendly to computer chips. Unlike the earth where items can be electrically connected to ground, satellites in space have no solid ground. The space environment is known for accumulating charged particles on satellites until they experience "lightning" from one side of the satellite to the other. It's also known for tiny particles of radioactive energy that can enter into a circuit and toggle bits within an algorithm. Building chips and algorithms to operate successfully in this environment is a study in and of itself. Most chips, FPGAs included, can't handle this environment. It usually takes several years of working with a particular chip design before that design can be "space qualified". In the process, the chip becomes quite out of date. As a result, the electrical technology launched into space tends to lack what is on the earth by several years. Dan
  31. 2 points
    Hi @Tickstart, Since your question was not directly related one of the Digilent FPGA boards, I have moved it to a different section of the Forum to hopefully produce less confusion for other readers. As for my personal perspective, I'm in a bit of an odd spot since I have a degree in chemical engineering rather than EE/CS/CompE, yet here I am helping answer questions on all of those things, meaning I don't have a lot (i.e. any) formal education with HDL design. But like Dan hinted at, I'd like to make sure that the people to be hired can "engineer" their way through a problem, not just hope that a single approach works for everything. Thanks, JColvin
  32. 2 points
    JColvin

    Query on schematic of CRII board

    Hi @Arvind Gupta, I believe that header just provides an alternate location to program the board. You'll note the data signals also tie in to the JTAG header J8. Thanks, JColvin
  33. 2 points
    morsucci

    Just Memory

    @deppenkaiser It is true that you can use /dev/mem and uio drivers to accomplish the same functionality. However, It is almost always a better idea to use uio as a opposed to /dev/mem Here is why: using /dev/mem directly opens your system up to security risks. You could be potentially accessing memory that can be harmful to your system. Additionally, other people may be able to exploit this to access memory that they would otherwise not be able to access. UIO provides kernel interrupt functionality. That is: UIO drivers can register interrupts with the kernel and the kernel can recognize when an interrupt has occurred and carry out the assigned task. Currently, the only way you would do this using /dev/mem is through polling of an interrupt register. Polling usually is not always the best approach, especially when you are trying to catch interrupts from FPGA hardware. Regards, Mitchell
  34. 2 points
    Hi @skakon, I have sent you a PM about this. Thanks, JColvin
  35. 2 points
    attila

    WaveForms 3.6.8 release

    Dear All, The new software version can be downloaded from the following page: https://reference.digilentinc.com/waveforms3 The changelog is available here: https://reference.digilentinc.com/reference/software/waveforms/waveforms-3/change-logs/3-6-8 See this blog for more details: https://blog.digilentinc.com/software-update-waveforms-3-6-8/ Please let us know if you have any observation. Thank you, Attila
  36. 2 points
    D@n

    Communication using pmod

    @jpeyron, @aksaltaaf, Why not implement a simple wired SPI protocol between the two boards? No PmodBT required, only a couple of wires required? Dan
  37. 2 points
    Although I flaunt here with other people's feathers it seemed to me a nice topic for the forum. I love practical examples for the Analog Discovery 2. I think this mix of old school technology with modern technology is fascinating, don't you think so? If you don't want this on the forum feel free to throw it off with confidence. Greetings, Hans
  38. 2 points
    Hi, I haven't looked at the board's specs, but you can find examples at https://github.com/hamsternz/ArtyEtherentTX (100BaseT on the Arty board) https://github.com/hamsternz/FPGA_GigabitTx (1000BaseT on the Nexys Video board). They should be helpful to you.
  39. 2 points
    attila

    Using script with Spectrum on AD2

    Hi @abzza @tomtektest With WF 3.6.8 you can access Spectrum measurements, like: print(Spectrum1.Trace1.measureFreq("FF")+" Hz") // fundamental frequency print(Spectrum1.Trace1.measure("FF")+" dBV") // magnitude print(Spectrum1.Trace1.measure("THD")+" dBc") // total harmonic distortion
  40. 2 points
    @Sam_a Should be fixed this time. Thanks for your patience, Arthur
  41. 2 points
    hamster

    Combination lock.

    A while ago there was a thread about writing a 'combination lock' design for an FPGA board. I finally got around to updating my Wiki with the design: http://hamsterworks.co.nz/mediawiki/index.php/Combination_Lock A short video of it in action is here:
  42. 2 points
    hamster

    MMCM dynamic clocking

    Hey, something else I just saw when reading the clocking guide was: MMCM Counter Cascading The CLKOUT6 divider (counter) can be cascaded with the CLKOUT4 divider. This provides a capability to have an output divider that is larger than 128. CLKOUT6 feeds the input of the CLKOUT4 divider. There is a static phase offset between the output of the cascaded divider and all other output dividers. And: CLKOUT4_CASCADE : Cascades the output divider (counter) CLKOUT6 into the input of the CLKOUT4 divider for an output clock divider that is greater than 128, effectively providing a total divide value of 16,384. So that can divide a 600 MHz VCO down to 36.6 kHz.
  43. 2 points
    The trick is your code does not need to infer a block memory generator. It will actually need to explicitly implement the block memory generator INTERFACE. This is because the block memory generator is already being instantiated in the block diagram. You will need to design a state machine in VHDL that properly implements the interface. For a description of the signals (en, we, addr, etc.) you should refer to the block memory generator Product Guide. You can find the guide by double clicking the block memory generator IP and selecting Documentation in the upper left corner. The end goal will be to create a custom IP core that contains this custom VHDL. Since you do not have an AXI interface on your core, this should be pretty easy. I believe you can just create a new project that targets the ZYBO and has its top level ports be the desired ports on the IP block. Then I think you can run the Create and Package IP wizard from the tools menu to convert the project to an IP core so it can be inserted into you block diagram (which will be in a different vivado project). I'd recommend simulating your project before you convert it to an IP core to help make sure it is functioning as expected. BTW, you can just expand the BRAM_PORTB interface on the block memory generator IP core and manually connect each of the signals to your IP core if you have difficulty making you custom IP implement the BRAM interface. See the picture below for an example of what your end goal will be:
  44. 2 points
    D@n

    JTAG-HS3 connection with API (DmgrOpen)

    @Assane, You know what's really cool about this then? I get to get the credit for being the "more experienced engineer" @jpeyron mentioned ... when I really know very little about this interface. Dan
  45. 2 points
    D@n

    arty - getting started and above

    @MrKing, Looking back over my answer, I think I'd like to amend it with the following: First, I didn't recommend these forums before. I'd like to do so now. Lots of folks working on their designs come to these forums for help. The help and advice I've seen given here ranges anywhere from helping the very beginner get their first design up and running, all the way to more experienced engineers trying to build a commercial product. You are more then welcome to come back and ask for help on Digilent's forum (here), and I have to imagine Digilent would be very thankful if you did: it raises the profile of their site, and hence their products. Other beginners have asked for advice here, much like you, and rather than repeat that advice, I'd like to reference you to it. It's not necessarily for the Arty, but often generic to any board: Please feel free to come back with more questions if you have more. I'd offer to help you get started, but ... I think the posts above outline how to go about that. So, instead, write back if this is confusing, or if you have further questions, Dan
  46. 2 points
    AndrewHolzer

    Image Capture System

    Hi @jem2k, I was able to locate the project buried within our server archives. I've included the project zip here for you and anybody else who may be interested in this project in the future. I've also found another project that targets the Nexys2 that does edge detection. I'm going to include it as well as an extra goodie. Good luck with your project! AndrewHolzer 23 Image Capture Watermark - Ceapa.zip 14_Image_Processing_with_Edge_Detection_-_Gidro.zip
  47. 2 points
    D@n

    Pmod8LD C code

    @Esonwe, Glad you asked! You can find a reference page for the PMod 8LD here. From there, you can find a link to its schematic, a PMod pinout diagram, a reference manual, and even a sample project for the ChipKit Mx3, if I recall correctly. Judging from the schematic, controlling the PMod is quite simple: wire each of the pins to generic I/O pins, set those pins for 3.3V output, and toggle them to your hearts desire. If the output pin is set high, the LED will be on, if set low, then the LED will be off. Let us know if you have further questions. Dan P.S. I'm assuming your other post was about this same question, right?
  48. 2 points
    Hi, there are two cases one for "bare metal" one for "linux" : "bare metal" Add this code to FSL bootloader (this code from Digilent source), Zybo board have I2C eeprom that have unique MAC address: /****************************************************************************** * This function is the hook which will be called before the FSBL does a handoff * to the application. The user can add all the customized code required to be * executed before the handoff to this routine. * * @param None * * @return * - XST_SUCCESS to indicate success * - XST_FAILURE.to indicate failure * ****************************************************************************/ u32 FsblHookBeforeHandoff(void) { u32 Status; Status = XST_SUCCESS; /* * User logic to be added here. * Errors to be stored in the status variable and returned */ fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n"); /* Read Out MAC Address */ { int Status; XIicPs Iic; XIicPs_Config *Iic_Config; XEmacPs Emac; XEmacPs_Config *Mac_Config; unsigned char mac_addr[6]; int i = 0; fsbl_printf(DEBUG_GENERAL,"Look Up I2C Configuration\n\r"); Iic_Config = XIicPs_LookupConfig(XPAR_PS7_I2C_0_DEVICE_ID); if(Iic_Config == NULL) { return XST_FAILURE; } fsbl_printf(DEBUG_GENERAL,"I2C Initialization\n\r"); Status = XIicPs_CfgInitialize(&Iic, Iic_Config, Iic_Config->BaseAddress); if(Status != XST_SUCCESS) { return XST_FAILURE; } fsbl_printf(DEBUG_GENERAL,"Set I2C Clock\n\r"); XIicPs_SetSClk(&Iic, 200000); mac_addr[0] = 0xFA; fsbl_printf(DEBUG_GENERAL,"Set Memory Read Address\n\r"); XIicPs_MasterSendPolled(&Iic, mac_addr, 1, 0x50); while(XIicPs_BusIsBusy(&Iic)); fsbl_printf(DEBUG_GENERAL,"Get Mac Address\n\r"); XIicPs_MasterRecvPolled(&Iic, mac_addr, 6, 0x50); while(XIicPs_BusIsBusy(&Iic)); fsbl_printf(DEBUG_GENERAL,"MAC Addr: "); for(i = 0; i < 6; i++) { fsbl_printf(DEBUG_GENERAL,"%02x ", mac_addr[i]); } fsbl_printf(DEBUG_GENERAL,"\n\r"); fsbl_printf(DEBUG_GENERAL,"Look Up Emac Configuration\n\r"); Mac_Config = XEmacPs_LookupConfig(XPAR_PS7_ETHERNET_0_DEVICE_ID); if(Mac_Config == NULL) { return XST_FAILURE; } fsbl_printf(DEBUG_GENERAL,"Emac Initialization\n\r"); Status = XEmacPs_CfgInitialize(&Emac, Mac_Config, Mac_Config->BaseAddress); if(Status != XST_SUCCESS){ return XST_FAILURE; } fsbl_printf(DEBUG_GENERAL,"Set Emac MAC Address\n\r"); Status = XEmacPs_SetMacAddress(&Emac, mac_addr, 1); if(Status != XST_SUCCESS){ return XST_FAILURE; } fsbl_printf(DEBUG_GENERAL,"Verify Emac MAC Address\n\r"); XEmacPs_GetMacAddress(&Emac, mac_addr, 1); if(Status != XST_SUCCESS){ return XST_FAILURE; } } return (Status); } "linux" To get actual MAC address zybo:~# ifconfig eth0 Link encap:Ethernet HWaddr 00:11:22:33:44:55 inet addr:192.168.1.2 Bcast:192.168.1.255 Mask:255.255.255.0 UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:333436242 errors:0 dropped:111 overruns:0 frame:0 TX packets:166776007 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:3075863808 (2.8 GiB) TX bytes:462587297 (441.1 MiB) Interrupt:54 Base address:0xb000 lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 UP LOOPBACK RUNNING MTU:65536 Metric:1 RX packets:432 errors:0 dropped:0 overruns:0 frame:0 TX packets:432 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:0 RX bytes:31127 (30.3 KiB) TX bytes:31127 (30.3 KiB) To set new MAC address zybo:~# ifconfig eth0 hw ether 00:11:22:33:44:55 I hope I was helpful.
  49. 2 points
    Hi Derek, The PmodIOXP demo has an example sketch IOXPDemoInt here for MPIDE that has the PmodKYPD plug into the PmodIOXP like you are describing. The sketch/libraries should help you get your project working. I used the cerebot MX4 ck chipkit which as essentially the same as the chipKit pro MX4. I was not able to get the sketch to work in the Arduino IDE but was able to get it to work in the MPIDE IDE. I have included some pictures below of my setup. Hope this helps! thank you, Jon pictures_(1).zip
  50. 2 points
    D@n

    set the PS2 power jumper

    The blue object is just a convenience for wiring two pins together. You can wire the center pin to the pin on the side you need it wired to, and you'll do just fine. It's just that, when you want to change things, it's a whole lot easier to pick up the blue piece and move it to the next location than it is to remove your wire and wrap it around the new pin you want it connected to. Dan