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  1. 5 points
    attila

    WaveForms beta download

    3.11.4 digilent.waveforms_beta_v3.11.4_64bit.exe Added: - Scope: - set/reset zero offset in each channel option - precision option for measurements Fixed: - Script: access to traces and channels from Instrument.Export - unit conversions V to Ṽ, A to à - I2S 32 bit data 3.11.3 digilent.waveforms_beta_v3.11.3_64bit.exe digilent.waveforms_beta_3.11.3_amd64.deb digilent.waveforms_beta_3.11.3.x86_64.rpm Fixes 3.11.2 digilent.waveforms_beta_v3.11.2_64bit.exe digilent.waveforms_beta_3.11.2_amd64.deb digilent.waveforms_beta_3.11.2.x86_64.rpm Added: - Spectrum, Network and Impedance Analyzer store time data when this view is open Fixed: - runscript argument - loading of docked views geometry 3.11.1 digilent.waveforms_beta_v3.11.1_64bit.exe digilent.waveforms_beta_3.11.1_amd64.deb digilent.waveforms_beta_3.11.1.x86_64.rpm Added: - Scope: out of range warning in measurements - Protocol/UART: - support up to 32bit/word - TX/RX format: text, binary, decimal, hex - Wheel Direction option - Logic Analyzer: option to swap previous/next events - Spectrum Analyzer: allowing higher number of BINs for CZT 3.10.7 digilent.waveforms_beta_v3.10.7_64bit.exe Added: - Spectrum: logarithmic magnitude scale for voltage units - Protocol: datetime stamp for SPI/I2C Spy Fixes 3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom mathematic channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Netowrk Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.
  2. 3 points
    Ciprian

    Digital Twin

    Hi @Kris Persyn, It depends on how you manage your resources, driving immersive visuals on a HDMI display can be done in multiple ways at different resolutions, some are PL taxing others are DDR taxing; you could generate entire frame buffers in PL or PS or you could find a optimal algorithm to change just the previous frame or you could allocate a high number of frame buffers and then run them in a loop. It also depends on how math lab synthesizes the IP you will need to add to your design. If you design your project properly and don't aim for a resolution higher more 720p( I'm being conservative, we managed to drive the HDMI at 1080p with processing filters without a problem) I think it should be enough for what you want to do, resource wise. My suggestion, download and install Vivado, download and install the board files, create and implement your project look at the resource consumption and then buy a board. - Ciprian
  3. 3 points
    In your constraint file, the ddc pins have lowercase "ddc_scl_io" and "ddc_sda_io". Your block design has the port in uppercase "DDC". The case must match. Try editing your constraint file to have "DDC_scl_io" and "DDC_sda_io".
  4. 3 points
    jpeyron

    pmod wifi

    Hi @harika, I believe the HTML web page error is related to the materials on the SD card. 1) Please attach a screen shot of the contents of the Sd card you are using. 2) Please follow the YouTube video here from about 6 minutes and 28 seconds on for how to set up the HTTP server project. Make sure to update the login an password for the router/modem you are using. thank you, Jon
  5. 3 points
    @thobie, the bare-metal purchase option for the Zybo was done to enable a lower price point for those who do not require the accessories. For the rest of our customers, adding the Accessory Kit is recommended during the purchase process. You are not the first and the last to complain about version compatibility. It is economically unfeasible for us to update all support projects, IP and support packages provided for free four times per year for each Vivado version. Instead we made a commitment to consider the last Vivado release in each year stable and do a once-a-year update cycle. In that regard, 2017.4 is the version we are upgrading projects to. There is a question whether OOB designs should be updated at all, or kept at the version which generated the binary image shipped with the board. The board presets are not versioned for Vivado (no version-specific releases in our git repo), because these should be forward-compatible with Vivado versions. The critical warning itself related to CK-to-DQS delays being negative appears starting with 2017.4. The negative values are due to CK trace being shorter than any of the four DQS traces. In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Zybo was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Zybos shipped to customers are functionally tested and pass the DDR3 calibration process. Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. Since these delays are board-dependent, we would need to re-design the board to make the delay positive. This is impossible with the current form-factor. Another option would be modifying the board preset file and forcing a zero value instead of the actual delay. The tools seem to be using zero anyway for calibration. This will have to be thoroughly verified first.
  6. 3 points
    Hello, I've posted the next part in my FPGA graphics series using the Arty + VGA Pmod or Basys 3. It shows you how to make use of double buffering to animate sprites using simple Verilog. https://timetoexplore.net/blog/arty-fpga-vga-verilog-03 Feedback very welcome, Will PS. I'll add the source to GitHub shortly.
  7. 3 points
    An FPGA can be a useful "swiss army knife", but all the nice features aren't easily accessible. Enter "LabToy": A batteries-included collection of utilities, just double-click and go. As the name implies, this isn't meant to compete against "real" test equipment. The main selling point is like a pocket knife - this fits into a shirt pocket and the power tools don't. And speaking of "selling points", it's free to use. So what do we have here: - Digital data: Shows the input state of all pins - Analog data: Readings from the two ADCs, up to about 700 ksps sustained (XADC "simultaneous sampling" mode, phase-accurate between channels) - Streaming data logger: Both analog and digital data can be written to a .vcd file, to be shown in gtkwave. There is no limit to the capture length. - Analog signal generator: 8 fully independent channels, sine, square wave, the usual suspects. Well, the DACs won't win any audiophile awards, but they are usable. - "Programmable" digital LED mode: Configurable pulse width to suppress short glitches, or edge detect with a built-in pulse generator to highlight them. - Analog LED mode: Shows the input value of the ADC in real time Some screenshots: 1k sine / cosine from DAC jumpered to ADC (in gtkwave) The digital signal is the generator's sync output that can be recorded as a digital input. Realtime display of the inputs. With pocket knives in mind ("this button will unlock the large blade, allowing it to be manually returned to its folded position") I decided to keep the screen uncluttered and put descriptions into tooltips. The large displays are the average voltage readings from the ADC. The smaller ones show the digital inputs in groups of four. Generator controls (frequency, minimum voltage, maximum voltage, phase). The voltage scaling is a bit unusual (typically there is "AC magnitude" and "DC offset") but I chose this approach because it shows clearly the limitations of the 0..3.3V output range. Most people will probably leave all this at the default values for a full-scale signal. Data capture Example: The output in gtkwave after I touched a jumper cable to the digital inputs on the DIL connector. +++ DO NOT USE THE +5V OUTPUT P24 FOR THIS KIND OF TEST +++ (3.3 V is available on the PMOD connector, bottom row) The red "undefined" marks flag the first input in an 8-bit group. In this example, they aren't too meaningful, but they can alert me to the fact that no data events have been observed yet. LED control The two numbers give the number of consecutive 1 or 0 samples (at 125 MHz) before a signal change is propagated to the LED. E.g. put 125 million there and it'll take one second after changing the input state for the LED to light / go dark. Those can be used interactively to study an unknown signal. "Level": no further processing ("level" mode and 1 / 1 sample counts is equivalent to directly connecting the LED to the physical input) "Edge" mode generates a brief pulse on signal changes, the LED is dark otherwise. "Invert" flips the input right next to the pin (0 becomes 1, black becomes white and man gets himself killed on the next zebra crossing -DA). How to get it: The file is attached: labToy0v1_beta.exe The installer unpacks a single .exe. Happy hacking! Requirements: Windows 64 bit (!) .NET 4.5 FTDI libraries CMOD A7 35 T (not 15 T). Warnings: Direct access to digital IO pins is an inherently dangerous activity. "PROVIDED WITHOUT WARRANTY OF ANY KIND" means Just That. And beware of the +5V pin. PS: If you try it, kindly let me know whether it works, or what goes wrong.
  8. 3 points
    attila

    Using script with Spectrum on AD2

    Hi @tomtektest, @abzza With WaveForms Script THD and other measurement logging and plotting can be automated, like this: function doTHD(){ var rgTHD = [] var rgFreq = [] for(var idx = 1; idx <= 100; idx++){ Wavegen1.Channel1.Simple.Frequency.value = 1000*idx Wavegen1.run() // start AWG wait(0.01) // settle time for the external circuit, expressed in seconds Spectrum1.Frequency.Stop.value = 20*Wavegen1.Channel1.Simple.Frequency.value // adjust analyzer stop frequency Spectrum1.single() // start acquisition if(!Spectrum1.wait()){ // wait to finish return; } rgFreq.push(Spectrum1.Trace1.measureFreq("FF")) rgTHD.push(Spectrum1.Trace1.measure("THD")) } Wavegen1.stop() print(rgFreq, rgTHD) // print data for copy paste // draw in plot1, View / Add plot plot1.X.Units.text = "Hz" plot1.Y1.Units.text = "dBc" plot1.X.data = rgFreq plot1.Y1.data = rgTHD } doTHD();
  9. 3 points
    zygot

    Rants about FPGA tool chain(s)

    @D@n , Here's a secret; I'm whispering because this is just between you and me: At places where they do a lot of quality FPGA development work no one ever brings up a GUI for anything. All of the toolchain invocation is done using Perl and TCL/TKL. Shhhh. Don't tell anyone....
  10. 3 points
    A few reasons are... a - The introduction of logic hazards can cause glitches : https://en.wikipedia.org/wiki/Hazard_(logic) b - Routing of clocks is very complex - It is hard to ensure that the same clock edge appears all over the FPGA at almost exactly the same time. Sometimes this is achieved with 'slight of hand' (e.g. using a on-chip PLL to advance phase of the clock, so that by the time it reaches the edge of the chip is in back phase with the original signal). Low-skew paths also exist, but are restricted to small areas of the FPGA, and the clock has to be connected to the correct pin to be placed and routed correctly. c - FPGAs and their tools are designed to behave predictably under the "synchronous digital design" paradigm (something like https://hps.hs-regensburg.de/scm39115/homepage/education/courses/red/2_SynchronousDigitalCircuitDesignRules.pdf). If you work outside the paradigm you will be fighting against the tools and their assumptions. d - There is almost nothing that you are unable to code in an FPGA friendly way, but there are infinitely many ways to write FPGA-hostile code. If you want your FPGA to place nice with you, you have to play nice with it. So you can either add an RC filter to debounce you switch, or you can sample it using a reliable clock.
  11. 3 points
    D@n

    Just for fun: Frequency Resolution challenge

    Hello everybody! Since I was sharing this image with others, I thought I'd share it here at Digilent as well. The attached image shows the frequency response of several FFT windows, including the well-known rectangle and Hanning windows. The blue window is one I've put together, but haven't shared the FPGA source code used to implement it. I challenge anyone to do better. Oh, and one other comment ... all but the Hanning window can be used in an invertible FFT process. Dan
  12. 3 points
    Tempest2k8

    OpenScope Mechanical STL Files

    Printed out on the Form Labs at my local TechShop.
  13. 3 points
    jpeyron

    Cmod A7 35T GPIO demo Error

    Hi @coloradosensors, I just generated bitstream on this project in Vivado 2015.4. You need to right click on the clocking wizard and remove it. Then under project manager click on ip catalog and re-add the clocking wizard with default settings. This will fix your issues with using an older version of Vivado for this project. cheers, Jon
  14. 3 points
    D@n

    Lots of fun UART testing code

    Hello Digilent Community! I just finished putting the finishing touches on a UART demonstration project that you can find here. The project was originally intended to share a C++ class that could work with Verilator to prove that anyone's UART implementation was working. However, after I got into it, I realized the project had a lot of value that others might appreciate. As an example, consider this post by @martin16. Had he used any of the testing mechanisms listed below, he might have known which side of the RS232 port he was working with was at fault. The core contains a complete implementation of both a transmit and receive UART encoder/decoder. These can be easily taken from my project and placed within your own. (Subject, of course, to the limits of the GPL v3) The core also contains a (fairly) generic FIFO implementation. For those wondering how to implement a FIFO, you may find this valuable as well. For those who would rather interact with a serial port over a bus, such as the wishbone bus, there are two approaches within the project that can be used to hook it up to a wishbone bus. One can be used within a larger wishbone slave module, the second as a standalone module. Both are Wishbone B4 compliant, and both use the pipeline mode--allowing you to read/write multiple values on consecutive clocks from/to the controller. Of course, this only really makes sense when using the FIFO. Those might be valuable enough on their own, but you can probably find without too much additional work other implementations of the above. Therefore this project includes some even more valuable files: It includes a series of test programs/configurations that can be used to determine if the hardware on your board is working properly. If you are like me, you've struggled every time you've tried to get a serial port working on a new board. Should you connect your output to the TX or to the RX line? Do you have the UART set up properly, at the right baud rate? Can you handle more than just single values at once? How fast can you transmit/receive? To help you answer these questions, the project file contains the following test configurations: Hello World: You know, that old fashioned hello world program? I would recommend trying this program on your board after you can blink an LED at your favorite rate, or equivalently after you know that your clock works. This particular project is so simple that it depends upon only the clock input and the UART transmit output. Getting this program running on your board will demonstrate that you understand your clock, and that you can modify your I/O constraint file properly, and that you know how to connect a terminal program to your board in order to observe the results. Line Test: Once you've got a hello world program running, so that you know the output UART pin works, then it is time to test the input UART pin. This is the purpose of the line test testing program. It works by reading a line of data (either until a newline or 80--characters), and then dumping that line to the output. (Don't forget to turn off hardware flow control, and be aware of the differences between a new line and a carriage return!) SpeechFifo: Finally, there's a program that can be used to test the FIFO capabilities found within the wishbone UART peripheral. This program uses the FIFO capability to make certain the transmitter stays fully loaded for over a thousand characters of output bytes. (No, this isn't computer speech generation, but rather a computer dumping a Abraham Lincoln's Gettysburg Address across the UART port.) Each of these configurations has a corresponding Verilator simulation file associated with it, allowing you to simulate the functionality within them as part of Verilator. The project includes, like I mentioned above, a C++ class that can be used to determine if your own UART is transmitting correctly under a Verilator simuation. This class can also be used generate UART signaling in order to test if your RTL can receive it properly. (See the line test C++ harness discussed below for an example of this.) As complements to each of the testing configurations above, the project contains C++ files to drive each of those within a Verilator context. Some unique features include: The Line Test C++ test harness automatically generates a linetest.vcd file that can be used together with GTKwave to study how the core works. Further, it can be run in either an interactive or an automated mode. The Speech Test C++ test harness can be used in an automated mode, or with the -i switch in a more interactive mode. In this latter mode, the speech test program generates a speechtrace.vcd file that can be used with GTK wave to understand how the UART transmitter, FIFO, the wishbone bus decoder, or even the test harness itself. I hope you find these as valuable as I have. Please feel free to post any questions or comments you might have about this project below. Dan
  15. 3 points
    LariSan

    Birth of an OpenScope!

    We got a series of photos of the OpenScope going through the manufacturing line. Unfortunately, Kickstarter didn't allow me to load all of them onto the update.
  16. 3 points
    D@n

    Nexys 4 DDR

    @gnicholls, Wow, what a good and thorough question. You've hit the nail on the head, and you are asking something a lot of users are asking. So in answer, may I reply, Welcome to the wonderful world of FPGA design! DDR memory is hard. I mean, really hard. I tried for about two solid months to get a DDR3 memory up and running, and eventually moved on because it was taking too much time to do. You can still find the project here, though--and I still hope to return to it--eventually. Xilinx has written a variety of App notes describing how they've gone about creating their reference solution. For 7-series devices, you can find their note here--but it just doesn't tell you much. I've found the most useful information in their note from a couple generations back, found here for a Virtex-5. Bottom line: it's *really* hard--most people only use the reference solution, and then make the reference solution work for their design. I love the examples found at fpga4fun.com. They tend to work through many of the basic I/Os that FPGAs need to work with, and how to build controllers for each of them. Another useful website is Asic-World--it's just not one I've ever gotten into. Xilinx has tried to make your problem easier with their platform studio and now its Vivado replacement--allowing you to connect via point and click various different Xilinx components together to make one of many (fairly) pre-canned designs. Many of the Digilent based "tutorials" or "examples" are of this type. I personally find them wanting, for many reasons: They are "too easy"--offering you no insight for how they are accomplished internally. They are so much of a black box that you cannot examine what they did or how they did it in order to modify it, debug it, or even learn from it. It can be difficult to integrate your own work with their components. They are all focused on how to use someone else's components, but offer little in the way of teaching you how to build your own. In the end, they leave you stuck with Xilinx solutions. Any components you create/develop will only ever work with Xilinx. This leaves you forever wedded to the Xilinx platform, or forced to relearn all you have learned. Verilog (and <gasp> even VHDL) is a better language than that--capable of doing a lot more. And if that's not enough, your design that works with one version of Vivado may well break when the next one comes out because ... they changed something. (This is an ongoing problem, and a thorn in Digilent's side--suggestions are always welcome.) I have personally been trying to work to create somewhat of a solution to your problem, but I'll admit my own designs are perhaps far from the professor's materials that you are looking for. You can find many of my Verilog designs on github here. A recent design I've put together for both beginners and more experienced types alike can be found here. It contains examples of how to create a serial port, both transmitter and receiver, together with some top level designs that use such a port. As the task of figuring out which pin is which on any board is fairly common--even among experienced users, these offer examples you can work with to make sure you have your serial port working. My efforts have gone so far as to even build my own CPU, flash controller(s), SD-card controller, GPS controller, real-time clock, 7-segment controller, FFT, VGA controller, etc. I mean, why when you buy a board would you only learn to work with some of it, right? You can find a fairly complete design here, using a CMod-S6, that places a CPU onto the S6 with a minimal multi-tasking "operating system". I'm also working on a more complicated design for the Arty here--this one uses the Xilinx generated MIG DDR3 SDRAM, such as you have on your Nexys 4 DDR. This design is currently somewhat on hold, as I am trying to update the CPU within it to a more mainstream CPU that will even support the C-library. (Today's success: I managed to get newlib to compile for it! This is after updating the assembler, linker, GCC compiler backend, etc.) If you are a hard-core VHDL type, Xess.com has put together a fascinating library of VHDL routines to demo how to use their boards. To my knowledge though, the tutorial information within their libraries is ... a bit harder to follow than the simple point and click designs Xilinx peddles. One of the things I've noticed about many (most, all?) of the more complicated FPGA designs I've come across is that they all depend upon some form of internal bus by which things can be connected. Once you get past learning about how to build the simple peripherals fpga4fun wishes to teach you, you're next step is really to learn about that bus structure. Why? If for no other reason than memories seem to be best accessed via a bus, so anything using a DDR type of memory tends to send its requests over a bus. This can easily become a bottleneck to your design, but ... it sort of comes with the territory. You can build other memories and distribute them throughout your FPGA, but the amount of block RAM memory you will get within any FPGA tends to be ... never enough. Hence you are often stuck with the external memory chip(s). Xilinx uses the AXI bus protocol. You can find the specification for it here. I haven't found any good tutorials on how to use it, but there's a way you can get Vivado to generate a sample AXI-lite design that you can interface with. (I can google it if you are interested--I just don't have it at my fingertips.) I've personally used the Wishbone Bus protocol, version B4, pipelined mode. Many others use version B3. I find that I can transfer data 3x faster using B4. To get from the Wishbone Bus to a DDR memory, controlled via Xilinx's Memory Interface Generated AXI controller, I built a wishbone-AXI bridge. Others of these also exist. There's an open source package manger out there called fusesoc which was designed to facilitate composing solutions from many different FPGA components together. In particular, the OpenRISC team has put a lot of work into making sure their CPU's, peripherals, and board designs can be built using this package manager. (These tend to connect to each other via the wishbone B3 standard.) If you dig into this, you can probably find many, many examples of working peripherals for various boards--although that community does tend to focus more on the Altera boards than the Xilinx boards, and Verilog more than VHDL. So ... when I build a new design, how do I do it? For every board of Digilent's that I have bought, I start with the reference page, look up the schematic to see how the components are connected, and then google the part numbers on the schematic. Those will contain the instructions you need to access the various chips on your board. They are usually where things pick up next after you leave the canned tutorials and examples. I hope I haven't overwhelmed you, but really ... where you go next is up to you. What would you like to do? Dan P.S.: My favorite description of RTL design for those who know nothing about FPGA's is, "Infuriatingly complex in its simplicity." Everything you do will be simple--like the clock divider. But too many of these very "simple" components can become so complex that it very quickly gets under your skin.
  17. 3 points
    hamster

    Welcome!

    My name is Mike, and I've developed a bit of an obsession with FPGAs. You might be able to find some project ideas or inspiration on my WIki at http://hamsterworks.co.nz/mediawiki/index.php/FPGA_Projects I'm always happy to talk FPGAs, so feel free to drop me an email sometime
  18. 2 points
    Hi, there's a lot of new information in your last post. You aren't just "trying" FPGA but have a professional interest in Zynq. Don't let anybody scare you it's "difficult" and go for it, possibly with the cheapest board, no tutorials and low expectations like, blinking LEDs for quite a while. Given the price tag of any industrial training coarse, an FPGA board for self-study is a no-brainer. Maybe save some money to buy your FPGA engineer a coffee once a week, with some questions in mind
  19. 2 points
    True. Zygot believes that making you work for knowledge is kinder than giving you solutions that can be used to mindlessly resolve your problem of the hour.... it's just a different philosophical bent...
  20. 2 points
    @Ahmed Alfadhel If you installed Vivado then you also installed the Xilinx Document Navigator. If you are serious about developing with FPGA devices you need to know how to find and access the plethora of documents that your vendor provides in order to use their devices properly. Check the box for 7 Series devices to see the list of reference manuals, User's Guides, Datasheets etc. From there you can add all relevant documents to your search and keep up to date. Do the same for ISE or Vivado tools. This is where everyone needs to start their Xilinx FPGA journey. Xilinx makes it easier than other FPGA vendors to obtain knowledge.
  21. 2 points
    The warning you pasted is benign and simply means there are no ILAs present in your design. The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design. Finally, @elodg gives some great troubleshooting information in this thread.
  22. 2 points
    Hi @NYSD It is under development.
  23. 2 points
    attila

    Math on FFT traces

    Hi @lab!fyi 1. I think for your experiment you should use the Network Analyzer interface of the WaveForms application. Connect the Scope channel 1 to your filter input and channel 2 to the output. By default, the analyzer plots the magnitude and phase of channel 2 relative to 1. This will give the characteristics of your filter. In the NA under Wavegen gear menu select channel external (let you use external or custom wavegen control) and frequency extended (to let you use up to 50MHz). The Scope Math channel is performed on the time domain data not on the FFT. 2. The persistence view will be update with the next software version to handle curve interpolation option as well the min/max sampling.
  24. 2 points
    jpeyron

    Zedboard Zynq 7000 XADC Header

    Hi @farhanazneen, I used the Analog Discovery 2 which has the 2x15 Flywires: Signal Cable Assembly for the Analog Discovery without issue. Each signal wire is 260mm± 20. thank you, Jon
  25. 2 points
    @hamster I was able to run your AXI Slave interface. It works great! It is now very easy to exchange information between PS and PL, and it even supports execute-in-place (e.g. I can put ARM instructions to register file and run PS CPU directly from it). I have some questions about your AXI Slave design: 1) AXI_a*size has no effect on INCR type of burst transactions, but according to AXI protocol: the increment value depends on the size of the transfer. You set it only for WRAP type, is it correct? Thus, burst size is always 0 for INCR type? 2) Do you know how PS initiates INCR burst type? A kind of memset/memcpy need to be used for that or an incrementing pointer will also work? 3) Where WRAP type is necessary? How to use PS to work in WRAP mode? You may also update your wiki page with following: 0) Create provided VHDL files 1) Create a block-diagram and add PS IP core to it 2) Apply configuration provided by your board's pre-settings; this will set all necessary initialization settings for PS (e.g. clock frequencies, DDR bindings, etc.) 3) Press auto-configure (or how it's called) ==> this will connect PS IP to DDR and to fixed IO 4) Add "External ports" to the diagram (create new AXI_CLK and AXI external ports) and connect them to PS ports 5) Generate VHDL wrapping code for this block diagram 6) Put generated system under axi_test_top by renaming it to axi_test_wrapper (default name is design_#_wrapper in my Vivado version) 7) This will auto-connect block-diagram external ports with axi_test_top 8 ) Add constrains file and rename/uncomment external ports where necessary 9) Generate bitstream 10) File->Export->Hardware and create .hwf file which contains PS configuration 11) Open Xilinx SDK and create a new project: select .hwf file as Hardware BSP for this project 12) Now, Xilinx SDK will auto-generate few .c and .h files which contain necessary PS initialization ==> clocks, IRQs, DDR, etc. 13) Add hello_world.c application to the project @hamster Thank you very much. I've learned a bunch of new things thanks to your help!
  26. 2 points
    D@n

    XADC and the FFT

    @farhanazneen, I don't have @mohamed shffat's code, nor have I seen it. Therefore, I would struggle to answer your question regarding how he accomplished (or didn't accomplish) this task. As I recall, I've posted all of the details of my own solution on zipcpu.com, although several of the components were spread across multiple different blog posts. I think I've already linked to these above, though, so if you are missing some part of my own solution, please speak up. By the way, my solution is done in completely in Verilog. I haven't used the XADC (yet). It's also highly dependent upon what I call a debugging bus: a concept explored (and built) on my blog as well. Dan
  27. 2 points
    Ram

    vivado 2017.4

    Thank-you melisha ,,it is working Ram
  28. 2 points
    Piotr Rzeszut

    Analog Discovery 2 vs NI myDAQ

    Hi, NI myDAQ has an input sample rate of 200 kSPS and bandwidth of 400kHz, where AD2 has 100MSPS and 30MHz+ (with adapter) => point for AD2 NI myDAQ has maximum input voltage +-10V, where AD2 has +-25V => point for AD2 NI myDAQ has an output sample rate of 200 kSPS, where AD2 has 100MSPS => point for AD2 NI myDAQ has maximum output voltage of +-10V, where AD2 has +-5V => point for NI myDAQ NI myDAQ has a built-in multimeter (so it is able to measure in addition to voltage, also resistance, current, diode voltage without any additional adapters) AD2 requires separate adapters for such measurements => point for NI myDAQ NI myDAQ has fixed +-15V supplies (32 mA) and +5V (100mA), where AD2 has 0...5V and 0...-5V voltage outputs (700mA max with external power supply) => point for ??? Ni myDAQ has 8 digital IO, where AD2 has 16 of them. Also AD2 IOs can be controlled much faster than ones in myDAQ => point for AD2 This is a fast comparison of a key features. Full documentation of each device are available here: https://reference.digilentinc.com/reference/instrumentation/analog-discovery-2/reference-manual http://www.ni.com/pdf/manuals/373061f.pdf Summing up all above (in my opinion): AD2 is a better choice for debugging fast analog and analog/digital circuits. A software adds a great value by allowing various measurements and tools without any need of programming. Also an interface for python scripting allows designing own applications. There is also LabVIEW interface provided. You can always see all these functions in interactive demo - just download recent Waveforms software. https://reference.digilentinc.com/reference/software/waveforms/waveforms-3/start NI myDAQ offers much slower I/O and less digital channels. At the other hand it can be used as off-the-shelf multimeter`. It also includes basic software and interface for LabVIEW, but lacks for example interface control (I2C, SPI, ...). http://www.ni.com/tutorial/11431/en/ Also AD2 can be purchased in reduced price for academic use. This is of course my private opinion on these devices - you have to decide which one to buy by analyzing use cases.
  29. 2 points
    attila

    Analog Discovery 2 vs Raspberry Pi 3

    Hi @Phil_D @rprr The problem is that the USB IN packets/bytes are randomly lost/altered. I tried various kernel options, limiting the USB transfer rates but had no luck. The data corruption reduced from one in 1-60 seconds to one in 10-60 minutes, which it is still not good... It seems that the root of the problem is in the low level FTDI library, kernel or USB modules, or between them... The Analog Discovery is working fine with other SOCs but not with the RPi. I also notice issue with the USB keyboard I use with the RPi, time to time key presses are not received. You can find many similar RPi issues on the net: https://www.raspberrypi.org/forums/viewtopic.php?f=28&amp;t=5249&amp;sid=8839659cb92b7475fa196b2fad775d9f&amp;start=250 http://www.ftdicommunity.com/index.php?topic=40.0
  30. 2 points
    Thanks) It solved the problem)
  31. 2 points
    Adam_Darkh

    Arty-s7-25

    @JColvin Thank you. Your response prompted me to double-check my installed Vivado software. It was entirely my fault. On the Vivado 2017.4.1 release notes, it says that only the update 1 to Vivado 2017.4, namely 2017.4.1 Webpack should support Arty-s7-25. The original release of Vivado 2017.4 does not support Arty-s7-25 but it does support the Arty-s7-50. So I download both 2017.4.1. and 2018.1 and Arty-s7-25 shows up on both just fine. Kindly, -Adam
  32. 2 points
    Hi @Tickstart, Since your question was not directly related one of the Digilent FPGA boards, I have moved it to a different section of the Forum to hopefully produce less confusion for other readers. As for my personal perspective, I'm in a bit of an odd spot since I have a degree in chemical engineering rather than EE/CS/CompE, yet here I am helping answer questions on all of those things, meaning I don't have a lot (i.e. any) formal education with HDL design. But like Dan hinted at, I'd like to make sure that the people to be hired can "engineer" their way through a problem, not just hope that a single approach works for everything. Thanks, JColvin
  33. 2 points
    Hi @BYTEMAN, Feel free to put up your dropbox link to your project if you so wish; I know we had communicated about this earlier, but for the interest of letting other users know that they may put dropbox links or google drive or something similar links to their project if the Vivado project gets too big to upload. Alternatively, pictures can be uploaded via the Gallery which doesn't have the same upload restrictions as putting the image directly into the post. Thank you, JColvin
  34. 2 points
    @Aniq, I've never seen an FPGA board with a VGA input. You could certainly attempt to decode VGA with a fast ADC but it won't be trivial. VGA appeared on the old FPGA boards as HDMI/DVI still weren't mainstream yet. The cheaper FPGA boards offer VGA output using resistor ladder networks but really, the VGA monitor is disappearing. I'm not sure what you need to do with such a board but the best bet would be to find a generic FPGA board and compatible HDMI in/out adaptor and design you own VGA in/out interface. Most FPGA boards, except Atlys, Genesys2 use dedicated HDMI receiver or transmitter ICs which takes some control out of your hands. These devices are generally very programmable ( depending on how they are connected ) but not as flexible as say, the Atlys, but for a board like the Atlys you are responsible for creating the logic that the dedicated IC does. PAL, NTSC, SECAM etc are also video standards that have seen their day hit sunset.
  35. 2 points
    attila

    WaveForms 3.6.8 release

    Dear All, The new software version can be downloaded from the following page: https://reference.digilentinc.com/waveforms3 The changelog is available here: https://reference.digilentinc.com/reference/software/waveforms/waveforms-3/change-logs/3-6-8 See this blog for more details: https://blog.digilentinc.com/software-update-waveforms-3-6-8/ Please let us know if you have any observation. Thank you, Attila
  36. 2 points
    Hi @cristian_zanetti, Here is a tutorial explaining UART. Here is a XADC(mostly Verilog) demo on Github with a link to its project page in the REAMME. Here is the GPIO demo(vhdl) on Github with a link to its project page in the REAMME that has a Uart tx controller. Here is a project done by one of our community members that has the xadc done in VHDL. cheers, Jon
  37. 2 points
    D@n

    Memory Access

    @shis, If you only need to read the matrix one column at a time, transpose it. Memory works well when you attempt to read adjacent memory areas or in sequence. Which memory you choose also depends upon your timing needs. Most of the flash devices on the boards Digilent sells can read 8'bits every 20-40ns. However, they may take up to 240ns to get that first byte through. (Some of this depends on whether you are running the flash serial clock with a 50MHz or a 100MHz clock) Open source wishbone controllers &nbsp;are available, should you want one. SDRAM can be much faster. My Arty can read 128-bits every 12ns or so, although the first request may take about 300ns to complete--if I recall correctly, it's been some time since I measured that latency. I'm now working with a Nexys Video that can read 128-bits every 10ns, but I have no idea what the latency is through the controller. Should you choose to wish to use SDRAM, you'll probably want to initialize the SDRAM from the flash anyway. If you'll notice, I just gave two numbers for the speeds of each of those parts. The first is the speed you should be able to achieve if you read your values in sequence. The second, if you read your values in random order (i.e. column order) from your device. Just a thought or two, Dan
  38. 2 points
    artvvb

    This darn simulator...

    @Tickstart The simulator can have issues with figuring out what a signal should be when it is derived from itself or another signal that is derived from the first signal. This is only a problem when the signal is not initially defined or all of the paths to derive it depend on it. I am more familiar with verilog, so take vhdl suggestions from me with that in mind, but the following is what I would suspect would help fix the problem. //file D_flipflop.v: //Verilog Before: `timescale 1ns / 1ps module dff ( input clk, input d, output reg q ); always@(posedge clk) q <= d; endmodule //Verilog After: `timescale 1ns / 1ps module dff ( input clk, input d, output reg q ); initial q <= 0; always@(posedge clk) q <= d; endmodule And my attempt at VHDL for the same thing: //File D_flipflop.vhd //Before: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity D_flipflop is Port ( clk : in STD_LOGIC; d : in STD_LOGIC; q : out STD_LOGIC ); end D_flipflop; architecture Behavioral of D_flipflop is begin name: process (clk) begin if rising_edge(clk) then q <= d; end if; end process name; end Behavioral; //File D_flipflop.vhd //After addition of initial value: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity D_flipflop is Port ( clk : in STD_LOGIC; d : in STD_LOGIC; q : out STD_LOGIC := '0' ); end D_flipflop; architecture Behavioral of D_flipflop is begin name: process (clk) begin if rising_edge(clk) then q <= d; end if; end process name; end Behavioral; My other suggestion would be to take a look at the RTL Analysis -> Elaborated Design -> Schematic for your project, this tool is used to help figure out what the logical circuits that your design is being translated into are. I've attached the schematic I generated for your design. The important thing here is that looking at the I signal's paths, everything route from I to a 'd' pin goes through an AND gate. This means that if the other input to each gate is undefined, the output of that gate will be undefined. In short, this was just a long way of saying that you probably need to add ' := '0' ' to your D_flipflop file. Hope this helps, Arthur
  39. 2 points
    Notarobot

    Zynq PL-PS Interrupt issue

    @artvvb The issue seems to solved after I've added the statement: XScuGic_SetPriorityTriggerType(IntcInstancePtr, INTC_INTERRUPT_ID,0x00, 0x3); Now the applications responds and counts interrupt sisgnals coming fro PL. Regards, N
  40. 2 points
    jpeyron

    Quad SPI flas and .bin file upload

    Hi @ThomG, I found a thread on the xilinx forums here that says to program the flash using the non-project stand alone mode. I was not able to program the flash in Vivado 2017.1 using the hardware manager in the project but I was able to program the flash using the stand alone hardware manager on the main page under the tasks section. I have included a screen shot. I also included a completed project that programs the flash with the hello world and following the this tutorial. Screen shot below of tera term. hello_world.zip
  41. 2 points
    D@n

    ISE Design SUITE

    @buraklar, Welcome to the forum! Can I encourage you anyway in your current struggle as you work on your exam? I remember my exams from years back. As I recall, I wasn't allowed to ask for help from anyone other than the instructor. I don't think my experience was that unique. I think you will learn, here at this forum, that many, if not all, of those who answer questions here have been in your shoes some time before in our life--in a class, stuck (forced?) to learn a new skill, or taking exams to prove that we've actually acquired said skill. Some of us are also in the business world, and one of the things we do not want to do is to make the mistake of hiring someone with a wonderful resume boasting of impressive academic credential's who never learned the skills his academic credentials suggest he has. For this reason, and I apologize for this, I'm not going to do your exam work for you. (Sorry!) That said, many, many students come to this forum for help on their projects. Most of them leave the forum with exactly the help they came looking for. The one's who come to the forum with no idea where to start are often pointed to the documentation for the part or board they are working with. Some are counseled regarding how to build a design, leading to an open discussion that many take part in. Others come to the forum with a design (partly?) written that doesn't work for some reason or other. Sometimes they get the same response as the first group--the documentation to go read up on. Others get lucky and find someone nice enough to look over their code and comment on any mistakes they find. These are the people willing to work hard at their problems, the folks who really want to learn how to do the task themselves. Typically this is only a small part of their FPGA or embedded journey, still ... I think most who come here would find it a valuable part of their journey. Those who come to the forum and leave disappointed are typically the ones who have learned how to manipulate others to get their work done for them and hence have no idea how to do their own work, or those who are unwilling to even try. These people often leave here thinking the world is against them, and their professor and the Digilent Forum moderator's just hate them. While I don't hate you, I'm going to politely decline to solve your university exam problem for you. Consider it an act of love. (No, sorry, I'm already married ...) I wish you the best, and hope you do well, Dan
  42. 2 points
    @silverwolfman, I don't have my S6 on my desk to tell you how much time it took me to load the flash, but I do know I didn't use iMPACT. You can find my work here. In particular, the flash loader is called zipload, and depends upon the using the Digilent Adept utilities to load an initial configuration (generated from this toplevel file) into the flash. Dan P.S. I'll be redoing my work again soon, to prove that the updated ZipCPU can still fit (and work) on the device. You can see some of my update works in the 8-bit branch of the s6soc project, but ... although it builds, it hasn't been tested yet so ... it's still a work in progress.
  43. 2 points
    jpeyron

    Cant Generate a License File

    @JColvin I'm not sure what happened there. But the link is here. cheers, Jon
  44. 2 points
    D@n

    UART

    @zahid, Yeah, ... but ... we still haven't solved your original problem--that of receiving every other letter when you pipe things directly from the GPS to your computer. But, at least now, we know some new things: We know that your computer isn't broken, neither is the serial port or terminal on it, and the cable you are using appears to be good then. We know there are no foreign character set issues, such as things that take 2 characters to print one. We know that it can successfully receive at 9600 Baud. (We're you trying with the extra stop bit, or not? So, the question now is, what happened and what can we do to fix it? Here's my thought: when you used the echo test program to read from your GPS device, we rounded the number of baud clocks downward (as the spec suggests). The result, though, was that the receiver--which calibrates its input to the start bit of each character, was receiving the characters in just a couple clocks fewer than the transmitter was using. The result, then, was that when the receiver was done with the second character -- the transmitter was still transmitting the last one. The receiver strobes the line for the transmitter to start (i_wr inside txuart.v), but the transmitter is still busy ... so it ignores the write request. By the time the next byte is received, the transmitter is now idle and ready to accept the next request. As a result, you got what you saw above: every other character received. The problem was in your FPGA code, and not within your host. Suppose we test this? If you want to go back to your echo test and try again, then try setting the i_setup register to one or two clocks faster. When I personally ran the test to echo what was received from the GPS receiver to the PC/host (I haven't posted the code for this), I switched the line speed from 9600 Baud up to 115,200 Baud or faster, such as 1MBaud. At this high speed, you wouldn't have a problem. To do this, you'd need to set the setup register on the transmitter (txuart) for 115,200 Baud and that on the receiver (rxuart) for 9600 Baud--you'd also set your PC for the 115,200 Baud. Another possibility might be to try the line testing program. This one should manage to do large strings without losing anything, but I expect it would still struggle after a long series of things were received--only to recover by the top of the next second. So, at this point, I think we know what's going on and can move forward successfully. Feel free to tell me how any of these new tests work! Dan
  45. 2 points
    There are also open source RTCC cores out there as well. Dan
  46. 2 points
    D@n

    XADC demo

    @Manas, Sam is trying to turn voltage = (12-bit-code)/4096 into microvolts = (1000)*(1000)*(12-bit-code)/4096, and he's trying to avoid division. Rearranging: 1000*1000/4096 = 500*500/1024 (just by dropping common factors of two from both numerator and denominator) Shifting right by ten is equivalent to dividing by 1024, and then he multiplies by 500*500. Looks like it works alright. I might be concerned personally about losing any precision in the divide by 1024 (i.e. shift right by 10), especially since it is being done before the multiply if I understand correctly--leaving you with only 2-bits of precision (did I read that right?). Looking at the above, you might simplify it further into a shift right by 6, followed by a multiply of 15625. To get here, all I did was cancel out any factors of two that were in both the numerator and denominator. Then --- rearrange your order of operations, so the multiply is done first. What makes this choice special is that 15625 can fit within an 18-bit multiplier. Hence you can do: A = 15625*(12-bit-voltage-code) inside a DSP multiplier, and hence inside one clock. The result of this multiply will be a 30-bit number. If you ignore the bottom six bits, the 24-bit number that remains will be the number of microvolts that you are looking for. Converting this to a decimal display might take some more work though. Dan
  47. 2 points
    Hi, there are two cases one for "bare metal" one for "linux" : "bare metal" Add this code to FSL bootloader (this code from Digilent source), Zybo board have I2C eeprom that have unique MAC address: /****************************************************************************** * This function is the hook which will be called before the FSBL does a handoff * to the application. The user can add all the customized code required to be * executed before the handoff to this routine. * * @param None * * @return * - XST_SUCCESS to indicate success * - XST_FAILURE.to indicate failure * ****************************************************************************/ u32 FsblHookBeforeHandoff(void) { u32 Status; Status = XST_SUCCESS; /* * User logic to be added here. * Errors to be stored in the status variable and returned */ fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n"); /* Read Out MAC Address */ { int Status; XIicPs Iic; XIicPs_Config *Iic_Config; XEmacPs Emac; XEmacPs_Config *Mac_Config; unsigned char mac_addr[6]; int i = 0; fsbl_printf(DEBUG_GENERAL,"Look Up I2C Configuration\n\r"); Iic_Config = XIicPs_LookupConfig(XPAR_PS7_I2C_0_DEVICE_ID); if(Iic_Config == NULL) { return XST_FAILURE; } fsbl_printf(DEBUG_GENERAL,"I2C Initialization\n\r"); Status = XIicPs_CfgInitialize(&Iic, Iic_Config, Iic_Config->BaseAddress); if(Status != XST_SUCCESS) { return XST_FAILURE; } fsbl_printf(DEBUG_GENERAL,"Set I2C Clock\n\r"); XIicPs_SetSClk(&Iic, 200000); mac_addr[0] = 0xFA; fsbl_printf(DEBUG_GENERAL,"Set Memory Read Address\n\r"); XIicPs_MasterSendPolled(&Iic, mac_addr, 1, 0x50); while(XIicPs_BusIsBusy(&Iic)); fsbl_printf(DEBUG_GENERAL,"Get Mac Address\n\r"); XIicPs_MasterRecvPolled(&Iic, mac_addr, 6, 0x50); while(XIicPs_BusIsBusy(&Iic)); fsbl_printf(DEBUG_GENERAL,"MAC Addr: "); for(i = 0; i < 6; i++) { fsbl_printf(DEBUG_GENERAL,"%02x ", mac_addr[i]); } fsbl_printf(DEBUG_GENERAL,"\n\r"); fsbl_printf(DEBUG_GENERAL,"Look Up Emac Configuration\n\r"); Mac_Config = XEmacPs_LookupConfig(XPAR_PS7_ETHERNET_0_DEVICE_ID); if(Mac_Config == NULL) { return XST_FAILURE; } fsbl_printf(DEBUG_GENERAL,"Emac Initialization\n\r"); Status = XEmacPs_CfgInitialize(&Emac, Mac_Config, Mac_Config->BaseAddress); if(Status != XST_SUCCESS){ return XST_FAILURE; } fsbl_printf(DEBUG_GENERAL,"Set Emac MAC Address\n\r"); Status = XEmacPs_SetMacAddress(&Emac, mac_addr, 1); if(Status != XST_SUCCESS){ return XST_FAILURE; } fsbl_printf(DEBUG_GENERAL,"Verify Emac MAC Address\n\r"); XEmacPs_GetMacAddress(&Emac, mac_addr, 1); if(Status != XST_SUCCESS){ return XST_FAILURE; } } return (Status); } "linux" To get actual MAC address zybo:~# ifconfig eth0 Link encap:Ethernet HWaddr 00:11:22:33:44:55 inet addr:192.168.1.2 Bcast:192.168.1.255 Mask:255.255.255.0 UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:333436242 errors:0 dropped:111 overruns:0 frame:0 TX packets:166776007 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:3075863808 (2.8 GiB) TX bytes:462587297 (441.1 MiB) Interrupt:54 Base address:0xb000 lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 UP LOOPBACK RUNNING MTU:65536 Metric:1 RX packets:432 errors:0 dropped:0 overruns:0 frame:0 TX packets:432 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:0 RX bytes:31127 (30.3 KiB) TX bytes:31127 (30.3 KiB) To set new MAC address zybo:~# ifconfig eth0 hw ether 00:11:22:33:44:55 I hope I was helpful.
  48. 2 points
    D@n

    XADC demo

    @Manas, Your problem lies between your top level file and your .xdc file. Basically, your top level file is trying to use pins that are not defined in your xadc file. As a result, Xilinx is finding these pins at your top level undefined, and it is causing an error when you try to build. So basically, the way to use XDC files is ... Download the master XDC file for your board from among the board support files. Comment out any pins you will not be using ('#' starts a comment, the comment continues to the end of the line) Rename any pins from your top level design file in the XDC file whose names don't match, so that the pin names do match between XDC and your top level. For the most part, you can name things in your top level to be anything you want--as long as you then match the names in the XDC file. (It is the XDC file that translates the names within your project to pins on the chip) Now, use that modified XDC file in your project. Dan
  49. 2 points
    D@n

    Analog sensor interfacing with artix7

    @Manas, Is this the sensor you wish to interface to? Looks fairly straightforward. You'll need to run the output voltage through a divider, though, since (if I recall correctly) 5V is too much for the XADC. As I recall, 3.3V is the maximum you would want to put into the XADC. Xilinx discusses more of the external electronics associated with connecting up an XADC in this note. As far as the logic is concerned, you will need to get an equation that translates voltage to PPMs from the sensor manufacturer, and a similar equation that converts counts (i.e. ADC output value) to voltage from Xilinx. Counts to voltage is usually simply a linear scaling between the max voltage and the max ADC value, so that scaling is fairly simple. voltage to parts-per-million (PPM) of a given sensor reading ... well, that's more application specific. Let me know if this isn't enough of a help to get you going, or if not ... where your struggle lies. Dan
  50. 2 points
    Sergiu

    set the PS2 power jumper

    I attached two photos that show where JP6 is located. Simply move the blue jumper to select the desired voltage.