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Showing content with the highest reputation on 06/24/16 in all areas

  1. 2 points
    Bianca

    I want to blink LED

    Hello hilarikas, I just checked again your files and saw some things that I missed last time I looked. I saw that you tried to assign your clock signal and one led. Unfortunately you confused the XDC file with the UCF file. Both UCF and XDC are contraints files. UCF is used with ISE and XDC is used with Vivado. The main difference between them is the syntax. What you tried to do was writing in the XDC the with the syntax from UCF. It won't work. XDC syntax for the clock: ## Clock Signal #set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n #set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p UCF syntax for the clock: ## Clock signal #NET "clk" LOC = "E3" | IOSTANDARD = "LVCMOS33"; (taken from Nexys4 UCF) What you tried to do: ##NET "refclk" LOC = "AD11"; Then, you cannot use the Genesys2 clock like this. It's a differential clock and you'll have to use a primitive to instantiate it. As you can see you have a sysclk_n and a sysclk_p. You'll have to use IBUFG primitive. you can find more information in Xilinx documentation. This primitive will allow you to use the clock. The primitive looks like this: IBUFDS_inst : IBUFGDS generic map ( DIFF_TERM => FALSE, -- Differential Termination IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "DEFAULT") port map ( O => O, -- Buffer output I => I, -- Diff_p buffer input (connect directly to top-level port) IB => IB -- Diff_n buffer input (connect directly to top-level port) ); Where, O is a clock signal you will declare as standard_logic. (Not Port, but Signal) in your case you wanted refclk and I and IB are the two parts of the differential clock. it would look like this: IBUFDS_inst : IBUFGDS generic map ( DIFF_TERM => FALSE, -- Differential Termination IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "DEFAULT") port map ( O => refclk, -- Buffer output I => sysclk_p, -- Diff_p buffer input (connect directly to top-level port) IB => sysclk_n -- Diff_n buffer input (connect directly to top-level port) ); After this when your code and your XDC are ready synthesize your project. Don't generate bitstream just synthesize then open the synthesized design. You'll have to assign that clock to the design, in order to know that is a clock signal. Attached to this post is a word document with a tutorial on how to assign the clock. At the end of this reload your XDC file. You'll have an option on the top where you have the page open and if all works well you'll see that it will add an extra line on the bottom of your XDC. Mine looks like this: create_clock -period 5.000 -name sysclk_p -waveform {0.000 2.500} [get_ports sysclk_p] After you finished, generate your bitstream and put it on the board. Attached here you'll also find an example of a working code that counts on the leds and the correct uncommented XDC file. Best regads, Bianca Asign Clock.docx LED.vhd Genesys2_H.xdc
  2. 1 point
    Hi jophish, It could be possible to use xc3sprog looking at the following website, http://xc3sprog.sourceforge.net/hardware.php. However it is not supported by Digilent, so we can't guarantee that it will work. If you want to continue with xc3sprog I would recommend contacting the software developers. Have you tried using Vivado or Adept? These are both supported by Diligent and have plenty of resources for them. We can provide support when needed as well. lengland
  3. 1 point
    rmp

    Shipping Time for Zedboard

    Hello, I would like to buy a Zedboard but need it to arrive in Milpitus, California in a day. If I order it today (23 Jun) with Fedex Overnight Priority Shipping, will it arrive tomorrow? I would appreciate help from a sales representative. Thank you. Edit: On calling the Digilient office, I was told that the board is available and can be delivered tomorrow.
  4. 1 point
    I tried really hard to avoid coding it for you, but here is code that has the spirit of what you need to do. I haven't tried to compile or debug it, but it should provide a framework that will guide you.... ... the headers and top of the module.... SIGNAL COUNT : INTEGER:=0; SIGNAL I : integer range 0 to 2000; BEGIN -------------------------------------------------------------------------------------- -- I am pretty sure that this will divide the clock by four -------------------------------------------------------------------------------------- PROCESS(CLK, RESET) BEGIN IF RESET='1' THEN COUNT<=0; TEMP<='0'; ELSIF RISING_EDGE(CLOCK_50) THEN COUNT<=COUNT+1; IF COUNT=1 THEN TEMP<=NOT TEMP; COUNT<=0; END IF; END IF; CLK_OUT<=TEMP; END PROCESS; PROCESS(CLK,RESET) BEGIN IF RESET='1' THEN I <=0; ELSIF RISING_EDGE(CLOCK_50) THEN IF I < 5 THEN IF(KEY(0)='1' AND TX_BUSY='0') THEN TX_DATA<=SW(7 DOWNTO 0); TX_START<='1'; I <= I+1; ELSE TX_START<='0'; END IF; END IF; END IF; END PROCESS; ... the rest of the code....
  5. 1 point
    Elie Assaf

    Use of two Pmod on ZedBoard

    Hello. I need to use two Pmod on ZedBoard. I already know how to communicate with one Pmod, by building a Vivado project with a Quad SPI IP in the block design, and than pin assigning it to a Pmod connector on the board. Should I use two of such IPs? I tried but I think what I did is wrong, since no connector is "active". Thank you.
  6. 1 point
    While I think hamster found your immediate problem, I would also recommend you avoid the asynchronous reset. Such resets can often have unpredictable results, particularly in large designs. Dan
  7. 1 point
    Elie Assaf

    Use of two Pmod on ZedBoard

    Ciprian, In fact I figured out a solution yesterday and it worked (can be used for two and only two PMods): -Hardware (VIVADO): Use Zynq7 Processing system + AXI QSPI on JA + SPI1 (of the Processing system) on JE (MIO 10:15). -Software (SDK): Initialisation and configuration of an XSpi (for the AXI QSPI), and a XSpiPs (for the PS SPI1), and enabling the SPI instance, transfer with it and then disabling it each time we want to use it. Note that the transfer is for sure done based on the reference manual of each PMod. That was a solution of this problem. But I'm still interested in knowing what was I misunderstanding? I may had think quite wrong in solving this problem. If I had to use multiple PMods, what would be the best solution? I know that an SPI controller can have many slaves. So how to implement and use an SPI interface where the master is the Zynq, and slaves are PMods, where all transfer with Pmods is software-based. When using 2 QSPIs, nothing worked and as D@N said that Vivado is confused. I don't really know how to use a QSPI with multiple slaves since only select slave is being extended to a vector, how can I connect MISO, MOSI and SCK to several Pmod connectors. The same was for PS SPIs with multiple slaves. When using PS SPI controllers with PL PMods, problems in transfer occurred (I guess because of the frequency difference between master and slave, so how to use PS SPI controllers with PL PMods). I think that I am missing something. It would be great to have clear answers of above questions. Thank you for being interested.