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  1. 5 points

    WaveForms beta download

    3.11.4 digilent.waveforms_beta_v3.11.4_64bit.exe Added: - Scope: - set/reset zero offset in each channel option - precision option for measurements Fixed: - Script: access to traces and channels from Instrument.Export - unit conversions V to Ṽ, A to à - I2S 32 bit data 3.11.3 digilent.waveforms_beta_v3.11.3_64bit.exe digilent.waveforms_beta_3.11.3_amd64.deb digilent.waveforms_beta_3.11.3.x86_64.rpm Fixes 3.11.2 digilent.waveforms_beta_v3.11.2_64bit.exe digilent.waveforms_beta_3.11.2_amd64.deb digilent.waveforms_beta_3.11.2.x86_64.rpm Added: - Spectrum, Network and Impedance Analyzer store time data when this view is open Fixed: - runscript argument - loading of docked views geometry 3.11.1 digilent.waveforms_beta_v3.11.1_64bit.exe digilent.waveforms_beta_3.11.1_amd64.deb digilent.waveforms_beta_3.11.1.x86_64.rpm Added: - Scope: out of range warning in measurements - Protocol/UART: - support up to 32bit/word - TX/RX format: text, binary, decimal, hex - Wheel Direction option - Logic Analyzer: option to swap previous/next events - Spectrum Analyzer: allowing higher number of BINs for CZT 3.10.7 digilent.waveforms_beta_v3.10.7_64bit.exe Added: - Spectrum: logarithmic magnitude scale for voltage units - Protocol: datetime stamp for SPI/I2C Spy Fixes 3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom mathematic channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Netowrk Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.
  2. 4 points

    HDMI input for Nexys Video.

    I've finally got my HDMI input project to a point where I have something to show. This little picture makes me really happy: This project does the following actions: Advertise HDMI support over EDID/DCCReceive the TMDS signalsDe-serialize them into 10-bit symbolsAlign the symbols using bitslipsTune the input delays for best receptionConvert the TMDS symbols into data valuesExtract CTL, Aux Data Periods (ADPs) and Video Data Periods (VDPs)Extract Video Infoframes from the ADP dataExtract Audio Samples from the ADP data.Extract Raw Pixels from the VDPsPerform 422 to 444 conversion, if required by video formatPerform YCbCr to RGB conversion, if required by video formatConvert Studio Level RGB to Full Range RGB, if required by video formatConvert Audio smaples to a relative db levelOverlay Audio level meters over the video streamConvert the video stream and sync signals back to TMDS symbolsSerialize them through a 10:1 serialisersTransmit the TMDS.I think that this is an awesome base for any video experimentation. I've even got to the trouble of making a GitHub repo for it: https://github.com/hamsternz/Artix-7-HDMI-processing Please feel free to fork and extend.
  3. 4 points

    Petalinux on Genesys 2!

    Hi All, On http://www.iwans.net/xilinx/ I placed a comprehensive manual on how to run Petalinux on a Digilent Genesys 2 board. Board files made in Vivado 2016.2 are included, but at the moment only the USB UART, on-board GPIO (LED's and buttons) and 1 GBit Ethernet are supported. Iwan
  4. 4 points

    Add board to ISE

    Hi, You can add your own board following the steps: 1. Go to ..\Xilinx\14.7\ISE_DS\EDK\board\Xilinx\boards 2. Create a folder board 3. In your folder board create "data" folder 4. Create a .xbd file 5. Open this file and edit with the necessary parameters For example, I add a Nexys4 board. The path for the Digilent_Nexys4.xbd file, in my case is: C:\Xilinx\14.7\ISE_DS\EDK\board\Xilinx\boards\Digilent_Nexys4\data The file content is: ATTRIBUTE VENDOR = Digilent ATTRIBUTE NAME = Nexys4 ATTRIBUTE REVISION = B ATTRIBUTE SPEC_URL = www.digilentinc.com ATTRIBUTE CONTACT_INFO_URL = http://www.digilentinc.com/Support/Support.cfm ATTRIBUTE DESC = Digilent Nexys4 Evaluation Platform ATTRIBUTE LONG_DESC = '-' BEGIN FPGA ATTRIBUTE INSTANCE = fpga_0 ATTRIBUTE FAMILY = artix7 ATTRIBUTE DEVICE = xc7a100t ATTRIBUTE PACKAGE = csg324 ATTRIBUTE SPEED_GRADE = -1 ATTRIBUTE JTAG_POSITION = 1 END Please see the result: Best regards, Cristian
  5. 4 points
    Hi Arvy, Here is some code I wrote tonight. It includes the XADC instance, set to measure channel 6 in unipolar mode. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; Library UNISIM; use UNISIM.vcomponents.all; entity xadc_test is Port ( clk100 : in STD_LOGIC; led : out STD_LOGIC_VECTOR (15 downto 0); JXADC : in STD_LOGIC_VECTOR (7 downto 0)); end xadc_test; architecture Behavioral of xadc_test is signal reading : std_logic_vector(15 downto 0) := (others => '0'); signal muxaddr : std_logic_vector( 4 downto 0) := (others => '0'); signal channel : std_logic_vector( 4 downto 0) := (others => '0'); signal vauxn : std_logic_vector(15 downto 0) := (others => '0'); signal vauxp : std_logic_vector(15 downto 0) := (others => '0'); begin led <= reading; ----------------------------------- -- Pass through the analogue inputs ----------------------------------- vauxp(6) <= jxadc(0); vauxn(6) <= jxadc(4); vauxp(14) <= jxadc(1); vauxn(14) <= jxadc(5); vauxp(7) <= jxadc(2); vauxn(7) <= jxadc(6); vauxp(15) <= jxadc(3); vauxn(15) <= jxadc(7); XADC_inst : XADC generic map ( -- INIT_40 - INIT_42: XADC configuration registers INIT_40 => X"9000", -- averaging of 16 selected for external channels INIT_41 => X"2ef0", -- Continuous Seq Mode, Disable unused ALMs, Enable calibration INIT_42 => X"0800", -- ACLK = DCLK/8 = 100MHz / 8 = 12.5 MHz -- INIT_48 - INIT_4F: Sequence Registers INIT_48 => X"4701", -- CHSEL1 - enable Temp VCCINT, VCCAUX, VCCBRAM, and calibration INIT_49 => X"000CC", -- CHSEL2 - enable aux analog channels 6,7,14,15 INIT_4A => X"0000", -- SEQAVG1 disabled all channels INIT_4B => X"0000", -- SEQAVG2 disabled all channels INIT_4C => X"0000", -- SEQINMODE0 - all channels unipolar INIT_4D => X"00CC", -- SEQINMODE1 - all channels unipolar INIT_4E => X"0000", -- SEQACQ0 - No extra settling time all channels INIT_4F => X"0000", -- SEQACQ1 - No extra settling time all channels -- INIT_50 - INIT_58, INIT5C: Alarm Limit Registers INIT_50 => X"b5ed", -- Temp upper alarm trigger 85°C INIT_51 => X"5999", -- Vccint upper alarm limit 1.05V INIT_52 => X"A147", -- Vccaux upper alarm limit 1.89V INIT_53 => X"dddd", -- OT upper alarm limit 125°C - see Thermal Management INIT_54 => X"a93a", -- Temp lower alarm reset 60°C INIT_55 => X"5111", -- Vccint lower alarm limit 0.95V INIT_56 => X"91Eb", -- Vccaux lower alarm limit 1.71V INIT_57 => X"ae4e", -- OT lower alarm reset 70°C - see Thermal Management INIT_58 => X"5999", -- VCCBRAM upper alarm limit 1.05V INIT_5C => X"5111", -- VCCBRAM lower alarm limit 0.95V -- Simulation attributes: Set for proper simulation behavior SIM_DEVICE => "7SERIES", -- Select target device (values) SIM_MONITOR_FILE => "design.txt" -- Analog simulation data file name ) port map ( -- ALARMS: 8-bit (each) output: ALM, OT ALM => open, -- 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram OT => open, -- 1-bit output: Over-Temperature alarm -- STATUS: 1-bit (each) output: XADC status ports BUSY => open, -- 1-bit output: ADC busy output CHANNEL => channel, -- 5-bit output: Channel selection outputs EOC => open, -- 1-bit output: End of Conversion EOS => open, -- 1-bit output: End of Sequence JTAGBUSY => open, -- 1-bit output: JTAG DRP transaction in progress output JTAGLOCKED => open, -- 1-bit output: JTAG requested DRP port lock JTAGMODIFIED => open, -- 1-bit output: JTAG Write to the DRP has occurred MUXADDR => muxaddr, -- 5-bit output: External MUX channel decode -- Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0] VAUXN => vauxn, -- 16-bit input: N-side auxiliary analog input VAUXP => vauxp, -- 16-bit input: P-side auxiliary analog input -- CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs CONVST => '0', -- 1-bit input: Convert start input CONVSTCLK => '0', -- 1-bit input: Convert start input RESET => '0', -- 1-bit input: Active-high reset -- Dedicated Analog Input Pair: 1-bit (each) input: VP/VN VN => '0', -- 1-bit input: N-side analog input VP => '0', -- 1-bit input: P-side analog input -- Dynamic Reconfiguration Port (DRP) -- hard set to read channel 6 (XADC4/XADC0) DO => reading, DRDY => open, DADDR => "0010110", -- The address for reading AUX channel 6 DCLK => clk100, DEN => '1', DI => (others => '0'), DWE => '0' ); end Behavioral; And here is the XDC file for the Basys3: set_property PACKAGE_PIN W5 [get_ports clk100] set_property IOSTANDARD LVCMOS33 [get_ports clk100] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk100] ## LEDs set_property PACKAGE_PIN U16 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] set_property PACKAGE_PIN E19 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] set_property PACKAGE_PIN U19 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] set_property PACKAGE_PIN V19 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] set_property PACKAGE_PIN W18 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] set_property PACKAGE_PIN U15 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] set_property PACKAGE_PIN U14 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] set_property PACKAGE_PIN V14 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] set_property PACKAGE_PIN V13 [get_ports {led[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] set_property PACKAGE_PIN V3 [get_ports {led[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] set_property PACKAGE_PIN W3 [get_ports {led[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] set_property PACKAGE_PIN U3 [get_ports {led[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] set_property PACKAGE_PIN P3 [get_ports {led[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] set_property PACKAGE_PIN N3 [get_ports {led[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] set_property PACKAGE_PIN P1 [get_ports {led[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] set_property PACKAGE_PIN L1 [get_ports {led[15]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] ##Pmod Header JXADC ##Sch name = XA1_P set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] ##Sch name = XA2_P set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] ##Sch name = XA3_P set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] ##Sch name = XA4_P set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] ##Sch name = XA1_N set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] ##Sch name = XA2_N set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] ##Sch name = XA3_N set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] ##Sch name = XA4_N set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] When downloaded to your board, the value displayed in binary on the the LEDs should reflect the voltage on Pin 0 if the PXADC. I tested just by pushing some header pins into the PMOD and touching the pin - not exactly a complete test, but enough to show that it does something. NOTE: THE FULL SCALE VOLTAGE FOR THE XADC IS 1V, so some crafty planning might be required to interface to it.
  6. 4 points

    Zybo ZYNQ Beginners help

    I had the same problem and switching the "reset Processor" to "Reset entire system" worked like a charm! Love you guys at Digilent!
  7. 4 points

    Help With A Zybo Video Design

    Hey guy, I got it working with a little help from Sam. To simplify the whole thing, I trimmed out all of the zynq associated blocks since this is project isn't using the PS and removed the extra XDCs. The DDC channels on the dvi2rgb core need to assigned correctly and it is a bit of a pain. Delete all connectionsright-click DDC Select "make external" open the design wrapper and there should be two signals names "ddc_scl_io" and "ddc_sda_io"modify the Zybo master XDC to reflect those names in the HDMI group. Sam helped me fix the timing errors associated with timing. The fix was to comment out comment out this the create_clock line in "dvi2rgb.xdc". The new file should look like this: The issue is that the "create_clock" command is forcing the TMDS_Clk_p to be a frequency that cannot be supported by FPGA on the Zybo causing the timing error. Removing it allows the solution in the TMDS clock generate work. Finally, change the clocking wizard block to be in the PLL instead of the MMCM. The dvi2rgb core uses an MMCM and the clocking wizard wants to use a MMCM but there is only one MMCM in that section of the FPGA so tell the clocking wizard to use a PLL. I uploaded working directory to my github: here Hope this helps! Marshall
  8. 3 points

    Digital Twin

    Hi @Kris Persyn, It depends on how you manage your resources, driving immersive visuals on a HDMI display can be done in multiple ways at different resolutions, some are PL taxing others are DDR taxing; you could generate entire frame buffers in PL or PS or you could find a optimal algorithm to change just the previous frame or you could allocate a high number of frame buffers and then run them in a loop. It also depends on how math lab synthesizes the IP you will need to add to your design. If you design your project properly and don't aim for a resolution higher more 720p( I'm being conservative, we managed to drive the HDMI at 1080p with processing filters without a problem) I think it should be enough for what you want to do, resource wise. My suggestion, download and install Vivado, download and install the board files, create and implement your project look at the resource consumption and then buy a board. - Ciprian
  9. 3 points
    In your constraint file, the ddc pins have lowercase "ddc_scl_io" and "ddc_sda_io". Your block design has the port in uppercase "DDC". The case must match. Try editing your constraint file to have "DDC_scl_io" and "DDC_sda_io".
  10. 3 points

    pmod wifi

    Hi @harika, I believe the HTML web page error is related to the materials on the SD card. 1) Please attach a screen shot of the contents of the Sd card you are using. 2) Please follow the YouTube video here from about 6 minutes and 28 seconds on for how to set up the HTTP server project. Make sure to update the login an password for the router/modem you are using. thank you, Jon
  11. 3 points

    Adept SDK C# Library

    This is a little DLL I wrote using C++ Interop in Visual Studio to pull some of the functions from the Adept SDK into C#. I'm posting it here in the hopes this is useful to someone else. It's pretty rough as I am absolutely not a Windows developer and I make no guarantees as to how well it is written and/or works (it does do what I need it to do ). Only supports basic DEPP functions as that's all I needed, other functions shouldn't be too hard to add at this point. Released under the BSD license. https://bitbucket.org/orslmontana/digilent-adept-clr-dll/
  12. 3 points
    @thobie, the bare-metal purchase option for the Zybo was done to enable a lower price point for those who do not require the accessories. For the rest of our customers, adding the Accessory Kit is recommended during the purchase process. You are not the first and the last to complain about version compatibility. It is economically unfeasible for us to update all support projects, IP and support packages provided for free four times per year for each Vivado version. Instead we made a commitment to consider the last Vivado release in each year stable and do a once-a-year update cycle. In that regard, 2017.4 is the version we are upgrading projects to. There is a question whether OOB designs should be updated at all, or kept at the version which generated the binary image shipped with the board. The board presets are not versioned for Vivado (no version-specific releases in our git repo), because these should be forward-compatible with Vivado versions. The critical warning itself related to CK-to-DQS delays being negative appears starting with 2017.4. The negative values are due to CK trace being shorter than any of the four DQS traces. In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Zybo was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Zybos shipped to customers are functionally tested and pass the DDR3 calibration process. Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. Since these delays are board-dependent, we would need to re-design the board to make the delay positive. This is impossible with the current form-factor. Another option would be modifying the board preset file and forcing a zero value instead of the actual delay. The tools seem to be using zero anyway for calibration. This will have to be thoroughly verified first.
  13. 3 points
    Hello, I've posted the next part in my FPGA graphics series using the Arty + VGA Pmod or Basys 3. It shows you how to make use of double buffering to animate sprites using simple Verilog. https://timetoexplore.net/blog/arty-fpga-vga-verilog-03 Feedback very welcome, Will PS. I'll add the source to GitHub shortly.
  14. 3 points
    An FPGA can be a useful "swiss army knife", but all the nice features aren't easily accessible. Enter "LabToy": A batteries-included collection of utilities, just double-click and go. As the name implies, this isn't meant to compete against "real" test equipment. The main selling point is like a pocket knife - this fits into a shirt pocket and the power tools don't. And speaking of "selling points", it's free to use. So what do we have here: - Digital data: Shows the input state of all pins - Analog data: Readings from the two ADCs, up to about 700 ksps sustained (XADC "simultaneous sampling" mode, phase-accurate between channels) - Streaming data logger: Both analog and digital data can be written to a .vcd file, to be shown in gtkwave. There is no limit to the capture length. - Analog signal generator: 8 fully independent channels, sine, square wave, the usual suspects. Well, the DACs won't win any audiophile awards, but they are usable. - "Programmable" digital LED mode: Configurable pulse width to suppress short glitches, or edge detect with a built-in pulse generator to highlight them. - Analog LED mode: Shows the input value of the ADC in real time Some screenshots: 1k sine / cosine from DAC jumpered to ADC (in gtkwave) The digital signal is the generator's sync output that can be recorded as a digital input. Realtime display of the inputs. With pocket knives in mind ("this button will unlock the large blade, allowing it to be manually returned to its folded position") I decided to keep the screen uncluttered and put descriptions into tooltips. The large displays are the average voltage readings from the ADC. The smaller ones show the digital inputs in groups of four. Generator controls (frequency, minimum voltage, maximum voltage, phase). The voltage scaling is a bit unusual (typically there is "AC magnitude" and "DC offset") but I chose this approach because it shows clearly the limitations of the 0..3.3V output range. Most people will probably leave all this at the default values for a full-scale signal. Data capture Example: The output in gtkwave after I touched a jumper cable to the digital inputs on the DIL connector. +++ DO NOT USE THE +5V OUTPUT P24 FOR THIS KIND OF TEST +++ (3.3 V is available on the PMOD connector, bottom row) The red "undefined" marks flag the first input in an 8-bit group. In this example, they aren't too meaningful, but they can alert me to the fact that no data events have been observed yet. LED control The two numbers give the number of consecutive 1 or 0 samples (at 125 MHz) before a signal change is propagated to the LED. E.g. put 125 million there and it'll take one second after changing the input state for the LED to light / go dark. Those can be used interactively to study an unknown signal. "Level": no further processing ("level" mode and 1 / 1 sample counts is equivalent to directly connecting the LED to the physical input) "Edge" mode generates a brief pulse on signal changes, the LED is dark otherwise. "Invert" flips the input right next to the pin (0 becomes 1, black becomes white and man gets himself killed on the next zebra crossing -DA). How to get it: The file is attached: labToy0v1_beta.exe The installer unpacks a single .exe. Happy hacking! Requirements: Windows 64 bit (!) .NET 4.5 FTDI libraries CMOD A7 35 T (not 15 T). Warnings: Direct access to digital IO pins is an inherently dangerous activity. "PROVIDED WITHOUT WARRANTY OF ANY KIND" means Just That. And beware of the +5V pin. PS: If you try it, kindly let me know whether it works, or what goes wrong.
  15. 3 points

    Using script with Spectrum on AD2

    Hi @tomtektest, @abzza With WaveForms Script THD and other measurement logging and plotting can be automated, like this: function doTHD(){ var rgTHD = [] var rgFreq = [] for(var idx = 1; idx <= 100; idx++){ Wavegen1.Channel1.Simple.Frequency.value = 1000*idx Wavegen1.run() // start AWG wait(0.01) // settle time for the external circuit, expressed in seconds Spectrum1.Frequency.Stop.value = 20*Wavegen1.Channel1.Simple.Frequency.value // adjust analyzer stop frequency Spectrum1.single() // start acquisition if(!Spectrum1.wait()){ // wait to finish return; } rgFreq.push(Spectrum1.Trace1.measureFreq("FF")) rgTHD.push(Spectrum1.Trace1.measure("THD")) } Wavegen1.stop() print(rgFreq, rgTHD) // print data for copy paste // draw in plot1, View / Add plot plot1.X.Units.text = "Hz" plot1.Y1.Units.text = "dBc" plot1.X.data = rgFreq plot1.Y1.data = rgTHD } doTHD();
  16. 3 points

    Rants about FPGA tool chain(s)

    @D@n , Here's a secret; I'm whispering because this is just between you and me: At places where they do a lot of quality FPGA development work no one ever brings up a GUI for anything. All of the toolchain invocation is done using Perl and TCL/TKL. Shhhh. Don't tell anyone....
  17. 3 points
    A few reasons are... a - The introduction of logic hazards can cause glitches : https://en.wikipedia.org/wiki/Hazard_(logic) b - Routing of clocks is very complex - It is hard to ensure that the same clock edge appears all over the FPGA at almost exactly the same time. Sometimes this is achieved with 'slight of hand' (e.g. using a on-chip PLL to advance phase of the clock, so that by the time it reaches the edge of the chip is in back phase with the original signal). Low-skew paths also exist, but are restricted to small areas of the FPGA, and the clock has to be connected to the correct pin to be placed and routed correctly. c - FPGAs and their tools are designed to behave predictably under the "synchronous digital design" paradigm (something like https://hps.hs-regensburg.de/scm39115/homepage/education/courses/red/2_SynchronousDigitalCircuitDesignRules.pdf). If you work outside the paradigm you will be fighting against the tools and their assumptions. d - There is almost nothing that you are unable to code in an FPGA friendly way, but there are infinitely many ways to write FPGA-hostile code. If you want your FPGA to place nice with you, you have to play nice with it. So you can either add an RC filter to debounce you switch, or you can sample it using a reliable clock.
  18. 3 points

    Just for fun: Frequency Resolution challenge

    Hello everybody! Since I was sharing this image with others, I thought I'd share it here at Digilent as well. The attached image shows the frequency response of several FFT windows, including the well-known rectangle and Hanning windows. The blue window is one I've put together, but haven't shared the FPGA source code used to implement it. I challenge anyone to do better. Oh, and one other comment ... all but the Hanning window can be used in an invertible FFT process. Dan
  19. 3 points

    OpenScope Mechanical STL Files

    Printed out on the Form Labs at my local TechShop.
  20. 3 points

    Cmod A7 35T GPIO demo Error

    Hi @coloradosensors, I just generated bitstream on this project in Vivado 2015.4. You need to right click on the clocking wizard and remove it. Then under project manager click on ip catalog and re-add the clocking wizard with default settings. This will fix your issues with using an older version of Vivado for this project. cheers, Jon
  21. 3 points

    Lots of fun UART testing code

    Hello Digilent Community! I just finished putting the finishing touches on a UART demonstration project that you can find here. The project was originally intended to share a C++ class that could work with Verilator to prove that anyone's UART implementation was working. However, after I got into it, I realized the project had a lot of value that others might appreciate. As an example, consider this post by @martin16. Had he used any of the testing mechanisms listed below, he might have known which side of the RS232 port he was working with was at fault. The core contains a complete implementation of both a transmit and receive UART encoder/decoder. These can be easily taken from my project and placed within your own. (Subject, of course, to the limits of the GPL v3) The core also contains a (fairly) generic FIFO implementation. For those wondering how to implement a FIFO, you may find this valuable as well. For those who would rather interact with a serial port over a bus, such as the wishbone bus, there are two approaches within the project that can be used to hook it up to a wishbone bus. One can be used within a larger wishbone slave module, the second as a standalone module. Both are Wishbone B4 compliant, and both use the pipeline mode--allowing you to read/write multiple values on consecutive clocks from/to the controller. Of course, this only really makes sense when using the FIFO. Those might be valuable enough on their own, but you can probably find without too much additional work other implementations of the above. Therefore this project includes some even more valuable files: It includes a series of test programs/configurations that can be used to determine if the hardware on your board is working properly. If you are like me, you've struggled every time you've tried to get a serial port working on a new board. Should you connect your output to the TX or to the RX line? Do you have the UART set up properly, at the right baud rate? Can you handle more than just single values at once? How fast can you transmit/receive? To help you answer these questions, the project file contains the following test configurations: Hello World: You know, that old fashioned hello world program? I would recommend trying this program on your board after you can blink an LED at your favorite rate, or equivalently after you know that your clock works. This particular project is so simple that it depends upon only the clock input and the UART transmit output. Getting this program running on your board will demonstrate that you understand your clock, and that you can modify your I/O constraint file properly, and that you know how to connect a terminal program to your board in order to observe the results. Line Test: Once you've got a hello world program running, so that you know the output UART pin works, then it is time to test the input UART pin. This is the purpose of the line test testing program. It works by reading a line of data (either until a newline or 80--characters), and then dumping that line to the output. (Don't forget to turn off hardware flow control, and be aware of the differences between a new line and a carriage return!) SpeechFifo: Finally, there's a program that can be used to test the FIFO capabilities found within the wishbone UART peripheral. This program uses the FIFO capability to make certain the transmitter stays fully loaded for over a thousand characters of output bytes. (No, this isn't computer speech generation, but rather a computer dumping a Abraham Lincoln's Gettysburg Address across the UART port.) Each of these configurations has a corresponding Verilator simulation file associated with it, allowing you to simulate the functionality within them as part of Verilator. The project includes, like I mentioned above, a C++ class that can be used to determine if your own UART is transmitting correctly under a Verilator simuation. This class can also be used generate UART signaling in order to test if your RTL can receive it properly. (See the line test C++ harness discussed below for an example of this.) As complements to each of the testing configurations above, the project contains C++ files to drive each of those within a Verilator context. Some unique features include: The Line Test C++ test harness automatically generates a linetest.vcd file that can be used together with GTKwave to study how the core works. Further, it can be run in either an interactive or an automated mode. The Speech Test C++ test harness can be used in an automated mode, or with the -i switch in a more interactive mode. In this latter mode, the speech test program generates a speechtrace.vcd file that can be used with GTK wave to understand how the UART transmitter, FIFO, the wishbone bus decoder, or even the test harness itself. I hope you find these as valuable as I have. Please feel free to post any questions or comments you might have about this project below. Dan
  22. 3 points

    Birth of an OpenScope!

    We got a series of photos of the OpenScope going through the manufacturing line. Unfortunately, Kickstarter didn't allow me to load all of them onto the update.
  23. 3 points

    Nexys 4 DDR

    @gnicholls, Wow, what a good and thorough question. You've hit the nail on the head, and you are asking something a lot of users are asking. So in answer, may I reply, Welcome to the wonderful world of FPGA design! DDR memory is hard. I mean, really hard. I tried for about two solid months to get a DDR3 memory up and running, and eventually moved on because it was taking too much time to do. You can still find the project here, though--and I still hope to return to it--eventually. Xilinx has written a variety of App notes describing how they've gone about creating their reference solution. For 7-series devices, you can find their note here--but it just doesn't tell you much. I've found the most useful information in their note from a couple generations back, found here for a Virtex-5. Bottom line: it's *really* hard--most people only use the reference solution, and then make the reference solution work for their design. I love the examples found at fpga4fun.com. They tend to work through many of the basic I/Os that FPGAs need to work with, and how to build controllers for each of them. Another useful website is Asic-World--it's just not one I've ever gotten into. Xilinx has tried to make your problem easier with their platform studio and now its Vivado replacement--allowing you to connect via point and click various different Xilinx components together to make one of many (fairly) pre-canned designs. Many of the Digilent based "tutorials" or "examples" are of this type. I personally find them wanting, for many reasons: They are "too easy"--offering you no insight for how they are accomplished internally. They are so much of a black box that you cannot examine what they did or how they did it in order to modify it, debug it, or even learn from it. It can be difficult to integrate your own work with their components. They are all focused on how to use someone else's components, but offer little in the way of teaching you how to build your own. In the end, they leave you stuck with Xilinx solutions. Any components you create/develop will only ever work with Xilinx. This leaves you forever wedded to the Xilinx platform, or forced to relearn all you have learned. Verilog (and <gasp> even VHDL) is a better language than that--capable of doing a lot more. And if that's not enough, your design that works with one version of Vivado may well break when the next one comes out because ... they changed something. (This is an ongoing problem, and a thorn in Digilent's side--suggestions are always welcome.) I have personally been trying to work to create somewhat of a solution to your problem, but I'll admit my own designs are perhaps far from the professor's materials that you are looking for. You can find many of my Verilog designs on github here. A recent design I've put together for both beginners and more experienced types alike can be found here. It contains examples of how to create a serial port, both transmitter and receiver, together with some top level designs that use such a port. As the task of figuring out which pin is which on any board is fairly common--even among experienced users, these offer examples you can work with to make sure you have your serial port working. My efforts have gone so far as to even build my own CPU, flash controller(s), SD-card controller, GPS controller, real-time clock, 7-segment controller, FFT, VGA controller, etc. I mean, why when you buy a board would you only learn to work with some of it, right? You can find a fairly complete design here, using a CMod-S6, that places a CPU onto the S6 with a minimal multi-tasking "operating system". I'm also working on a more complicated design for the Arty here--this one uses the Xilinx generated MIG DDR3 SDRAM, such as you have on your Nexys 4 DDR. This design is currently somewhat on hold, as I am trying to update the CPU within it to a more mainstream CPU that will even support the C-library. (Today's success: I managed to get newlib to compile for it! This is after updating the assembler, linker, GCC compiler backend, etc.) If you are a hard-core VHDL type, Xess.com has put together a fascinating library of VHDL routines to demo how to use their boards. To my knowledge though, the tutorial information within their libraries is ... a bit harder to follow than the simple point and click designs Xilinx peddles. One of the things I've noticed about many (most, all?) of the more complicated FPGA designs I've come across is that they all depend upon some form of internal bus by which things can be connected. Once you get past learning about how to build the simple peripherals fpga4fun wishes to teach you, you're next step is really to learn about that bus structure. Why? If for no other reason than memories seem to be best accessed via a bus, so anything using a DDR type of memory tends to send its requests over a bus. This can easily become a bottleneck to your design, but ... it sort of comes with the territory. You can build other memories and distribute them throughout your FPGA, but the amount of block RAM memory you will get within any FPGA tends to be ... never enough. Hence you are often stuck with the external memory chip(s). Xilinx uses the AXI bus protocol. You can find the specification for it here. I haven't found any good tutorials on how to use it, but there's a way you can get Vivado to generate a sample AXI-lite design that you can interface with. (I can google it if you are interested--I just don't have it at my fingertips.) I've personally used the Wishbone Bus protocol, version B4, pipelined mode. Many others use version B3. I find that I can transfer data 3x faster using B4. To get from the Wishbone Bus to a DDR memory, controlled via Xilinx's Memory Interface Generated AXI controller, I built a wishbone-AXI bridge. Others of these also exist. There's an open source package manger out there called fusesoc which was designed to facilitate composing solutions from many different FPGA components together. In particular, the OpenRISC team has put a lot of work into making sure their CPU's, peripherals, and board designs can be built using this package manager. (These tend to connect to each other via the wishbone B3 standard.) If you dig into this, you can probably find many, many examples of working peripherals for various boards--although that community does tend to focus more on the Altera boards than the Xilinx boards, and Verilog more than VHDL. So ... when I build a new design, how do I do it? For every board of Digilent's that I have bought, I start with the reference page, look up the schematic to see how the components are connected, and then google the part numbers on the schematic. Those will contain the instructions you need to access the various chips on your board. They are usually where things pick up next after you leave the canned tutorials and examples. I hope I haven't overwhelmed you, but really ... where you go next is up to you. What would you like to do? Dan P.S.: My favorite description of RTL design for those who know nothing about FPGA's is, "Infuriatingly complex in its simplicity." Everything you do will be simple--like the clock divider. But too many of these very "simple" components can become so complex that it very quickly gets under your skin.
  24. 3 points
    prince, I recently ran into the same issue. You can follow this tutorial to put your program in the flash. BKallaher
  25. 3 points

    I want to blink LED

    Hello hilarikas, I just checked again your files and saw some things that I missed last time I looked. I saw that you tried to assign your clock signal and one led. Unfortunately you confused the XDC file with the UCF file. Both UCF and XDC are contraints files. UCF is used with ISE and XDC is used with Vivado. The main difference between them is the syntax. What you tried to do was writing in the XDC the with the syntax from UCF. It won't work. XDC syntax for the clock: ## Clock Signal #set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n #set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p UCF syntax for the clock: ## Clock signal #NET "clk" LOC = "E3" | IOSTANDARD = "LVCMOS33"; (taken from Nexys4 UCF) What you tried to do: ##NET "refclk" LOC = "AD11"; Then, you cannot use the Genesys2 clock like this. It's a differential clock and you'll have to use a primitive to instantiate it. As you can see you have a sysclk_n and a sysclk_p. You'll have to use IBUFG primitive. you can find more information in Xilinx documentation. This primitive will allow you to use the clock. The primitive looks like this: IBUFDS_inst : IBUFGDS generic map ( DIFF_TERM => FALSE, -- Differential Termination IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "DEFAULT") port map ( O => O, -- Buffer output I => I, -- Diff_p buffer input (connect directly to top-level port) IB => IB -- Diff_n buffer input (connect directly to top-level port) ); Where, O is a clock signal you will declare as standard_logic. (Not Port, but Signal) in your case you wanted refclk and I and IB are the two parts of the differential clock. it would look like this: IBUFDS_inst : IBUFGDS generic map ( DIFF_TERM => FALSE, -- Differential Termination IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "DEFAULT") port map ( O => refclk, -- Buffer output I => sysclk_p, -- Diff_p buffer input (connect directly to top-level port) IB => sysclk_n -- Diff_n buffer input (connect directly to top-level port) ); After this when your code and your XDC are ready synthesize your project. Don't generate bitstream just synthesize then open the synthesized design. You'll have to assign that clock to the design, in order to know that is a clock signal. Attached to this post is a word document with a tutorial on how to assign the clock. At the end of this reload your XDC file. You'll have an option on the top where you have the page open and if all works well you'll see that it will add an extra line on the bottom of your XDC. Mine looks like this: create_clock -period 5.000 -name sysclk_p -waveform {0.000 2.500} [get_ports sysclk_p] After you finished, generate your bitstream and put it on the board. Attached here you'll also find an example of a working code that counts on the leds and the correct uncommented XDC file. Best regads, Bianca Asign Clock.docx LED.vhd Genesys2_H.xdc
  26. 3 points

    Is there an arty drawing available?

    Hi Gra, Please see the document attached. Best regards, Bianca Arty Dimensions.pdf
  27. 3 points
    Hello, The 16 inch cable length limitation of USB 2.0 is for data transmission signal integrity. In case you need more than this you use up to 5 USB hubs. The Analog Discovery needs about 400mA (2W) to function, less than the 500mA USB 2.0 limitation at 5V. Most computers can provide more than 2A without any problem (like external HDDs need this to spin up), having the surge protection above this limit. However long and/or bad quality cables have high resistance and the voltage will drop too much on the device side, below the ~4V minimal requirement for the AD. http://goughlui.com/2014/10/01/usb-cable-resistance-why-your-phonetablet-might-be-charging-slow/ There can be huge differences between cables. The best cable I have is a thin unshielded 6 feet one, some others are thick and looking good but have way more resistance. It seems the plug contact resistance is a very important factor since these can oxidize easily. With a good cable I see 0.1V drop (4.9V), with other bad ones up to 0.8V (4.2V) when using with AD taking 2W. Try using different USB cables, check the device voltage in the WaveForms application status bar. You can also try the Analog Discovery 2 which can be powered from 5V auxiliary supply.
  28. 3 points
    You want to use TMDS_33 - for example: set_property -dict { PACKAGE_PIN Y1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; set_property -dict { PACKAGE_PIN W1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; set_property -dict { PACKAGE_PIN AB1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; set_property -dict { PACKAGE_PIN AA1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; set_property -dict { PACKAGE_PIN AB2 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; set_property -dict { PACKAGE_PIN AB3 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; (this is from an Artix 7 project for the Nexys Video, so you will have different pin locations - but you get the gist - it is TMDS_33)
  29. 3 points

    Extra GPIO on Nexys Video

    Check out this one: http://www.xilinx.com/products/boards-and-kits/hw-fmc-xm105-g.html It is still not the best priced card at $159, but it is cheaper than the one you found on trenz. We have wanted to do a cheap fmc breakout for a while now, but haven't been able to get around to it yet. Sorry we couldn't help out by having one available now edit: it looks like you could also inquire about this board here: http://www.kayainstruments.com/fmc-prototype-board/
  30. 3 points

    Reprogram (reset) FPGA

    Actually, resetting/reprogramming the FPGA from within the internal logic of the FPGA isn't as hard as it sounds--once you figure out how to do it. Check out the project wbicapetwo at opencores. On there you'll see a core that can be used to access the internal ICAPE2 port within a series 7 FPGA. I use it on my Basys-3 board (w/ Artix 7 FPGA) to reset the board from internal logic. All it takes is to write a 15 (IPROG) to the command address, 0x04. The FPGA will then reload its configuration. Should you wish to load an alternate configuration, load the address of that alternate configuration on your flash into the WBSTAR register, found at address 0x010, and then issue the IPROG command. You can find further documentation from Xilinx. However, Xilinx's manual is sparse on the timing of this operation, and the core at opencores resolves that. D@n
  31. 3 points

    Reprogram (reset) FPGA

    Hi Alexis, Unfoortunately, the program_b pin is only tied to the PROG button, and not to the FPGA. You can drive it with a Pmod port very easily though. Just take a wire and stick it under one of the bottom two feet on the PROG button. Put the other end into a Pmod port. In your .XDC file for your project, add a pullup to the port. set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP TRUE} [get_ports { ja1 }]; Now you just pull ja1 low when you want to reprogram through QSPI. Make sure JP1 is on QSPI.
  32. 3 points
    Hello, Please open http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug908-vivado-programming-debugging.pdf and go to page 13, chapter Programming Configuration Memory Devices. First of all, you might not need to generate the mcs file, as you can program the QSPI with the bin file, generated when the bit file was generated. For this, you just have to add the Configuration Memory device (explained in the above mentioned document, enter S25FL128 and select the first from the list). Then, program it with the bin file. If you still want to build the mcs file, here is how you can do it: I have used the Nexys4 Basic User Demo, available here: https://reference.digilentinc.com/nexys:nexys4:gpiodemo After generating the Bitstream, I have used the following commands in the TCL script window: - cd <project location> lab1.runs\impl_1 (location where the bit is) - write_cfgmem -format mcs -interface SPIx1 -size 32 -loadbit "up 0x0 Nexys4UserDemo.bit" -file Nexys4UserDemo.mcs Then, the mcs file is created. In order to program, add the Configuration Memory device as explained above, and then program the memory with the mcs file. In the end, please do not forget to power off and back on the board, having MODE switch on QSPI.
  33. 3 points
    I'm working on a design for receving HDMI video and decided to write up my method for tuning the IDELAY and ISERDES settings to sync with the incoming stream. If you are interested, you can find it at http://hamsterworks.co.nz/mediawiki/index.php/SERDES_symbol_locking
  34. 3 points

    Help With A Zybo Video Design

    Hey Run, Where did you get the demo? I would like to see what you are working from. 1. I suspect you just need to change the clocking wizard that feed the dvi2rgb core to 75MHz instead of 200MHz but I cannot be sure without poking around a little. Although, I have only ever used one ucf/xdc file per design so I am wondering if you are having issues with that. I could see how using multiple files could work but I don't have any experience with it. As for your errors, "[Common 17-55] 'set_property' expects at least one object. " error is caused by a mismatch between the defined port in Vivado and the xdc. In this case, I would get rid of the "dvi2rgb.xdc" and the "dvi2rgb_ooc.xdc" files and rely on the zybo master xdc. Then I would change the zybo xdc to match the port names that are attached to the dvi2rgb core. 2. I'll ask around but I think you should have one universal XDC. 3. Make sure to change the XDC to reflect the port names you used. 4. Do you mean you tied them by outputting them to a pin and using a wire to put them to VDD or GND? That isn't a good idea. Those pins are being driven as outputs and driving them to VDD or GND could short them and damage the pins. On inputs that would be fine but I like to tie the signals to a switch or button. On outputs, leave them unconnected. Hope this helps. Marshall
  35. 3 points


    My name is Mike, and I've developed a bit of an obsession with FPGAs. You might be able to find some project ideas or inspiration on my WIki at http://hamsterworks.co.nz/mediawiki/index.php/FPGA_Projects I'm always happy to talk FPGAs, so feel free to drop me an email sometime
  36. 2 points

    PMOD DA1 to zedboard

    Nevermind, i downloaded the digilent board files from https://reference.digilentinc.com/learn/software/tutorials/vivado-board-files/start?redirect=1 and was able to connect the pmod ip via the board tab in ip integrator like it says in the walkthrough
  37. 2 points
    Hi Jon, Just want to give you an update. I got it working using the PL AXI Quad SPI controller after I fixed my IO constraints. And I did contact the Avnet support you mentioned above. Here is the thread if you are interested. Again thank you very much for your help on my project. -Iris
  38. 2 points

    Using script with Spectrum on AD2

    Hi @abzza @tomtektest With WF 3.6.8 you can access Spectrum measurements, like: print(Spectrum1.Trace1.measureFreq("FF")+" Hz") // fundamental frequency print(Spectrum1.Trace1.measure("FF")+" dBV") // magnitude print(Spectrum1.Trace1.measure("THD")+" dBc") // total harmonic distortion
  39. 2 points
    @Sam_a Should be fixed this time. Thanks for your patience, Arthur
  40. 2 points

    LabView Panel VI's for ZedBoard?

    Hi @shawnerz, I moved this thread to the section where more labview oriented forum members look. From my understanding at this point in time, none of the Digilent FPGA boards are compatible with LabVIEW. LabVIEW is able to interact with our microcontroller boards and our instrumentation line and we have VIs to go with them, but not for our FPGAs at this point in time. Let us know if you have any more questions. Thanks,
  41. 2 points

    set the PS2 power jumper

    The blue object is just a convenience for wiring two pins together. You can wire the center pin to the pin on the side you need it wired to, and you'll do just fine. It's just that, when you want to change things, it's a whole lot easier to pick up the blue piece and move it to the next location than it is to remove your wire and wrap it around the new pin you want it connected to. Dan
  42. 2 points

    Student from germany

    Hello Digilent Forums, i'm a german computer-science student and just finished the bachelor to now walk into the master studies. There had been plenty projects in uni to explore FPGAs and we're (the uni) kinda well equiped with boards. I had the opportunity to work with Nexys4 and ZyBo and started a little youtube-channel about SDSoC. The thesis was about building a Vectorgraphicsunit (for displaying 3D on oscilloscopes). The thesis-stuff is published under GPLv3 and i'll get the project up to the project-vault as soon as i can (there's still some github-readme-work to do). Cheers and see you around in the forums, Thorsten Attached is a photo of a 3D Cube on the Oscilloscope (yes, the engine can rotate, scale and move the cube)
  43. 2 points
    Your problem is that block RAM on FPGA's is a limited resource, some would say even a precious resource. Your design over-uses your block RAM. There is only about 16 Mbits of block RAM on your device in total, or about 2MBytes, or equivalently, enough to handle one Mpixel. Your design exceeds this by itself, leaving no room for anything else within your design that might need the same block RAM. What you will need to do instead is to use the DDR3 SDRAM. You will have 1GB available to you with the DDR3 SDRAM. Use the Xilinx Memory Interface Generator to create a configuration for the SDRAM, rather than the BlockRAM interface generator. Let us know how that works, Dan
  44. 2 points
    While I haven't used this memory generator before, it occurrs to me that the singular characteristic of DDR memory is that it clocks data on both rising and falling edge of the clock. I can't be certain, but I can imagine that 400MHz clock is exactly what you are looking for. Dan
  45. 2 points

    HDM In EDID ROM default file?

    Hi Randall, Unfortunately the documentation is not up to date, so I notified someone who can fix that. In order to change the EDIDs, you can download a program (it's a single .exe file) called Phoenix EDID Designer. This gives you a GUI which allows you to change the ****_edid.dat files found in the dvi2rgb_v1_6/docs folder. There's a .cpp script in there that can be run to generate the ****_edit.txt files. These files are then selected in the IP core. I'm not sure, but I think you'll need to overwrite one of the .txt files if you want it to be seen in the IP core.
  46. 2 points
    Hello Andrew, We don't have any such examples. We do test SD and USB in our manufacturing tests, but it does not go as far as knowing anything about files. For both SD and USB Mass-storage you will need file system support. FatFs is a good open-source example. The lower-level drivers are the ones provided by Xilinx and we use them ourselves. For example, reading the first data block on an SD is as simple as: #include "sdps.h" /// Initialize the read buffer memset(arrbyReadBuff, 0, kwBlockSizeBytes); /// Initialize SDIO controller psSdConfig = XSdPs_LookupConfig(XPAR_PS7_SD_0_DEVICE_ID); if (XSdPs_CfgInitialize(&sSdPs, psSdConfig, psSdConfig->BaseAddress) != XST_SUCCESS) { VERBOSE("%s (line %d) error", __func__, __LINE__); FAIL_AND_RETURN; } /// Initialize SD card if (XSdPs_CardInitialize(&sSdPs) != XST_SUCCESS) { VERBOSE("%s (line %d) error", __func__, __LINE__); FAIL_AND_RETURN; } /// Change bus width to 4-bit if (XSdPs_Change_BusWidth(&sSdPs) != XST_SUCCESS) { VERBOSE("%s (line %d) error", __func__, __LINE__); FAIL_AND_RETURN; } /// Issue a read of the first block (boot block) XSdPs_ReadPolled(&sSdPs, 0, 1, arrbyReadBuff);
  47. 2 points
    I think you are right and that the changes are a good idea. I guess you thought of this already but alternatively, perhaps you can detect what version of the library you found and keep looking if it is too old? I did not try any of my other software that might be using the other driver (I guess it could be Arduino/Energia) but I guess something will probably break if I keep it renamed My /usr/local/lib/ has both 0.1.7 and 1.2.2 and uses a symlink that points to 0.1.7. Since you say 1.2.2 should work I will do some experimenting with changing the symlink to point to that version instead in case I find issues with some other software. (Before saw your latest message I was going to ask for a strategy for running Waveforms along with other software that uses that driver..) Finally, thanks a lot for guiding me Michael! You made it really difficult for me to be mad at Digilent for having to spend two weeks just to get this up and running
  48. 2 points

    Moving to Linux

    Speaking of third party solutions, we have an open-source utility for programming Xilinx FPGAs. It starts up and runs faster than the Xilinx tool and only requires libusb in order to run. It works from Linux and Mac. It appears there is a libusb for Windows, so someone could probably get it working on Windows also. We're always happy to see a pull request. https://github.com/cambridgehackers/fpgajtag
  49. 2 points

    Analogshield and arduino due

    Sorry to dig up a old thread. Got things working (at least far enough to get the ramp example working) on a DUE. Don't know what version of the library jvandijk was starting from, but I started from the one @‌ https://www.digilentinc.com/Products/Detail.cfm?NavPath=2,648,1261&Prod=TI-ANALOG-SHIELD however this looks to be same as the master version on mwingerson github. Was running into problems with SPI not being instantiated before analogshield needed it. Also found and fixed a compile issue for the uno (I have both a DUE and an UNO) I signed up for a github account, forked the library from mwingerson, put my changes in and did a pull request. Hope I did the github stuff correctly. First time I've contributed to an open source project. Hope this helps!
  50. 2 points

    Help With A Zybo Video Design

    Dear Chris, 1. Like Run suggested, the error "IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: BiDi RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 2 sites." such kind of problem is caused by one or more unconnected external ports on your block diagram. Please check your diagram first to make sure all unused external ports are deleted. (this problem will occur on both 2014.4 and 2015.1) 2. For the DDC part, the HDMI protocol described it clearly that this is a mechanism to let video transmitter and receiver to communicate which each other. By exchanging information, the transmitter could know the detail configuration(ability) of the receiver part (what resolution, frame rate, format of signal the receiver can process). This is a necessary part in HDMI transmission and can not be ignored or deleted. 3. Currently the problem you encountered is how to synthesis the Bi-Directional inner control ports into a signal Bi-Di external port. To solve this problem, first you should understand what is a bi-di port and its mechanism(I am sure you know it). Secondly, in Xilinx ISE, three bi-di control ports can be easily synthesized together by adding a constrain command in the .ucf file. In vivado the goal can't be achieved by only modify the .xdc. In my way, i directly modified the DVI2RGB ip core, the top_module i mentioned is the top module of the ip core (the dvi2rgb.vhd file). The core is written by VHDL, modify the following: a. In the port description change DDC ports to below -- Optional DDC port DDC_SDA : inout std_logic; DDC_SCL : in std_logic; b. add HPD and CEC port in the end of port def HDMI_HPD : out std_logic; HDMI_OUT_EN : out std_logic c. in the behavioral part add signal def and logic architecture Behavioral of dvi2rgb is ....... signal hpd : std_logic; ....... begin DDC_SCL_I <= DDC_SCL; DDC_SDA <= DDC_SDA_O when DDC_SDA_T = '0' else 'Z'; DDC_SDA_I <= DDC_SDA; HDMI_OUT_EN <= '0'; HDMI_HPD <= hpd; ....... d. in the TMDS_ClockingX call add port "hpd" TMDS_ClockingX: entity work.TMDS_Clocking generic map ( kClkRange => kClkRange) port map ( ......... hpd => hpd ); f. in the TMDS_ClockingX module(vhd file) add "hpd" def. this will active the HDMI transmittion only after the sink core has been locked entity TMDS_Clocking is Generic ( kClkRange : natural := 1); -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5 Port ( ......... hpd : out std_logic); end TMDS_Clocking; architecture Behavioral of TMDS_Clocking is .......... begin hpd <= aDlyLckd; ......... the above is all you need to make this core compatible with HDMI. after modification -> save -> repackage ip core 4. All you need in your project xdc file is really sample if modification has been done inside ip core. below is my xdc set_property PACKAGE_PIN H16 [get_ports HDMI_CLK_P] set_property PACKAGE_PIN H17 [get_ports HDMI_CLK_N] set_property PACKAGE_PIN D19 [get_ports {HDMI_D_P[0]}] set_property PACKAGE_PIN C20 [get_ports {HDMI_D_P[1]}] set_property PACKAGE_PIN B19 [get_ports {HDMI_D_P[2]}] set_property PACKAGE_PIN D20 [get_ports {HDMI_D_N[0]}] set_property PACKAGE_PIN B20 [get_ports {HDMI_D_N[1]}] set_property PACKAGE_PIN A20 [get_ports {HDMI_D_N[2]}] set_property IOSTANDARD TMDS_33 [get_ports HDMI_CLK_*] set_property IOSTANDARD TMDS_33 [get_ports HDMI_D*] set_property PACKAGE_PIN G17 [get_ports HDMI_SCL] set_property PACKAGE_PIN G18 [get_ports HDMI_SDA] set_property IOSTANDARD LVCMOS33 [get_ports HDMI_SCL] set_property IOSTANDARD LVCMOS33 [get_ports HDMI_SDA] set_property PACKAGE_PIN E18 [get_ports HDMI_HPD] set_property IOSTANDARD LVCMOS33 [get_ports HDMI_HPD] set_property PACKAGE_PIN F17 [get_ports HDMI_OUT_EN] set_property IOSTANDARD LVCMOS33 [get_ports HDMI_OUT_EN] create_clock -name sysclk -period 25 -waveform {0 12.5} [get_ports HDMI_CLK_P] this is all you need for your project. Jieming