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  1. 4 points

    Add board to ISE

    Hi, You can add your own board following the steps: 1. Go to ..\Xilinx\14.7\ISE_DS\EDK\board\Xilinx\boards 2. Create a folder board 3. In your folder board create "data" folder 4. Create a .xbd file 5. Open this file and edit with the necessary parameters For example, I add a Nexys4 board. The path for the Digilent_Nexys4.xbd file, in my case is: C:\Xilinx\14.7\ISE_DS\EDK\board\Xilinx\boards\Digilent_Nexys4\data The file content is: ATTRIBUTE VENDOR = Digilent ATTRIBUTE NAME = Nexys4 ATTRIBUTE REVISION = B ATTRIBUTE SPEC_URL = www.digilentinc.com ATTRIBUTE CONTACT_INFO_URL = http://www.digilentinc.com/Support/Support.cfm ATTRIBUTE DESC = Digilent Nexys4 Evaluation Platform ATTRIBUTE LONG_DESC = '-' BEGIN FPGA ATTRIBUTE INSTANCE = fpga_0 ATTRIBUTE FAMILY = artix7 ATTRIBUTE DEVICE = xc7a100t ATTRIBUTE PACKAGE = csg324 ATTRIBUTE SPEED_GRADE = -1 ATTRIBUTE JTAG_POSITION = 1 END Please see the result: Best regards, Cristian
  2. 3 points
    An FPGA can be a useful "swiss army knife", but all the nice features aren't easily accessible. Enter "LabToy": A batteries-included collection of utilities, just double-click and go. As the name implies, this isn't meant to compete against "real" test equipment. The main selling point is like a pocket knife - this fits into a shirt pocket and the power tools don't. And speaking of "selling points", it's free to use. So what do we have here: - Digital data: Shows the input state of all pins - Analog data: Readings from the two ADCs, up to about 700 ksps sustained (XADC "simultaneous sampling" mode, phase-accurate between channels) - Streaming data logger: Both analog and digital data can be written to a .vcd file, to be shown in gtkwave. There is no limit to the capture length. - Analog signal generator: 8 fully independent channels, sine, square wave, the usual suspects. Well, the DACs won't win any audiophile awards, but they are usable. - "Programmable" digital LED mode: Configurable pulse width to suppress short glitches, or edge detect with a built-in pulse generator to highlight them. - Analog LED mode: Shows the input value of the ADC in real time Some screenshots: 1k sine / cosine from DAC jumpered to ADC (in gtkwave) The digital signal is the generator's sync output that can be recorded as a digital input. Realtime display of the inputs. With pocket knives in mind ("this button will unlock the large blade, allowing it to be manually returned to its folded position") I decided to keep the screen uncluttered and put descriptions into tooltips. The large displays are the average voltage readings from the ADC. The smaller ones show the digital inputs in groups of four. Generator controls (frequency, minimum voltage, maximum voltage, phase). The voltage scaling is a bit unusual (typically there is "AC magnitude" and "DC offset") but I chose this approach because it shows clearly the limitations of the 0..3.3V output range. Most people will probably leave all this at the default values for a full-scale signal. Data capture Example: The output in gtkwave after I touched a jumper cable to the digital inputs on the DIL connector. +++ DO NOT USE THE +5V OUTPUT P24 FOR THIS KIND OF TEST +++ (3.3 V is available on the PMOD connector, bottom row) The red "undefined" marks flag the first input in an 8-bit group. In this example, they aren't too meaningful, but they can alert me to the fact that no data events have been observed yet. LED control The two numbers give the number of consecutive 1 or 0 samples (at 125 MHz) before a signal change is propagated to the LED. E.g. put 125 million there and it'll take one second after changing the input state for the LED to light / go dark. Those can be used interactively to study an unknown signal. "Level": no further processing ("level" mode and 1 / 1 sample counts is equivalent to directly connecting the LED to the physical input) "Edge" mode generates a brief pulse on signal changes, the LED is dark otherwise. "Invert" flips the input right next to the pin (0 becomes 1, black becomes white and man gets himself killed on the next zebra crossing -DA). How to get it: The file is attached: labToy0v1_beta.exe The installer unpacks a single .exe. Happy hacking! Requirements: Windows 64 bit (!) .NET 4.5 FTDI libraries CMOD A7 35 T (not 15 T). Warnings: Direct access to digital IO pins is an inherently dangerous activity. "PROVIDED WITHOUT WARRANTY OF ANY KIND" means Just That. And beware of the +5V pin. PS: If you try it, kindly let me know whether it works, or what goes wrong.
  3. 3 points
    A few reasons are... a - The introduction of logic hazards can cause glitches : https://en.wikipedia.org/wiki/Hazard_(logic) b - Routing of clocks is very complex - It is hard to ensure that the same clock edge appears all over the FPGA at almost exactly the same time. Sometimes this is achieved with 'slight of hand' (e.g. using a on-chip PLL to advance phase of the clock, so that by the time it reaches the edge of the chip is in back phase with the original signal). Low-skew paths also exist, but are restricted to small areas of the FPGA, and the clock has to be connected to the correct pin to be placed and routed correctly. c - FPGAs and their tools are designed to behave predictably under the "synchronous digital design" paradigm (something like https://hps.hs-regensburg.de/scm39115/homepage/education/courses/red/2_SynchronousDigitalCircuitDesignRules.pdf). If you work outside the paradigm you will be fighting against the tools and their assumptions. d - There is almost nothing that you are unable to code in an FPGA friendly way, but there are infinitely many ways to write FPGA-hostile code. If you want your FPGA to place nice with you, you have to play nice with it. So you can either add an RC filter to debounce you switch, or you can sample it using a reliable clock.
  4. 3 points

    Just for fun: Frequency Resolution challenge

    Hello everybody! Since I was sharing this image with others, I thought I'd share it here at Digilent as well. The attached image shows the frequency response of several FFT windows, including the well-known rectangle and Hanning windows. The blue window is one I've put together, but haven't shared the FPGA source code used to implement it. I challenge anyone to do better. Oh, and one other comment ... all but the Hanning window can be used in an invertible FFT process. Dan
  5. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  6. 2 points

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  7. 2 points
    The warning you pasted is benign and simply means there are no ILAs present in your design. The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design. Finally, @elodg gives some great troubleshooting information in this thread.
  8. 2 points
    Hi @akhilahmed, In the mentioned video tutorial, the leds are controlled using "xgpio.h" library but the application is standalone. If you want to use a linux based application you have to use linux drivers for controlling. In the current Petalinux build, which is used in SDSoC platform, UIO driver is the best approach. Steps: 1. Vivado project generation: - Extract .dsa archive from /path_to_sdsoc_platform/zybo_z7_20/hw/zybo_z7_20.dsa - Launch Vivado - In Tcl Console: cd /path_to_extracted_dsa/prj - In Tcl Console: source rebuild.tcl - In this point you should have the vivado project which is the hardware component of SDSoC platform. Open Block Design. Change to Address Editor Tab. Here you will find the address for axi_gpio_led IP: 0x4122_0000 2. Petalinux UIO driver: - Launch SDx - Import zybo-z7-20 SDSoC platform - Create a new SDx linux based project using a sample application (e.g. array_zero_copy) - Build the project - Copy the files from /Dubug/sd_card to SD card - Plug the SD card in Zybo Z7. Make sure that the JP5 is set in SD position. Turn on the baord - Use your favorite serial terminal to interact with the board (115200, 8 data bits, 2 stop bits, none parity) - cd to /sys/class/uio - if you run ls you will get something like: uio0 uio1 uio2 uio3 uio4 uio5 - Now you have to iterate through all these directories and to search for the above mentioned axi_gpio_led address: 0x4122_0000 - For example: cat uio0/maps/map0/addr will output: 0x41220000, which means that the axi_gpio_led can be accessed using linux uio driver through uio0 device. - Code: #include <stdio.h> #include <stdlib.h> #include <sys/ioctl.h> #include <sys/mman.h> #include <stdint.h> #include <unistd.h> #include <fcntl.h> #define UIO_MEM_SIZE 65536 #define UIO_LED_PATH "/dev/uio0" void UioWrite32(uint8_t *uioMem, unsigned int offset, uint32_t data) { *((uint32_t*) (uioMem+offset)) = data; } uint32_t UioRead32(uint8_t *uioMem, unsigned int offset) { return *((uint32_t*) (uioMem+offset)); } void led_count_down(uint8_t *ledMem) { uint8_t count = 0xF; uint8_t index = 0; for (index = 0; index < 5; index++) { UioWrite32(ledMem, 0, count); count = count >> 1; sleep(1); } } int main() { // Set Leds as output int led_fd = open(UIO_LED_PATH, O_RDWR); uint8_t *ledMem = (uint8_t *) mmap( 0, UIO_MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, led_fd, (off_t)0); UioWrite32(ledMem, 4, 0x0); // Set all leds as output while(1) { // Start led count-down led_count_down(ledMem); } return 0; } - Build the project and copy the content of Debug/sd_card on SD sd_card - Power on the board and connect to it using a serial terminal - run the following commands: mount mmcblk0p1 /mnt cd /mnt ./project_name.elf - Result: A countdown should be displayed on leds.
  9. 2 points

    Arty A7 flash chip

    Hi @D@n, I believe the new part that is used in the Arty A7 boards (and other A7 boards) is now a Spansion S25FL128SAGMF100; based on old schematics, I believe this was added in Rev D of the Arty A7 (dated August 2017), though I do not know when that particular Rev was then released (or if it even was released) to the public. I confirmed that the Arty S7 also uses this part and I wouldn't be surprised if most of our other Artix 7 based boards use it now as well. I've requested that the chip name and images are updated in any appropriate tutorials and requested that the pdf version of the reference manual (updated wiki) is updated as well. Thanks, JColvin
  10. 2 points
    @hamster I was able to run your AXI Slave interface. It works great! It is now very easy to exchange information between PS and PL, and it even supports execute-in-place (e.g. I can put ARM instructions to register file and run PS CPU directly from it). I have some questions about your AXI Slave design: 1) AXI_a*size has no effect on INCR type of burst transactions, but according to AXI protocol: the increment value depends on the size of the transfer. You set it only for WRAP type, is it correct? Thus, burst size is always 0 for INCR type? 2) Do you know how PS initiates INCR burst type? A kind of memset/memcpy need to be used for that or an incrementing pointer will also work? 3) Where WRAP type is necessary? How to use PS to work in WRAP mode? You may also update your wiki page with following: 0) Create provided VHDL files 1) Create a block-diagram and add PS IP core to it 2) Apply configuration provided by your board's pre-settings; this will set all necessary initialization settings for PS (e.g. clock frequencies, DDR bindings, etc.) 3) Press auto-configure (or how it's called) ==> this will connect PS IP to DDR and to fixed IO 4) Add "External ports" to the diagram (create new AXI_CLK and AXI external ports) and connect them to PS ports 5) Generate VHDL wrapping code for this block diagram 6) Put generated system under axi_test_top by renaming it to axi_test_wrapper (default name is design_#_wrapper in my Vivado version) 7) This will auto-connect block-diagram external ports with axi_test_top 8 ) Add constrains file and rename/uncomment external ports where necessary 9) Generate bitstream 10) File->Export->Hardware and create .hwf file which contains PS configuration 11) Open Xilinx SDK and create a new project: select .hwf file as Hardware BSP for this project 12) Now, Xilinx SDK will auto-generate few .c and .h files which contain necessary PS initialization ==> clocks, IRQs, DDR, etc. 13) Add hello_world.c application to the project @hamster Thank you very much. I've learned a bunch of new things thanks to your help!
  11. 2 points

    Zybo z7-20 Zynq Presets

    Hi @Mahesh, As @jpeyron said in the post marked as accepted solution, the Zynq processing system will be configured with the board presets when you first add the Zynq processing system IP core to the block design and run the block automation task from the green message that appears! Just remember to keep the Apply Board Preset option checked as shown in he picture. So this means if you are using the pre-built block design from the example project, a possible solution can be to remove the existing Zynq processing system block and adding a new one!
  12. 2 points

    Cmod A7 oscillator question

    PS: Reading the above post: I suggest you DO use the IP wizard, not calculate it manually. Pain does not equal gain.
  13. 2 points

    Vivado slowness reality check

    For comparison: My labToy project on CMOD A7 35 builds in 3:40 min (excluding clock IP, measured on my wristwatch by resetting synthesis, then "generate bitstream"). It's not a large project - about 20 % of DSP used and slices touched - but not trivial either. A hello-world project compiles in maybe 1 min, give or take some. But my desktop was built for the job (water-cooled i7 4930 @ 4.5G, 32G quad-channel RAM, M2 SSD). Most of this doesn't help with a one-LED design, but there are a number of things that will slow down the run considerably: - Use correct timing constraints: For example, a LED driven from logic clocked at 200 MHz can be very difficult to route (but at the 12 MHz crystal frequency it shouldn't matter much). A simple set_false_path -to [get_ports LED] makes it "don't-care". - Throw in extra registers where appropriate, especially between blocks (which tend to be physically separate). Most of the time, it does not matter whether the signal arrives one or two clock cycles late, and some spare registers will simplify implementation. This is especially useful for register rebalancing. - For the extra registers, it may make sense to use a "don't touch" attribute. E.g. in Verilog: (* DONT_TOUCH = "TRUE" *)reg [5:0] wa [1:NWRDELAY]; (* DONT_TOUCH = "TRUE" *)reg [17:0] wd [1:NWRDELAY]; (* DONT_TOUCH = "TRUE" *)reg we [1:NWRDELAY]; When I have multiple, parallel instances of a timing-critical block, the input registers are logically equivalent, get optimized away, and then P&R takes ages because timing is so difficult. The "don't touch" attribute" keeps them separate, possibly using a couple of FFs more than strictly necessary. - Removal of redundant logic can take a long time. For example, when I simulate pipelined DSP like the "labToy" generators I simply carry all data all the way through the pipeline, even though most of it isn't needed. Optimization will eventually remove it, but the cost is runtime. The LabToy example includes 8 instances each with a 6-lane 14-cycle 18-bit wide pipeline, and it adds minutes to the synthesis time if I don't remove the unused ends of delay chains in the source code. - Read and understand every warning, and read the timing report. "The compiler is my friend" For example, with PLL blocks it is easy to create duplicate clocks with the same frequency (one from the constraints file, one from the IP block). Timing analysis tries to (and will eventually) sort out all possible interactions, but it takes a lot of time and can create meaningless but difficult routing constraints. - Fix "critical warnings" related to timing. Even if common sense tells the design will work e.g. classroom demo with buttons, Vivado will waste a lot of time trying the impossible.
  14. 2 points
    I solved my ethernet problem and the specific connections to make it work. I didn't have I2C enabled on the Zynq7 customisation. so I also enabled I2C over EMIO. I think this hampered it's ability to communicate with the address chip I changed in the Zynq 7 processor MIO configuration - the ENET0 MDIO device is now MDIO pins MIO 52-53.
  15. 2 points

    AD2 THD

  16. 2 points
    @Shuvo Sarkar What exactly needs to be done depends on what you mean by "region of interest" and "binary mask". I will assume that you are trying to replace some area of what is being displayed on the screen with a rectangular image. A good starting point would be to take the input stream and output it with modifications. The DemoScaleFrame function in video_demo.c does this. The resolution scaling being done by this function also may or may not be desirable for your project. The Bilinear interpolation function implemented on line 473 of the original source is the primary point of interest here. The three variables required to tell what is being written to in the destination frame are the index, i, which can be used to determine the color channel being written to, and the destination coordinate variables xcoDest and ycoDest. A good starting point to be able to see changes being made would be to add extra code to black out a rectangular area of the screen. This can be accomplished by wrapping the destFrame[iDest] statement within an if statement, that either writes a zero to destFrame[iDest] or runs the bilinear interpolation of the source frame, depending on the coordinates of the target pixel in the destination frame. How you store, access, and process the binary mask (overlay image?) is a large topic that I would need more details to provide information on. Let us know if you have more questions. -Arthur
  17. 2 points

    Analog Discovery 2 vs Raspberry Pi 3

    FTDI USBs like AD, AD2, DD are not working with RPI model B (1,2,3) data packets/bytes are randomly lost. The EExplorer with different USB controller is working fine on these. All devices are working with other embeddeds: Zed, Zybo, BeagleBone… According reports AD is working with the original RPI model A and probably Zero because it has similar chipset/USB. The problem seems to be with FTDI or RPI B USB, library or hardware. You can find such comments regarding RPI problems with other devices too. Unfortunately we couldn't remediate this problem.
  18. 2 points
    @Sam_a Should be fixed this time. Thanks for your patience, Arthur
  19. 2 points

    Zynq PL-PS Interrupt issue

    @artvvb The issue seems to solved after I've added the statement: XScuGic_SetPriorityTriggerType(IntcInstancePtr, INTC_INTERRUPT_ID,0x00, 0x3); Now the applications responds and counts interrupt sisgnals coming fro PL. Regards, N
  20. 2 points
    @dcc, If you actually want to set/read memory, you'll need to learn how to interact with a bus. I like to use a B4 pipelined wishbone bus. I find it very simple and easy to use. For example, you can find a very simple block RAM device here that interacts with a wishbone bus. (It would be even simpler if I wasn't keeping my high speed and low speed code in the same file ...) Xilinx has committed themselves to the AXI bus--a bus that requires the management of five separate data paths just to get right. If you want access to DDR3 SDRAM, you'll need to use Xilinx's memory interface generator (MIG) to build an interface for you. (I tried without MIG, made lots of progress, but ... after two months of full time work on it hadn't finished the task. It's a shame. The memory access delay would've been about half of what Xilinx's delay is.) Xilinx's MIG generates a DDR3 interface to a memory using an AXI controller. You can see how I interact with that AXI controller in my own Arty design here. Within that file, take a look at the mig_axis component and then roll your eyes with me at the quantity of wires and communications paths you need to handle just to read or write from memory. Yuck. That's why, in the same file, you'll find a wishbone to axi bridge, one I call wbm2axisp, or wishbone master to AXI slave pipelined. As a result, I can interact with that core using wishbone signals, such as i_wb_cyc to indicate that I am accessing the bus (needs to be high throughout the transaction), i_wb_stb to request a memory interaction (only needs to be high for one clock while o_wb_stall is low per request), i_wb_addr (specifying the address of my request, must be valid any time i_wb_stb is high), i_wb_we (specifies if I am reading or writing), i_wb_data (data to write, must be valid anytime i_wb_stb and i_wb_we are high), o_wb_ack (true any time a memory access completes), o_wb_stall (true if the memory isn't ready to accept a transaction), and o_wb_data (the data result of any read transaction). The number of wishbone signals are truly ... much less than that giant AXI bus. (10 signals, of which 4 have multiple bits associated with them.) Looking at the AXI bus, to interact with it you will need 35 signals, of which 23 have multiple bits. Take your pick. (By the way, going from an 8-bit data width to the 128 bit data width used by the DDR3 SDRAM is not nearly as hard as it sounds, if that's something you would be struggling with.) If you are trying to read/write from memory to support both an ADC and a DAC, you'll need a couple of things. One of them is a FIFO. You can see an example of a FIFO supporting a UART here. DDR3 memory speed can be unpredictable, and it can drop out suddenly for a refresh cycle while you are trying to interact with it. Worse, that MIG interface takes upwards of 24 clocks to complete a transaction. (If you pipeline your requests, only the first will take 24 clocks, the rest can take one clock. See the wishbone B4 spec for a discussion of this.) However, with a FIFO you can weather some of these problems without dropping samples, and even get on and off the memory bus faster. Second, you'll need an arbiter--something that decides of the two transactions you'd like to make, which of them actually gets access to the bus. You can find my own wishbone arbiter here. If you are wondering just how to get a wishbone transaction working, I have examples ranging from simple to complex. For example, here is a simple prefetch example that just reads a single value from memory (i.e., the next instruction for a CPU). Here's another, similar example, which reads two values from memory at a time. (When working with that SDRAM, the first can take 24 cycles per read, the second can do two reads in 25 clock cycles.) And, while we are at it, here's an example which reads 2^N values at once--but since it's got a cache within it, it ... tends to be more complicated. Another example would be the code I've used for building my own DMA. Take your pick. How deep would you like to dive into this? I could go on and on for a while with more examples ... Is this the sort of thing you are looking for? Let me know, and I can offer more, explain any of the above, or ... you tell me. Yours, Dan
  21. 2 points
    The trick is your code does not need to infer a block memory generator. It will actually need to explicitly implement the block memory generator INTERFACE. This is because the block memory generator is already being instantiated in the block diagram. You will need to design a state machine in VHDL that properly implements the interface. For a description of the signals (en, we, addr, etc.) you should refer to the block memory generator Product Guide. You can find the guide by double clicking the block memory generator IP and selecting Documentation in the upper left corner. The end goal will be to create a custom IP core that contains this custom VHDL. Since you do not have an AXI interface on your core, this should be pretty easy. I believe you can just create a new project that targets the ZYBO and has its top level ports be the desired ports on the IP block. Then I think you can run the Create and Package IP wizard from the tools menu to convert the project to an IP core so it can be inserted into you block diagram (which will be in a different vivado project). I'd recommend simulating your project before you convert it to an IP core to help make sure it is functioning as expected. BTW, you can just expand the BRAM_PORTB interface on the block memory generator IP core and manually connect each of the signals to your IP core if you have difficulty making you custom IP implement the BRAM interface. See the picture below for an example of what your end goal will be:
  22. 2 points
    @silverwolfman, I don't have my S6 on my desk to tell you how much time it took me to load the flash, but I do know I didn't use iMPACT. You can find my work here. In particular, the flash loader is called zipload, and depends upon the using the Digilent Adept utilities to load an initial configuration (generated from this toplevel file) into the flash. Dan P.S. I'll be redoing my work again soon, to prove that the updated ZipCPU can still fit (and work) on the device. You can see some of my update works in the 8-bit branch of the s6soc project, but ... although it builds, it hasn't been tested yet so ... it's still a work in progress.
  23. 2 points
    @Hassan Iqbal, Can I try to answer? Your solution will have two parts. The first part will feed the camera image constantly into memory. When you get the vertical sync to start again at the top of the page, you just reset your write memory pointer. The second part of your solution will read the image out of memory on your other clock. This will read out with the synchronization parameters you are trying to achieve. This way, if you write faster than you read, you'll quietly and slowly drop a frame, and if you read faster than you write, you'll eventually get a full frame stuffed into your stream--but either way things will work. This approach will use a "nearest-neighbor" interpolator, and will handle over and underruns by frame dropping or stuffing respectively. The trick you will have is that you only have one interface to memory. For that reason, both video streams will need to buffer their work into a FIFO. When the writer's FIFO is roughly half full, then it will need to write to memory until it's FIFO is empty. Likewise, when the reader's FIFO is half full, it'll want to initiate a read until its FIFO is full. This way, if both the writer and the reader want to access memory at the same time, they'll both be able to wait until the other completes it's memory access request/requirement. I haven't checked on your memory timing requirements at all. That could make things difficult. If it makes things impossible, then drop color bits and you should be able to get back into the realm of possible again. As for how to handle the multiple clocks, you will have three clocks you will need to deal with and work from. Two of these are your pixel clocks. The third is your memory clock. You can synchronize from the pixel to the memory clock and back again using the single "FIFO is half-full" wire. Dan
  24. 2 points

    Stretch Goals?

    I ain't got anything specific in mind. For now, I'm just throwing spaghetti at the fridge and seeing if any of it sticks!
  25. 2 points

    XADC demo

    @Manas, Sam is trying to turn voltage = (12-bit-code)/4096 into microvolts = (1000)*(1000)*(12-bit-code)/4096, and he's trying to avoid division. Rearranging: 1000*1000/4096 = 500*500/1024 (just by dropping common factors of two from both numerator and denominator) Shifting right by ten is equivalent to dividing by 1024, and then he multiplies by 500*500. Looks like it works alright. I might be concerned personally about losing any precision in the divide by 1024 (i.e. shift right by 10), especially since it is being done before the multiply if I understand correctly--leaving you with only 2-bits of precision (did I read that right?). Looking at the above, you might simplify it further into a shift right by 6, followed by a multiply of 15625. To get here, all I did was cancel out any factors of two that were in both the numerator and denominator. Then --- rearrange your order of operations, so the multiply is done first. What makes this choice special is that 15625 can fit within an 18-bit multiplier. Hence you can do: A = 15625*(12-bit-voltage-code) inside a DSP multiplier, and hence inside one clock. The result of this multiply will be a 30-bit number. If you ignore the bottom six bits, the 24-bit number that remains will be the number of microvolts that you are looking for. Converting this to a decimal display might take some more work though. Dan
  26. 2 points


    Hello, R254 is a 0 ohm resistance. you can find it on bottom of the board. See picture attached. It is true though, that it has a tolerance of few miliOhms. They are not different from one board to another. Best regards, Bianca
  27. 2 points
    Hello saleksin, Sorry for the late response, one great source of information, demos and tutorials for the Zedboard in Vivado is at zedboard.org. I believe it requires you to register but there is no cost. Once registered follow this path : Home->Support->Reference Design / Tutorials->Zedboard. Also a good blog for information for the zedboard is at http://svenand.blogdrive.com/archive/160.html#.V2r2RvkrJhG. In the near future we will be posting a demo for the Zybo that uses the PmodOLED that with some little changes that will enable users to use onboard OLED on the Zedboard. Thank you, Jon
  28. 2 points
    Hello, I think the demo project for the Genesys2 would be a good place to start. You can find all the information about it here. Sergiu
  29. 2 points
    While I haven't used this memory generator before, it occurrs to me that the singular characteristic of DDR memory is that it clocks data on both rising and falling edge of the clock. I can't be certain, but I can imagine that 400MHz clock is exactly what you are looking for. Dan
  30. 2 points

    Nexys 4 FPGA board

    Please try manually installing the cable drivers. You can find them in the Vivado installation folder. In my case, they are located here: C:\Xilinx\Vivado\2015.3\data\xicom\cable_drivers\nt64 You can find instructions on how to install them here. You could also run "install_digilent.exe" from the "digilent" folder also found at the location from above. Let me know if this helps.
  31. 2 points

    fft noise and thd

    Hi, To have better horizontal resolution, adjust the Frequency Range to the interested domain or set it to Auto. To have better vertical resolution, lower the Magnitude Top level (<= 3dBV) or adjust the Range for scope inputs, under Channel options.
  32. 2 points
    Hello, You can install the "Digilent WaveForms VIs" hardware support package which provides simple VIs to use the Analog Discovery 1&2 and EExplorer. This package is based on Virtual Bench VIs and does not provide all the features that WaveForms SDK has. https://decibel.ni.com/content/docs/DOC-44838 http://vipm.jki.net/#!/package/digilent_waveforms_vis You can also access all features of WaveForms SDK importing the dwf library, like the following project is done: http://www.instructables.com/id/Analog-Discovery-USB-Oscilloscope-LabVIEW/ The WaveForms installs the Application (GUI), Runtime (dwf library) and SDK (manual, examples). An SPI transmission using the DigitalOut (Pattern Generator) in Python looks like this: from ctypes import * import math import time import sys if sys.platform.startswith("win"): dwf = cdll.dwf elif sys.platform.startswith("darwin"): dwf = cdll.LoadLibrary("/Library/Frameworks/dwf.framework/dwf") else: dwf = cdll.LoadLibrary("libdwf.so") #print DWF version version = create_string_buffer(16) dwf.FDwfGetVersion(version) print "DWF Version: "+version.value #open device hdwf = c_int() print "Opening first device" dwf.FDwfDeviceOpen(c_int(-1), byref(hdwf)) if hdwf.value == 0: print "failed to open device" quit() hzSys = c_double() dwf.FDwfDigitalOutInternalClockInfo(hdwf, byref(hzSys)) # SPI parameters CPOL = 0 # or 1 CPHA = 0 # or 1 hzFreq = 1e6 cBits = 16 rgdData = (2*c_byte)(*[0x12,0x34]) # serialization time length dwf.FDwfDigitalOutRunSet(hdwf, c_double((cBits+0.5)/hzFreq)) # DIO 2 Select dwf.FDwfDigitalOutEnableSet(hdwf, c_int(2), c_int(1)) # output high while DigitalOut not running dwf.FDwfDigitalOutIdleSet(hdwf, c_int(2), c_int(2)) # 2=DwfDigitalOutIdleHigh # output constant low while running dwf.FDwfDigitalOutCounterInitSet(hdwf, c_int(2), c_int(0), c_int(0)) dwf.FDwfDigitalOutCounterSet(hdwf, c_int(2), c_int(0), c_int(0)) # DIO 1 Clock dwf.FDwfDigitalOutEnableSet(hdwf, c_int(1), c_int(1)) # set prescaler twice of SPI frequency dwf.FDwfDigitalOutDividerSet(hdwf, c_int(1), c_int(int(hzSys.value/hzFreq/2))) # 1 tick low, 1 tick high dwf.FDwfDigitalOutCounterSet(hdwf, c_int(1), c_int(1), c_int(1)) # start with low or high based on clock polarity dwf.FDwfDigitalOutCounterInitSet(hdwf, c_int(1), c_int(CPOL), c_int(1)) dwf.FDwfDigitalOutIdleSet(hdwf, c_int(1), c_int(1+CPOL)) # 1=DwfDigitalOutIdleLow 2=DwfDigitalOutIdleHigh # DIO 0 Data dwf.FDwfDigitalOutEnableSet(hdwf, c_int(0), 1) dwf.FDwfDigitalOutTypeSet(hdwf, c_int(0), c_int(1)) # 1=DwfDigitalOutTypeCustom # for high active clock, hold the first bit for 1.5 periods dwf.FDwfDigitalOutDividerInitSet(hdwf, c_int(0), c_int(int((1+0.5*CPHA)*hzSys.value/hzFreq))) # SPI frequency, bit frequency dwf.FDwfDigitalOutDividerSet(hdwf, c_int(0), c_int(int(hzSys.value/hzFreq))) # data sent out LSB first dwf.FDwfDigitalOutDataSet(hdwf, c_int(0), byref(rgdData), c_int(cBits)) dwf.FDwfDigitalOutConfigure(hdwf, c_int(1)) print "Generating SPI signal" time.sleep(1) dwf.FDwfDigitalOutReset(hdwf); dwf.FDwfDeviceCloseAll()
  33. 2 points

    ASEE 2015- Workshop Materials

    If you attended our ASEE 2015 workshop with Kathleen Meehan and wanted a digital copy of the workshop materials-- I've loaded them here. The material features Waveforms, a few analog components and the Analog Discovery. 5-_back_Digilent-2015-AnalogAccessories-infosheet-1.pdf 4-front_and_back_page_color_Digilent-2015-Discovery-infosheet-1.pdf 3-Design a night light lab.pdf 1-front and back front page- color.pdf 2-555 Timer Lab.pdf 5- front page color Digilent-2015-WaveForms-infosheet-1.pdf
  34. 2 points

    Help With A Zybo Video Design

    Dear Chris, 1. Like Run suggested, the error "IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: BiDi RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 2 sites." such kind of problem is caused by one or more unconnected external ports on your block diagram. Please check your diagram first to make sure all unused external ports are deleted. (this problem will occur on both 2014.4 and 2015.1) 2. For the DDC part, the HDMI protocol described it clearly that this is a mechanism to let video transmitter and receiver to communicate which each other. By exchanging information, the transmitter could know the detail configuration(ability) of the receiver part (what resolution, frame rate, format of signal the receiver can process). This is a necessary part in HDMI transmission and can not be ignored or deleted. 3. Currently the problem you encountered is how to synthesis the Bi-Directional inner control ports into a signal Bi-Di external port. To solve this problem, first you should understand what is a bi-di port and its mechanism(I am sure you know it). Secondly, in Xilinx ISE, three bi-di control ports can be easily synthesized together by adding a constrain command in the .ucf file. In vivado the goal can't be achieved by only modify the .xdc. In my way, i directly modified the DVI2RGB ip core, the top_module i mentioned is the top module of the ip core (the dvi2rgb.vhd file). The core is written by VHDL, modify the following: a. In the port description change DDC ports to below -- Optional DDC port DDC_SDA : inout std_logic; DDC_SCL : in std_logic; b. add HPD and CEC port in the end of port def HDMI_HPD : out std_logic; HDMI_OUT_EN : out std_logic c. in the behavioral part add signal def and logic architecture Behavioral of dvi2rgb is ....... signal hpd : std_logic; ....... begin DDC_SCL_I <= DDC_SCL; DDC_SDA <= DDC_SDA_O when DDC_SDA_T = '0' else 'Z'; DDC_SDA_I <= DDC_SDA; HDMI_OUT_EN <= '0'; HDMI_HPD <= hpd; ....... d. in the TMDS_ClockingX call add port "hpd" TMDS_ClockingX: entity work.TMDS_Clocking generic map ( kClkRange => kClkRange) port map ( ......... hpd => hpd ); f. in the TMDS_ClockingX module(vhd file) add "hpd" def. this will active the HDMI transmittion only after the sink core has been locked entity TMDS_Clocking is Generic ( kClkRange : natural := 1); -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5 Port ( ......... hpd : out std_logic); end TMDS_Clocking; architecture Behavioral of TMDS_Clocking is .......... begin hpd <= aDlyLckd; ......... the above is all you need to make this core compatible with HDMI. after modification -> save -> repackage ip core 4. All you need in your project xdc file is really sample if modification has been done inside ip core. below is my xdc set_property PACKAGE_PIN H16 [get_ports HDMI_CLK_P] set_property PACKAGE_PIN H17 [get_ports HDMI_CLK_N] set_property PACKAGE_PIN D19 [get_ports {HDMI_D_P[0]}] set_property PACKAGE_PIN C20 [get_ports {HDMI_D_P[1]}] set_property PACKAGE_PIN B19 [get_ports {HDMI_D_P[2]}] set_property PACKAGE_PIN D20 [get_ports {HDMI_D_N[0]}] set_property PACKAGE_PIN B20 [get_ports {HDMI_D_N[1]}] set_property PACKAGE_PIN A20 [get_ports {HDMI_D_N[2]}] set_property IOSTANDARD TMDS_33 [get_ports HDMI_CLK_*] set_property IOSTANDARD TMDS_33 [get_ports HDMI_D*] set_property PACKAGE_PIN G17 [get_ports HDMI_SCL] set_property PACKAGE_PIN G18 [get_ports HDMI_SDA] set_property IOSTANDARD LVCMOS33 [get_ports HDMI_SCL] set_property IOSTANDARD LVCMOS33 [get_ports HDMI_SDA] set_property PACKAGE_PIN E18 [get_ports HDMI_HPD] set_property IOSTANDARD LVCMOS33 [get_ports HDMI_HPD] set_property PACKAGE_PIN F17 [get_ports HDMI_OUT_EN] set_property IOSTANDARD LVCMOS33 [get_ports HDMI_OUT_EN] create_clock -name sysclk -period 25 -waveform {0 12.5} [get_ports HDMI_CLK_P] this is all you need for your project. Jieming
  35. 2 points


    Hi, My name is Stuart and I have been programming with my Zedboard for about 8 months now. I am primarily interested in parallel computing and am currently scouring the Internet trying to figure out how to use my PMODs on my Zedboard utilizing Vivado. Nice to meet you all!
  36. 1 point
    yes, for an application with basic requirements, like receiver gain control this will probably work just fine (it's equivalent to an analog envelope detector). Now it needs a fairly high bandwidth margin between the modulation and the carrier, and that may make it problematic in more sophisticated DSP applications (say "polar" signal processing when I try to reconstruct the signal from the envelope) where the tolerable noise level is orders of magnitude lower.
  37. 1 point

    Scope custom math channel limitations?

    Hi @P. Fiery You could use the View/Logging/Script to create an up-sampled reference channel like this: var rg = [] var v2 = 0 Scope.Channel1.data.forEach(function(v1){ rg.push((v1+v2)/2) rg.push(v1) v2 = v1 }) // upsampling by 2 doubles the sample rate Scope.Ref1.setData(rg, 2*Scope.Time.Rate.value)
  38. 1 point
    For the Protocol / SPI-I2C /Spy mode you should specify the approximate (or highest) protocol frequency which will be used to filter transient glitches, like ringing on clock signal transition. The Errors you get indicate the signals are not correctly captured. - make sure to have proper grounding between the devices/circuits - use twisted wires (signal/ground) to reduce EMI - use logic analyzer and/or scope to verify the captured data / voltage levels at higher sample rate at least 10x the protocol frequency Like here in the Logic Analyzer you can see a case when the samples are noisy:
  39. 1 point
    Hi! Check page 45 in https://www.xilinx.com/support/documentation/boards_and_kits/zc706/ug954-zc706-eval-board-xc7z045-ap-soc.pdf It stated: N8 MGTREFCLK0P_112 PCIE_CLK_QO_P A13 (1) N7 MGTREFCLK0N_112 PCIE_CLK_QO_N A14 (1) So just create clock input pins in your block diagram with any names. After that define constraints in xdc file which connects your clk names to N7/N8 pins.
  40. 1 point

    Pin mapping for JTAG-SMT2-NC?

    Hi @Sarah, Based on the JTAG SMT2 Reference Manual, the GPIO can be used for a number of applications, though the usual application for the GPIO2 would be to connect to the PS_SRST_B pin in Zynq based devices as you have noted. We (Digilent) do not have the timing information about when the Xilinx tools use this pin to reset the Zynq's processor core at various times during debugging operations, though it looks like Xilinx does have a little bit more information about it in their Zynq-7000 Technical Reference Manual here as well as some additional documentation for Zynq devices here. Thanks, JColvin
  41. 1 point
    Hi @BYTEMAN, I am not aware of a way to have those specific microblaze configuration pages to be used after the initial block automation. I would suggest to reach out to xilinx about this question. I believe you are correct about the xdc overriding the board file defaults. thank you, Jon
  42. 1 point
    One thing I realized in the course of mulling this question: Part of my early resistance to splitting pio[...] into pioA, pioB and pioC was that I wanted to implement a bus that would span those ranges, and had a mental block about how to achieve that. It's not very difficult, but in case someone else has the same hiccup, I'll post an example solution here: module top( input sysclck, output [1:0] led, input [14:1] pioA, input [23:17] pioB, input [48:26] pioC ); wire [8:1] mybus; assign mybus[4:1] = pioA[14:11]; assign mybus[8:5] = pioB[20:17]; assign led[0] = &mybus; assign led[1] = &pioA[10:1]; endmodule I should note in passing that the supplied xdc file has another problem. In the supplied xdc file, pio[1]..pio[9] are written as pio[01]..pio[09], as in: set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports { pio[01] }]; #IO_L8N_T1_AD14N_35 Sch=pio[01] The xdc file is a TCL language file, and it may not be evident what the { pio[01] } actually means. It looks like it would be an array pio, with index 01, which one might assume is an integer, and thus equivalent to plain 1. In fact, the {...} is syntax to enclose a string, which is not to be interpolated (no substitutions made). So the result of { pio[01] } is the string: " pio[01] " ... including the spaces! In short, the string " pio[01] " is used verbatim as a string key for some array/hashtable/dictionary. It does not imply that there's an array called "pio", from which this code fetches the item at index 1. But then how does this match up to a particular port object declared in module top's declaration (where pio[14:1] treats the numbers in the index range as integers). There is some mechanism in get_ports or somewhere that must match this string index ("key") to top's port declaration. So the {...} string as written in the xdc file has to follow the pattern that the matching algorithm uses, which pio[01] does not, apparently. Consequently, xdc's pio[01] fails to match top.v's pio[1], etc. (And Vivado will give some obtuse error message about "Unspecified I/O Standard", and fails to generate bitstream.) Instead, you have to edit the xdc file for all the cases where pio[xx] has a leading zero, and remove it. So, for example, { pio[01] } should be edited to { pio[1] }. This does satisfy the matching algorithm. For further illumination on this syntax, you might like to try the following code: set result A append result { pioA[01] } append result B puts $result ... at an online TCL interpreter, like: https://www.tutorialspoint.com/execute_tcl_online.php This prints a result "A pioA[01] B", demonstrating that the action of the {...} syntax used in the xdc file is simply to produce a string, which is used verbatim as an argument to get_ports.
  43. 1 point

    Vivado version for Arty Z7-20

    Hi @Mahesh, I was able to get the arty-Z7-20 hdmi out to generate a bitstream in vivado 2017.4. To do this you new a fresh project. Then upgrade the ip cores by clicking tools->repots->report ip status and upgrade/generate the ip cores. Then create a wrapper. The DVI2RGB ip core has been updated since this project was made. Because of the updated ip core you will need to change the xdc pin names in the xdc file. From hdmi_hpd_tri_i to HDMI_HPD_tri_i , from hdmi_ddc_scl_io HDMI_DDC_scl_io and from hdmi_ddc_sda_io to. HDMI_DDC_sda_io. Next generate bitstream. The rest should be the same steps to get project working. cheers, Jon
  44. 1 point

    JTAG-HS3 connection with API (DmgrOpen)

    Hi @Assane, I will reach out to a more experienced engineer about this question. Also did you use the EnumDemo.cpp? cheers, Jon
  45. 1 point
    I haven't used the JDK on zedboard or zybo, but I did run Android on zedboards and was able to get its GUI to display, which uses quite a bit of Java. Android really needs a GPU, which zynq does not have, so I do not recommend this path for a GUI. If JFRAMES works in Ubuntu 16.04, you might be able to run it on the ARM processor of a zybo, if you run Ubuntu on the zybo. In this case, you only need a small program to run on the zybo. Another option, if you have some skill with networking, is to run your UI on another machine and stream the data to it over ethernet from the zybo. If you know javascript, websockets is a good option for interaction between the GUI and a small amount of code on the zybo.
  46. 1 point

    How to program Arty flash

    Great to hear Enrico! Let us know if you hit another roadblock or need anything else. Also, feel free to comment on the guide if things were not clear or if we could improve it in some way. A little constructive criticism is always welcome. Mikel
  47. 1 point
    Hi Greg, Thank you for pointing out that encryption isn't just a matter of SW tools. I have some answers for your question, which I am happy to get into further if I don't give you a clear enough answer here. For your first question, currently the on-board USB-JTAG solution doesn't support eFUSE configuration due to how the toolchain confirms the cable speed. This should change in Xilinx's 2016 release of Vivado. For your second question, the J8 connection hasn't been tested with a Xilinx USB Platform Cable II, but has been tested with plenty of other cables. You should be able to use the Platform cable to configure the eFUSE registers through the header. Please let me know if I can further clarify anything for you, Andrew
  48. 1 point

    Zybo custom IP core example

    Hi kage-chan, I looked into it and found out it's a problem in Vivado 2015.3 and 2015.4. It looks like xparameters.h does not update the addresses for your custom IP core when you add it. So instead of giving it proper addresses, it defaults to Base addr 0xFFFFFFFF and High addr 0x00000000. Here is the Xilinx answer record for it. For a quick fix though, you can go into your Vivado block design, click the Address Editor tab, and copy the offset address there. Then in SDK, replace the #define with the offset address. This should be the correct address of the first register in your component. #define MY_PWM 0x43C00000 This should be fixed in future versions of Vivado. Thanks, Tommy
  49. 1 point

    Booting the Linaro filesystem on Zybo

    Hi Mike, I'm unsure about the problem you're having, but I would suggest checking out this tutorial about setting up the Ubuntu on the ZYBO: http://www.instructables.com/id/Setting-up-the-Zybot-Software/?ALLSTEPS In particular, Step 6 has the boot files that are needed to run Ubuntu after you have everything else ready. We are also going to be writing a new embedded systems tutorial designed specifically for the ZYBO, so stay tuned! -Josh
  50. 1 point
    You can talk with the PMOD over SPI - Wikipedia has an overview at http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus You can find the hardware detail in the reference manual at https://www.digilentinc.com/Data/Products/PMOD-NIC100/PmodNIC100_rm_RevA.pdf The PMOD use's Microchip's stand alone Ethernet controller - ENC424J600 - you can find the full datasheet for the chip at http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf. To use the chip there are thirty or so registers, and quite a few may need to be set appropriately before Ethernet frames can be sent. It might pay to experiment with it for a while in a more software-friendly environment - perhaps hook it up to a micro-controller and experiment with it for a while....