Popular Content

Showing content with the highest reputation since 07/17/19 in all areas

  1. 2 points

    FAT32 with Zybo Z7

    @sgandhi, Welcome to data processing. The sad reality is that text files aren't good for this kind of thing. It's not an FPGA particular thing, but rather a basic reality. 1) Text files tend to take up too much space, and 2) they require processing to get the data into a format usable by an algorithm. One way to solve this problem, which I've done in the past with great success, is to rearrange the file so that's it's a binary file containing a large homogeneous area of elements all of the same type. In my case, I wanted a file that could be easily ingested (or produced) by MATLAB. I chose a binary format that had a header, followed by an NxM dimensional matrix of all single-precision floats. (You can choose whatever base type you want, but single-precision floats were useful for my application.) The header started with three fields: 1) First, there was a short marker to declare that this was the file type. I used 4-capital text letters for this marker. That was then followed by the 2) number of columns in the table, and then 3) the offset to the start of the table. This allowed me to place information about the data in further header fields, while still allowing the processor to skip directly from the beginning header to the data in question. Further, because the data was all of the same type, I could just about copy it directly into memory without doing any transformations, and to then operate on it there. It did help that the data was produced on a system with the same endianness as the system it was read from ... Dan
  2. 2 points

    Zybo Z7 Pcam 5C Demo - Warnings

    To add a little bit to what Jon said, these warnings appear to be ignorable. They all relate to design choices made when connecting custom IP in the block design. Typically, even when designing with Xilinx IP, many warnings are seen in the project. These messages are there to help get information on why something may be causing bigger problems later (errors, critical warnings, something not working in actual hardware). Note that even some critical warnings may be ignored. -Arthur
  3. 2 points
    There is no code to draw any shape as you observed since it was/is a work in progress. Thus it was excluded by default from `rootfs`. However it was mentioned by mistake in the first link you mentioned. https://reference.digilentinc.com/reference/software/petalinux/start The issue has been corrected.
  4. 2 points
    Hi, Sorry to barge in, but if anybody can point me to the Hibbert Transformer info I would be very grateful. However, here is an FPGA friendly way to calculate mag = sqrt(x*x+y*y), with about a 99% accuracy. You can easily see the pattern to get whatever accuracy you need. #include <math.h> #include <stdio.h> #define M_SCALE (16) /* Scaling for the magnitude calc */ void cordic_mag(int x,int y, int *mag) { int tx, ty; x *= M_SCALE; y *= M_SCALE; /* This step makes the CORDIC gain about 2 */ if(y < 0) { x = -(x+x/4-x/32-x/256); y = -(y+y/4-y/32-y/256); } else { x = (x+x/4-x/32-x/256); y = (y+y/4-y/32-y/256); } tx = x; ty = y; if(x > 0) { x += -ty/1; y += tx/1;} else { x += ty/1; y += -tx/1;} tx = x; ty = y; if(x > 0) { x += -ty/2; y += tx/2;} else { x += ty/2; y += -tx/2;} tx = x; ty = y; if(x > 0) { x += -ty/4; y += tx/4;} else { x += ty/4; y += -tx/4;} tx = x; ty = y; if(x > 0) { x += -ty/8; y += tx/8;} else { x += ty/8; y += -tx/8;} tx = x; ty = y; if(x > 0) { x += -ty/16; y += tx/16;} else { x += ty/16; y += -tx/16;} *mag = ty/M_SCALE/2; /* the 2 is to remove the CORDIC gain */ } int main(int argc, char *argv[]) { int i; int cases = 300; printf("Irput Calculated CORDIC Error\n"); for(i = 0; i < cases; i++) { float angle = 2*M_PI*i/cases; int x = sin(angle)*20000; int y = cos(angle)*20000; int mag, a_mag = (int)sqrt(x*x+y*y); cordic_mag(x,y, &mag); printf("%6i %6i = %6i vs %6i %4i\n", x, y, a_mag, mag, mag-a_mag); } } Oh, here is the output with a couple more iterations added. Irput Calculated CORDIC Error 0 20000 = 20000 vs 19999 -1 418 19995 = 19999 vs 19995 -4 837 19982 = 19999 vs 20001 2 1255 19960 = 19999 vs 19998 -1 1673 19929 = 19999 vs 19995 -4 2090 19890 = 19999 vs 20001 2 2506 19842 = 19999 vs 19998 -1 2921 19785 = 19999 vs 19996 -3 3335 19719 = 19999 vs 20001 2 3747 19645 = 19999 vs 19998 -1 4158 19562 = 19999 vs 19996 -3 4567 19471 = 19999 vs 20001 2 4973 19371 = 19999 vs 19997 -2 5378 19263 = 19999 vs 19996 -3 5780 19146 = 19999 vs 20001 2 6180 19021 = 19999 vs 19998 -1 6577 18887 = 19999 vs 19999 0 6971 18745 = 19999 vs 20001 2 7362 18595 = 19999 vs 19993 -6
  5. 2 points

    Enevlope Detection using FPGA board

    Well yes and no. The question I'd ask is, can you use a local oscillator somewhere in your signal path with a 90 degree offset replica. In many cases this is trivially easy ("trivially" because I can e.g. divide digitally from double frequency or somewhat less trivially, use, say, a polyphase filter. In any way, it's probably easier on the LO than on the information signal because it's a single discrete frequency at a time, where the Hilbert transform approach needs to deal with the information signal bandwidth). If so, downconvert with sine and cosine ("direct conversion") and the result will be just the same. After lowpass filtering, square, add, take square-root, there's your envelope . When throughput / cost matters (think "Envelope tracking" on cellphones) it is not uncommon to design RTL in square-of-envelope units to avoid the square root operation. Or if accuracy is not that critical, consider a nonlinear bit level approximation see "root of less evil, R. Lyons". Of course, Hilbert transform is a viable alternative, just a FIR filter (if complex-valued). In case you can't tell the answer right away, I recommend you do the experiment in the design tools what happens if you try to reach 0 Hz (hint, "Time-bandwidth product, Mr. Heisenberg". Eventually it boils down to fractional bandwidth and phase-shifting DC remains an unsolved problem...).
  6. 2 points
    Hey guys, I've made some experiments that could be interesting for your as well. I put tap water into my ceramic container, I heated it to different temperatures and measured the impedance every 5 degrees. You can see the values between 60 ° Celsius (140 ° Fahrenheit) and 5 ° Celsius (41 ° Fahrenheit). Red is 60 Celsius, blue is 5 Celsius and there are 10 steps between them.
  7. 1 point

    Amplitude modulation with DDS generator

    The carrier phase alignment question is pretty important. What carrier frequency is this thing supposed to be operating at? And ... is it in the range of what an FPGA can create? Dan
  8. 1 point
    You could use the multiplication operator "*" in Verilog (similar VHDL). For example, scale the "mark" sections (level 10) by 1024, the "space" sections (level 3) by 307. This will increase the bit width from 12 to 22 bits, therefore discard the lowest 10 bits and you are back at 12 bits. Pay attention to "signed" signals at input and output, otherwise the result will be garbled.
  9. 1 point

    VGA example for Digilent Nexys A7?

    Hi @john_joe, It is possible to get a VGA input but the hardware needs to be configured for that. The DIR pin is tied to VDD so in this case the Pmod VGA is set to output as shown on the schematic here and here on the IC data sheet. I believe you would need to alter the DIR connection on the Pmod VGA to ground to have it usable for input. So you are aware this would void the Pmod VGA's warranty. Here and here are a few threads that discuss VGA input as well. best regards, Jon
  10. 1 point

    VGA example for Digilent Nexys A7?

    Hi @john_joe, Could you please elaborate more on your project. The Pmod VGA (resource center) facilitates a VGA connector from two pmod ports. There are a couple of Pmod VGA HDL projects linked on the bottom of the resource center. Here is a non-digilent product that might be helpful. best regards, Jon
  11. 1 point
    Hi @Andras A. Comparing two different tools might not be the best option, it could give different results. B. At the moment the Impedance Analyzer interface takes control over the Supplies and DIO lines to control the IA Adapter. On the Adapter the negative supply and some DIO lines are unused. In the next software version I will add option to be able to control these. Having these you could use a small signal relay with ~5V control, similar to the ones on IA adapter but non-latching, to switch between the measured and control DUTs. https://reference.digilentinc.com/_media/reference/instrumentation/analog_discovery_impedance_analyzer_sch.pdf Edit: You could use the current software for plan B. First, in the Impedance interface using the Adapter option select the needed resistor value, then select "W1-C1-DUT...". This will release the Supplies and DIO lines to be used from other interfaces, and the latching relays on the Adapter will remain unchanged. Then you can use the Static IO or Negative supply for other purposes, to control the external relay...
  12. 1 point
    Tim S.

    Pmod OLEDrgb with Zybo Z7

    Just to make sure my explanation is thorough. The above has a typo. It should read: Linux has a case-sensitive file system whereas Windows has a case-insensitive file system.
  13. 1 point

    DMC60c CAN Bus

    Hi opethmc, The current and voltage information is reported by the DMC60C every 100ms (by default) in the STSANALOG (0x020614C0) frame. This info can be found on page 28-30 of the CAN protocol guide. Fault status can be found in byte 4 (fs2) in the STSGENERAL(0x02061400) frame that is sent every 10ms (by default). You can find the fault counts by reading parameters 51 through 57. This can be done by sending PARAMREQ (0x02061800) frames containing the parameter you want to read, then scanning for a PARAMRESP(0x02061840) packet. This info can be found on page 12-28. Hope this helps! Tommy
  14. 1 point

    GPS Pmod

    Hi @cepwin, I'm glad you we able to get to the bottom of the issue. Thank you for sharing what happened. cheers, Jon
  15. 1 point
    Szia @Andras The WaveForms Sound Card option is solution for free... in case the audio IO limitations are suitable for the requirements. Here some IA measurements are compared between AD2 and Sound Card:
  16. 1 point

    GPS Pmod

    @cepwin, There's a real easy way to debug whether or not you are getting a fix or not. Remove the FPGA design, and replace it with a pass through from the GPS UART transmit pin to the FT2232 UART RX transmit pin. You can then use your favorite terminal program, mine is minicom some like teraterm, to examine the NEMA stream produced by the GPS device. It's typically 9600 Baud, 8 data bits, no parity and one stop bit. It's also pseudo-human readable--line upon line of CSVs--you should then be able to tell if you are getting lock or not. I see no reason why you wouldn't be getting lock from your upstairs bedroom. Also, for your security, you probably don't want to paste the NEMA stream coming out of the device here for discussion--since it may well reveal the coordinates of your bedroom. Dan
  17. 1 point
    This little project might give you some ideas - it controls the speed of the dev board's fan based on the XADC reading. It also uses no IP blocks so everything is exposed. http://hamsterworks.co.nz/mediawiki/index.php/XADC_Fan_PWM
  18. 1 point
    Impedance Analyzer v1.3.0.43 available for Download Currently, it only works with AD1 (cf. EEVblog AD2 not working with this great S/W). Would be great to get some advace from Digilent ,-) Best Ulli
  19. 1 point

    Custom IP

    @PoojaN, Welcome to the wonderful world of graphic design. I avoid it like the plague, since I worry that it conceals key details from the beginning designer--but that's another story for another day. You can read how you can go about creating an AXI component here. You can then tear the guts out of that component and start over with something that works (Xilinx's was broken last I checked), perhaps something like this one. If AXI is too complicated for you, feel free to try AXI-lite. Again, Xilinx's demo AXI-lite core is broken but you can find a non-broken one here that you can use. That said, the process is similar. As for the GPIO core ... I think it's intended to connect to external ports only, with the feature that the I/Os can be redirected on command to be either inputs or outputs. Personally? I wouldn't use it. The interface offered by the two cores linked above would be superior if you can use it. What do I mean by superior? I simply mean that there's been more than one person disappointed at how fast they can toggle an I/O from a CPU. The AXI GPIO core takes 5 clocks just to toggle an LED, in addition to any bus delays you might struggle with. Dan
  20. 1 point
    Bare metal is a stand alone program that runs on the PS without an operating system and is developed and deployed though Xilinx SDK. With Linux, you run Linux on the board and write a regular Linux application using the Linux toolchain. I suggest you read up a bit on both and see which you prefer.
  21. 1 point
    Using a tool for what it is meant to do is easy. Using a tool for something where it isn't suited, that is where the learning begins! (I now goes back to doing dental surgery with a steamroller, or maybe digging a tunnel with a teaspoon).
  22. 1 point

    GPS Pmod

    Hi @cepwin, Have you added the Vivado library to your Vivado 2019.1 installation? You can do this from inside Vivado by Choosing settings in the Project Manager in the upper left, expand the IP selection in Project Settings and choose Repository. You can then add in the path to the Vivado-Library from Digilent (which you can download from our GitHub here). This should let you generate the bitstream. Otherwise, you don't need to open up Vivado at all. If you have a fresh project you can open Xilinx SDK 2019.1, choose the workspace folder when it prompts you as the sdk folder source (as an example, mine is C:\Users\jcolvin\Documents\VivadoPrj\Arty-S7-PmodGPS_Vivado_2019_1\Arty-S7-PmodGPS_Vivado_2019_1.sdk) and wait for SDK to finish loading the workspace. When it is completed, you should see the hardware platform_0, the PmodGPS application folder, and the PmodGPS_bsp. You can then click the Xilinx tab at the top of the GUI, and choose to program the FPGA with the bitstream it finds. You will then want to connect to your board with your serial terminal of choice (I used TeraTerm) otherwise you won't see anything printing out. I then right-click on the PmodGPS application folder and choose Run As->Launch on Hardware (System Debugger). I then see the data printing out on the serial terminal. Is this what you did for your project? Thanks, JColvin
  23. 1 point


    I'd recommend you spend a working week "researching" the electrical-engineering aspects. The ADC may look just as an afterthought to DSP but it will require significant engineering resources (plan for several / many man-months). Long is the list of bright-eyed students / researchers / engineers / managers who have learned the hard way that there is a bit more to the problem than finding two boards with the same connector... Hint, check how much latency you can tolerate and research "digitizer" cards for PC (or PXI platform). If you don't need a closed-loop real-time system, don't design for a closed-loop realtime system.
  24. 1 point

    Zybo Z7020 SDK Programming Issue

    Yes, it's a 7020. I was able to get things working by power cycling the device. I was under the impression that changing jumper positions for boot device (JTAG vs. SPI) was enough to do between flashing the FPGA. I found that power cycling the device with the jumper in the JTAG position, and then flashing the device fixed this issue.
  25. 1 point
    Going to Incorporate it into my (MCU based) guitar tuner... but it is a nice tool to have in the kit.
  26. 1 point

    Creating A VI for Pmod Nav

    Hi @ARD1996, I looked through my old material, and found in a folder called "Minor Tweaks or Review needed" a number of VI's that I designed for the Pmod NAV. They were all last modified in late 2016 and haven't been looked at since then, so I do not how well it will work, but at least at lot of the base line is there. The existing Pmods added to LINX will have their own examples that detail how each of them work in the block diagrams in text boxes. I believe the ones I have attached do the same explanation, though based on what I had typed, there is at least some funkiness with the 2's complement conversion that is used. Thanks, JColvin PmodNAV_calibrate.vi PmodNAV_close.vi PmodNAV_loadCalibrationValues.vi PmodNAV_open.vi PmodNAV_openForLoop.vi PmodNAV_read.vi
  27. 1 point

    Project Archive in Vivado

    Hi @Antonio Fasano, Here is the xilinx recommended approach for sharing and archiving SDK that should be helpful for eliminating multiple hw platforms as well as having to use the same folder name. best regards, Jon
  28. 1 point

    Correct Battery for PmodGPS

    Hi @stefantimm, We have added a CR1220 to the Pmod GPS. I will pass on your reference manual suggestion to our content team. Here is a forum thread that discusses the height of the battery as well. best regards, Jon
  29. 1 point
    Szia @Andras For this you don't necessarily need a script. In the interface you can set constant frequency (Start = Stop), specify a long Settle time and press Single. Like the following will run for 50 minutes, 100 samples at about 2/min rate, 30s + a few milliseconds due software processing.
  30. 1 point

    Enevlope Detection using FPGA board

    @hamster, Not bad, not bad at all ... just some feedback for you though: The "official" Hilbert transform tap generation suffers from the same Gibbs phenomena that keeps folks from using the "ideal lowpass filter" (i.e. sin x/x) You could "window" the filter to get better performance, or you could try using Parks-McClellan to get better taps. There are tricks to designing filters with quantized taps as well ... however the ones I know are ad-hoc and probably about the same as what you did above There's symmetry in the filter. For half as many multiplies you can take sample differences, and then apply the multiplies to those sample differences. Other than that, pretty cool! Did you find anything useful to test it on? Dan
  31. 1 point

    Getting Input Phase Programmatically

    Hi @jamesbraza See the following SDK example compared to WF app result: AnalogImpedance_Input.py dwf.FDwfAnalogImpedanceStatusInput(hdwf, c_int(1), byref(gain2), byref(phase2)) # relative to Channel 1, C1/C# rgGaC2[i] = 20.0*math.log10(abs(gain2.value-1.0))
  32. 1 point
    You can find newer version in the description of the video: https://www.youtube.com/watch?v=4d3hc-9zBaI
  33. 1 point
    Oh, for what it's worth I've been toying with the Hilbert Transform. Here is a example of it; #include <math.h> #include <stdio.h> #define SAMPLES 1000 #define HALF_WIDTH 11 /* e.g. 11 filters from -11 to 11 */ float x[SAMPLES]; int main(int argc, char *argv[]) { int i; /* Build some test data */ for(i = 0; i < SAMPLES; i++) { x[i] = cos(2*M_PI*i/10.3); } /* Now apply the Hilbert Transform and see what we get */ /* It should be close to sin(2*M_PI*i/10.3) */ for(i = HALF_WIDTH; i < SAMPLES-HALF_WIDTH-1; i++) { double h = 0; int j; /* Apply the kernel */ for(j = 1; j <= HALF_WIDTH; j+=2) h += (x[i-j]-x[i+j]) * 2.0/(j*M_PI); /* Print result */ printf("%8.5f, %8.5f\n", x[i], h); } }
  34. 1 point

    ARTY A7 instantiate PLL in top module

    Hi @skylape, I believe the Verilog module should use the fastclk as a wire connecting the output from the clocking wizard to the pwm module. `timescale 1ns / 1ps module top( input CLK, output pwm_out1, output pwm_out2, output pwm_out3 ); wire fastClk; clk_wiz_0 clk_1 ( // Clock in ports .clk_in1(CLK), // Clock out ports .clk_out1(fastClk), // Status and control signals .locked() ); pwm pwm_output1 ( .clk(fastClk), .i_duty(10), .pwm_out(pwm_out1) ); pwm pwm_output2 ( .clk(fastClk), .i_duty(45), .pwm_out(pwm_out2) ); pwm pwm_output3 ( .clk(fastClk), .i_duty(80), .pwm_out(pwm_out3) ); endmodule You will also need an xdc file to constrain the input and output signals to pins on the FPGA. Here is the master xdc for the arty-a7. best regards, Jon
  35. 1 point
  36. 1 point

    Pulse Width Misbehavior

    Hi @P. Fiery I have added the idle disable option to do some internal testing and forgot to remove it from the release version. This option is not supported by AD2 and causes a glitch. In case you are interested about more details: On the AD the AWG has two gains, 1/5V amplitude, 2/10Vpk2pk and separate DAC for offset. This lets you generate low amplitude, high resolution waveform at higher offset level, like 1Vpk2pk signal + 4V offset. https://reference.digilentinc.com/reference/instrumentation/analog-discovery-2/reference-manual#awg_iv
  37. 1 point
    Oh having a look at the full signal chain, it looks like you just need to apply a low-pass filter on the absolute value of the signal. It might be just as simple as: if sample < 0 then filter := filter - filter/64 - sample; else filter := filter - filter/64 + sample; end if; With the value of "64" change depending on your sample rates and desired cutoff frequency. Or if your needs get very complex you might need to use a FIR low pass filter. Run some sample data through it in Matlab or Excel (or heavens forbid, some C code) and see what happens.
  38. 1 point

    GPS Pmod

    Hi @cepwin, Welcome to the Digilent Forums! To better assist you I would like a little more information about your project. From the linker script I can see that you are using Vivado 2019.1 and Microblaze and not ZYNQ. 1. What FPGA development board are you using? a. If a Digilent FPGA are you using the Digilent board files? 2. Please attach a screen shot of your block design. Here is a verified Pmod GPS Microblaze project using Vivado 2019.1 and the Arty-A7-35T(Artix-7). I have also attached screens shots of the Block design, SDK, the block automation for microblaze and the tera term serial output. best regards, Jon
  39. 1 point
    Hi @Lesiastas For reception you only need the lines with RX. See the other UART options, like FDwfDigitalUartRateSet, in the Python examples or the manual.
  40. 1 point
    Hi @pgmaser, I would look at the Spartan 3 Resource Center then which has the Xilinx made user guide (including details on the SRAM and flash). I don't believe you have control over the Done LED. Otherwise, I would recommend that you check that the FPGA configuration mode is set up correctly (as described in the Xilinx User Guide). Otherwise, there are also a number of projects for the Spartan 3 listed in it's Resource Center as well. What is the purpose of the second link you provided? It seems to have no relevance to FPGAs. Thanks, JColvin
  41. 1 point
    Hi @Lesiastas You can convert between VB String and byte arrays like this: https://docs.microsoft.com/en-us/dotnet/visual-basic/programming-guide/language-features/strings/how-to-convert-strings-into-an-array-of-bytes https://docs.microsoft.com/en-us/dotnet/visual-basic/programming-guide/language-features/strings/how-to-convert-an-array-of-bytes-into-a-string You could also change the argument declaration in the wrapper to: <MarshalAs(UnmanagedType.LPStr)> ByVal szRx As StringBuilder
  42. 1 point

    Getting Input Phase Programmatically

    Hi @jamesbraza You can use the FDwfAnalogImpedanceStatusInput(hdwf, 1, &gain2, &phase2) The equivalent for the WF IA "input gain" when using IA adapter = gain2 - 1.0
  43. 1 point
    Before I continued my tests with beer, I wanted to make sure of two things: a, the amount of the sample fluid does not influence the impedance values b, the measurement itself does not change the sample fluid so that its impedance is changed at every measurement For case A, I made 3 references with 1 cup, 2 cups and 3 cups of tap water. I used the same source and the same container for all the measurements. Then I made 3 other measurements of the same 3 cups of water. At this point I can conclude that the measurements are fairly harmless, there is only a small amount of change on the dataset after each consecutive measurement. I could probably use lower voltages, which could theoretically reduce the impact further. The amount of the test fluid does change the dataset somewhat, so I will keep that in mind when I go ahead with my further tests and I will try to keep the volume of the fluid fixed. As we could see from my previous post, the temperature is very important, so that's another parameter I will try to manage and keep constant between the tests.
  44. 1 point
    Hi @Lesiastas The samples mean the DIO values collected at the same time. The bits in each sample correspond to DIOs. Like with FDwfDigitalInSampleFormatSet(hdwf, 16) you will get UInt16 samples, where bits from 0 to 15 correspond to DIO 0 to 15. Such UInt16 sample array can be converted to BitArrays like this: Dim bitarray(15) As BitArray For b As Integer = 0 To 15 bitarray(b) = New BitArray(cSamples) For i As Integer = 0 To cSamples - 1 bitarray(b)(i) = System.Convert.ToBoolean((rgwData(i) >> b) And 1) Next Next
  45. 1 point
    Hi, I just have opened a new terminal and launch minicom through the new terminal which works the same way as SDK terminal but I have to close the SDK terminal before connecting to minicom. Thanks @D@n and @jpeyron
  46. 1 point
    Hi @Lesiastas The FDwfDigitalUart can handle only one RX at a time. The captured samples with FDwfDigitalInStatusData represent DIO values as bits, in a 16 bit integer from LSbit DIO-0 to MSbit DIO-15 Like in 128, or hex0080, or binary0000000010000000 the DIO7 is 1 To have DIO7 value as 0/1 from a sample use: (sample>>7)&1
  47. 1 point
    Hi @Lesiastas For FDwfDigitalUart functions you don't have to configure the digital-in or -out. The uart functions will do this. 1. For repeated capture use FDwfDigitalInAcquisitionModeSet acqmodeSingle 0 . The other options depend on your reqirements. 2. Please take a look at the manual and examples in WF SDK DigitalIn_Trigger.py: dwf.FDwfDigitalInTriggerSet(hdwf, c_int(0), c_int(0), c_int(0), c_int(1<<7)) # DIO7 falling edge
  48. 1 point
    hello @Andras ... My IA board (impedance analyzer) arrived a few days ago, but I did not even test it ... But now I have the AI board in my hands. Thanks for your attention. The IA board does not allow a reference electrode (RE) such as figure-item B. Such a scheme would be to not pass current between the working electrode (WE) and a reference electrode (RE). It would be to measure more accurately and discount several other effects in a more automated way. This scheme is not necessarily mandatory. You can use the scheme of just two electrodes as you mention. I am a chemist and I do not have much knowledge of the electrical / electronic part. I imagine that your measurements reflect well the salinity of the water tested. Actually, I think this device - AD2 - could provide a lot of chemical information of Impedance measurement, but I just started reading about it. It's great to know that more people are interested in AD2 and EIS ... so we can build a source of information. Regards, Cleber
  49. 1 point

    Analog Discovery 2 vs Raspberry Pi 3

    Szia and Attila I got a Raspberry Pi 4 last week on release day (got the 2GB version as they sold out of 4GB in half a day) . Just got it plugged into the Analog Discovery and it works! Not really tried it for long but it seems to work reliably, but only well on USB3. On USB3 port, first time it wasn't recognised, but tried again after swapping devices around a then it was detected. Maybe it clashed with my wireless mouse dongle When I tried USB2 port, it connected immediately but I found that every few minutes (max 5-10mins) it would throw a device error window and I would have to clear and reconnect. Maybe RPi foundation kept the FTDI chipset for USB2 and used a new one for USB3 (Pi datasheet only says there is one chipset and it's not FTDI). I will try and soak test tomorrow, but looking good on USB3. So far it has been running 23mins with no apparent glitches, and Chromium tabs open. Waveforms taking 13-20% of CPU in task manager.
  50. 1 point
    I am facing problem in how to use XADC wizard in Nexys 4 DDR board I just want to get the digital conversion of external inputs and access that 12bits of digital output directly. I am new to this and for now, I'm trying to just interlink XADC and a 12bits of DAC to convert an analog input(taken from a function generator) to digital(which will be stored in FPGA) and then use that digital data to generate the same signal at the output of a DAC. It will be really helpful If you can explain/provide a step by step process to do it. You can help using block design or a source code.... whichever way possible.