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Showing content with the highest reputation since 06/19/19 in all areas

  1. 1 point

    use the uart port in nexys 4ddr board

    Hi @shahad, After looking at your original post again you should look at this forum thread about connecting two FPGA through USB UART connection. Both of the Nexys 4 DRR usb uart bridges would be considered a downstream device. Neither of them have a USB Controller. best regards, Jon
  2. 1 point

    Analog Discovery 2 build in Gitlab

    Hi @Rozita, I have moved your question to a more appropriate section of the forum where the engineer most suited to answer your question will be able to see and respond to it. Thanks, JColvin
  3. 1 point
    Hi @jamesbraza The M (input gain) is Vdut/Vref and the < (input phase) is the phase of DUT output vs input. These are Network Analyzer like measurements. Since the IA Adapter module uses this circuit M = (VC1-VC2)/VC2 Here you can see in the Time view the captures of Scope channel 1 (yellow) and 2 (blue):
  4. 1 point
    Hi @jamesbraza Yes, you are right. The application, the IA measures the DUT relative to a reference resistor, using the Scope Channel 1 vs 2 inputs. From this it can calculate the voltage/current. Taking in consideration the scope probe impedance and open/short compensation can calculate further values: impedance Z/Rs/Xs (Rp/Xp rarely used); admittance Y/Gp/Bp (Gs/Bs rarely used); series or parallel equivalent inductance or capacitance... See the following documents: https://cdn.testequity.com/documents/pdf/series-parallel-impedance-parameters-an.pdf 1.6 Equivalent circuit models of components, page 13 : https://literature.cdn.keysight.com/litweb/pdf/5950-3000.pdf
  5. 1 point

    JTAG-HS3, FT232 chip erased

    Hi @jpeyron, Thank You! Best wishes, Harshith
  6. 1 point

    JTAG-HS3, FT232 chip erased

    Hi @thk3695, I sent you a PM about this. best regards, Jon
  7. 1 point


    Hi @Ahmed Alfadhel, We have not had the bandwidth to create an IP Core for the Pmod CLP. We have verilog and VHDL ISE projects that can be alter to work with vivado on the Pmod CLS resource center . You will need to use the UCF file as a reference for the XDC file. You should be able to use the ADD a Module function in the Vivado Block design as discusses in this forum as well as in this xilinx YouTube to use these projects with Microblaze. You can use the add a module function as described in this Xilinx YouTube. The add a module function allow users access to the AXI bus with their VHDL Entities/Verilog Modules. Here is a forum thread that discusses this as well. best regards, Jon
  8. 1 point

    Pmod da3 reconstruction filter

    Hi @lwew96, We have not used a reconstruction filter. I did find a paper that discusses a reconstruction filter with the AD5541 here. Hopefully one of the more experienced community members will have some input for you as well. best regards, Jon
  9. 1 point
    Hi @jamesbraza, I'm not an expert on the internal workings of WaveForms (that'll be @attila) but I'll see if I can answer your questions: What is the purpose of marking as series or parallel -- The purpose of looking at the series or parallel configuration is because you will get different results depending on the configuration; this website illustrates this for a set of 3 capacitors. Does WaveForms do additional computations with this information? -- Aside from the other impedance things that can be calculated (admittance, inductance, etc), I don't believe it does anything else. What if my DUT has multiple inductors/capacitors in a network, such that they are sort of both in a series/parallel arrangement? -- Generally, I imagine if you were interested in the individual sections you would measure them separately. Admittedly, I'm not certain the best way to consider an overall system if you are just treating it as a black box though. With regards to the Element parameter, I'm not certain. I would also recommend looking at this thread for some additional details. Thank you, JColvin
  10. 1 point

    FIR compiler 7.2 stopband

    @Ahmed Alfadhel, (Just read the prior, prior note--showing the beginnings of an impulse response ...) To get the "answer" from a trace file, there's a couple of things you can do: I use gtkwave for viewing traces. It has the option to view something as an analog value. You can do that and generally reflect that your impulse response has the right shape. That's useful, but it won't get you from a -20 dB stopband to a -80 dB stop band. What you really need to do is to take that impulse response and run an FFT on it. No, I don't mean dumping the impulse response into an FFT component, but rather taking the values of the impulse response from the filter and sending those values into an FFT. This often requires the ability to save values from your trace into a file of some kind of type that Matlab or Octave can read. I've done the same with a filter of my own, and you can red my report on it (and the links to how I did it) here. Dan
  11. 1 point

    FIR compiler 7.2 stopband

    I think you should go back to the basics. Set up a simple FIR filter e.g. [1 2 3 4 5 6 7] impulse response, and get your simulation working that an input of [..0, 1, 0.....0] gives something that resembles [1 2 3 4 5 6 7]. In your simulation this is not the case (the filter has 123 different coefficients, your simulation shows only a single output value).
  12. 1 point
    Hi @YaBoyRock, Glad to hear you were able to find the demo's in question. best regards, Jon
  13. 1 point
    Hi @YaBoyRock, There are two demo's available for the DJTG one is called DJTGDemo and the other is called DJTGTwoWireDemo as shown in the attached screen shot below. Its my understanding that the DJTGDemo is made to work with a 4-wire set up. best regards, Jon
  14. 1 point
    Hi @jamesbraza, The series vs parallel values for resistance/reactance/inductance/etc refer to the device or system you are measuring these traits of, i.e. are the resistors and/or capacitors arranged in a series configuration or are they arranged in a parallel configuration. The reason both are listed in the Impedance tool is because the WaveForms software does not know how the device under test (the DUT block shown in the images of the 'impedance.html' page) is organized since it just applies a waveform and compares what the two oscilloscope channels see as the response and performs a variety of calculations to get the values you see in the Meter and Analyzer views. Let me know if you have any questions about this. Thanks, JColvin
  15. 1 point
    Hi @YaBoyRock, Welcome to the Digilent Forums! It my understanding that the DtjgDemo.cpp is made for 4-wire. Is there a specific function in the DjtgTwoWireDemo.cpp that you are interested in? Have you looked at the Digilent Adept JTAG Interface(DJTG) Programmer's Reference found in the \digilent.adept.sdk_v2.4.2\doc folder? best regards, Jon
  16. 1 point

    FIR compiler 7.2 stopband

    @Ahmed Alfadhel, Cool, you know how your filter should respond! But ... does it respond that way? You were suggesting that your filter wasn't working. One of the first things to check is whether or not the filter, as implemented, continues to have the response you designed. Measuring the impulse response, and then comparing it to your predicted response above, can be valuable to that end. There are a lot of bugs that might get caught by this, to include issues associated with properly setting the coefficients in memory, truncating them to fixed bit widths, etc. Dan
  17. 1 point
    Hi @kuc3, Welcome to the Digilent Forums! I have moved your thread to a sub-section where more experienced embedded linux engineers look. best regards, Jon
  18. 1 point

    FIR compiler 7.2 stopband

    yes, it's the highest positive 16 bit signed number 32767 (0x8FFF is the smallest negative number, -32768). You could also consider 0x4000, which is a single bit, makes your coefficients easier to recognize in the output (because multiplying with this number is a single bit shift operation).
  19. 1 point

    FIR compiler 7.2 stopband

    That's a Verilog thing.. A 16-bit hex value, equivalent to 32767 decimal. The VHDL equivalent would be x"7FFF"
  20. 1 point
    Hi Jon, That makes sense, I guess I shouldn't expect consistent results out of undocumented behaviour. Thanks again for all your help. I think that solves my problem, though in the process of solving this one, another problem came up. I guess thats a topic for another thread... Thanks, Daniel
  21. 1 point
    Hi @Niranjan, You should be able to use 2 Pmod USBUART as communication between two ZC706 . You would use the Pmod Ports along with something like a micro usb to micro usb . In the block design use the Uartlite IP Core or the second UART in the ZYNQ processor and make that UART bus external. You will need to constrain the UART pins in the wrapper in an xdc file. After you generate a bitstream and launch SDK here is a polled SDK example that should be a good reference. thank you, Jon