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  1. 3 points
    hearos

    FTDI chip not recognized anymore

    I have not had any activity listed when trying the "dmesg" so I went to buy a new cable, and that actually was it. Thank you for the hint!
  2. 3 points
    xc6lx45

    FTDI chip not recognized anymore

    I think it's Linux... Try the "dmesg" command immediately after plugging or unplugging. It should show some related events. The obvious, try with a different computer and a different cable. Especially cables fail often.
  3. 2 points
    xc6lx45

    FIR compiler 7.2 stopband

    ... and how about a simple impulse response test (feed a stream of zeroes with an occasional 1 and check that the filter coefficients appear at the output). Just wondering, isn't there a "ready / valid" interface also at the output if you expand the port with "+"?
  4. 2 points
    D@n

    FIR compiler 7.2 stopband

    @Ahmed Alfadhel, Why not run a simulated sweep through the band and read out what the actual filter response is? Dan
  5. 2 points
    Hi @NikosFotias, I heard back from our design engineer about this; the recommend input ranges are 0V to 5V, but the absolute maximum ratings for the PWM inputs are -58V to 58V. Thank you, JColvin
  6. 1 point
    jpeyron

    Pmod da3 reconstruction filter

    Hi @lwew96, We have not used a reconstruction filter. I did find a paper that discusses a reconstruction filter with the AD5541 here. Hopefully one of the more experienced community members will have some input for you as well. best regards, Jon
  7. 1 point
    Hi @jamesbraza, I'm not an expert on the internal workings of WaveForms (that'll be @attila) but I'll see if I can answer your questions: What is the purpose of marking as series or parallel -- The purpose of looking at the series or parallel configuration is because you will get different results depending on the configuration; this website illustrates this for a set of 3 capacitors. Does WaveForms do additional computations with this information? -- Aside from the other impedance things that can be calculated (admittance, inductance, etc), I don't believe it does anything else. What if my DUT has multiple inductors/capacitors in a network, such that they are sort of both in a series/parallel arrangement? -- Generally, I imagine if you were interested in the individual sections you would measure them separately. Admittedly, I'm not certain the best way to consider an overall system if you are just treating it as a black box though. With regards to the Element parameter, I'm not certain. I would also recommend looking at this thread for some additional details. Thank you, JColvin
  8. 1 point
    D@n

    FIR compiler 7.2 stopband

    @Ahmed Alfadhel, (Just read the prior, prior note--showing the beginnings of an impulse response ...) To get the "answer" from a trace file, there's a couple of things you can do: I use gtkwave for viewing traces. It has the option to view something as an analog value. You can do that and generally reflect that your impulse response has the right shape. That's useful, but it won't get you from a -20 dB stopband to a -80 dB stop band. What you really need to do is to take that impulse response and run an FFT on it. No, I don't mean dumping the impulse response into an FFT component, but rather taking the values of the impulse response from the filter and sending those values into an FFT. This often requires the ability to save values from your trace into a file of some kind of type that Matlab or Octave can read. I've done the same with a filter of my own, and you can red my report on it (and the links to how I did it) here. Dan
  9. 1 point
    xc6lx45

    FIR compiler 7.2 stopband

    I think you should go back to the basics. Set up a simple FIR filter e.g. [1 2 3 4 5 6 7] impulse response, and get your simulation working that an input of [..0, 1, 0.....0] gives something that resembles [1 2 3 4 5 6 7]. In your simulation this is not the case (the filter has 123 different coefficients, your simulation shows only a single output value).
  10. 1 point
    Hi @jamesbraza, The series vs parallel values for resistance/reactance/inductance/etc refer to the device or system you are measuring these traits of, i.e. are the resistors and/or capacitors arranged in a series configuration or are they arranged in a parallel configuration. The reason both are listed in the Impedance tool is because the WaveForms software does not know how the device under test (the DUT block shown in the images of the 'impedance.html' page) is organized since it just applies a waveform and compares what the two oscilloscope channels see as the response and performs a variety of calculations to get the values you see in the Meter and Analyzer views. Let me know if you have any questions about this. Thanks, JColvin
  11. 1 point
    Hi @YaBoyRock, Welcome to the Digilent Forums! It my understanding that the DtjgDemo.cpp is made for 4-wire. Is there a specific function in the DjtgTwoWireDemo.cpp that you are interested in? Have you looked at the Digilent Adept JTAG Interface(DJTG) Programmer's Reference found in the \digilent.adept.sdk_v2.4.2\doc folder? best regards, Jon
  12. 1 point
    D@n

    FIR compiler 7.2 stopband

    @Ahmed Alfadhel, Cool, you know how your filter should respond! But ... does it respond that way? You were suggesting that your filter wasn't working. One of the first things to check is whether or not the filter, as implemented, continues to have the response you designed. Measuring the impulse response, and then comparing it to your predicted response above, can be valuable to that end. There are a lot of bugs that might get caught by this, to include issues associated with properly setting the coefficients in memory, truncating them to fixed bit widths, etc. Dan
  13. 1 point
    xc6lx45

    FIR compiler 7.2 stopband

    yes, it's the highest positive 16 bit signed number 32767 (0x8FFF is the smallest negative number, -32768). You could also consider 0x4000, which is a single bit, makes your coefficients easier to recognize in the output (because multiplying with this number is a single bit shift operation).
  14. 1 point
    hamster

    FIR compiler 7.2 stopband

    That's a Verilog thing.. A 16-bit hex value, equivalent to 32767 decimal. The VHDL equivalent would be x"7FFF"
  15. 1 point
    Thank you, JColvin! Last night I hooked it up to the Analog Discovery 2 and I read much better values than the "max bouncing" values in the datasheet of that small (6mm x 6mm) push button. It's actually so good that it's hard to start playing with capacitors to make it better. I'll try again later today with the oscilloscope in higher resolution (startup mode of the AD2). Stuk
  16. 1 point
    jpeyron

    Measure Clock on Arty

    Hi @PoojaN, Here is project I made in Vivado 2017.4 using the ODDR IP Core. I made two ports by right clicking on the block design. Both are type clock and one direction is input at 100 MHz and the other direction is an output. I connected the appropriate pins from the ODDR to the ports. I then created a wrapper. With the wrapper information I added a xdc using using the pin names in the wrapper. I then generated a bitstream. Next I opened the Hardware Manager and configured the Arty A7 with the bitstream. I then probed the pin 1 on JA (the pin I used for this project) with the Analog Discovery 2. It is showing a 400 KHz signal. I have included screen shots of the process. best regards, Jon
  17. 1 point
    Hi @dmishins, Welcome to the Digilent Forums! Please attach a screen shot of your Block design. Did you connect the 200 MHz clock to the MIG as instructed in section 10? What did you set the local memory and cache when running clock automation for Microblaze? best regards, Jon
  18. 1 point
    SmashedTransistors

    BASYS3 and Axoloti

    Thanks @OvidiuD, I'll take one step after another and the forums are quite a good source of knowledge. So far, I plan to start with very basic schemes in order to understand how Vivado works. Then I will work on communicating with the Axoloti through SPI. Best regards
  19. 1 point
    jpeyron

    pmod wifi

    Hi @harika, The board connects to the router through the Pmod WIFI. That is why you need the login and password for the router added in the HTTPServerConfig.h. The mode jumper would be set to SD if you were booting your project from the SD card reader. In this case the project is just using the SD card reader and not booting from the SD card reader. You should have the Mode Jumper set to JTAG. best regards, Jon
  20. 1 point
    xc6lx45

    FIR compiler 7.2 stopband

    true but it's a five-line job e.g. in Verilog reg[15:0] counter = 0; reg [15:0] impulse = 0; always @(posedge clk) begin counter <= counter + 1; impulse <= (counter == 0) ? 16'h7FFF : 0; end plus the protocol interface (e.g. trigger a new valid sample if counter[7:0] == 0)
  21. 1 point
    Hi @jpeyron @xc6lx45 Thankyou for the quick reply! Changing the clock frequency setting worked!! Thanks a lot!
  22. 1 point
    Musko

    LabVIEW and IIO data sources

    Thanks for pointers.
  23. 1 point
  24. 1 point
    I did some research on Xilinx.com and found this answer record: https://forums.xilinx.com/t5/Embedded-Development-Tools/XSDB-Server-ERROR-Hsi-55-1545-Problem-running-tcl-command/td-p/834915 I had two floating inputs on my concatenation block and once I connected these project creation proceeded correctly.
  25. 1 point
    JColvin

    LabVIEW and IIO data sources

    Hi @Musko, You would receive better support for this question by posting on the National Instruments forum, https://forums.ni.com/t5/Discussion-Forums/ct-p/discussion-forums?profile.language=en; the staff here on the Digilent forum are really only familiar with the LINX add-on for LabVIEW and the LabVIEW 2014 Home Edition. I'm sorry I could not be of more help. Thank you, JColvin
  26. 1 point
    Finally working! Brief description: On right monitor is ssh session from my devel PC to Zyboz7-20 where I start Qt applications (framebuffer and sysinfo on attached picture). Front monitor is connected to ZyboZ7-20 HDMI output port. Monitor resolution is SXGA (1280x1024@60fps). FPGA: - Build with Vivado 2016.4 - Data path for HDMI output: /dev/fb0 DDR image buffer --> Zynq AXI HP port --> AXI Protocol Converter IP (AXI3 to AXI4) --> VDMA IP (mm2s only) --> AXI4 Stream to Video IP --> Digilent RGB to DVI IP --> HDMI connector Video control signals are from Video Timing Controller IP (1280x1024p, Pixel clock is 108MHz). On SD card: - Boot image containing: FSBL, U-boot (Xilinx git tag xilinx-v2017.3), LX 4.6 kernel (configured and build from Xilinx git tag xilinx-v2016.4) and Buildroot-2017.08.1 - Modified Simple FrameBuffer driver. - Xilinx DMA driver. - My custom driver to control FPGA modules (VTC, Xilinx Performance monitor and some others I have in design). - Cross compiled Qt-4.8.6 examples (analogclock, framebuffer) and Qwt-6.1.3 examples (sysinfo, cpuplot). TODOs: - Simple FrameBuffer driver does not starts Xilinx DMA driver transfers, so I have to configure VDMA IP registers manually. But this is good enough for my first run and proof of concept. I will switch to and continue with DRM device driver. - Inputs (mouse and keyboard) to control Qt application.
  27. 1 point
    Hi @Abdul Qayyum, I am not directly seeing anything wrong with your FSM. Here is a UART RX TX verilog module and here that should be useful for your project. best regards, Jon
  28. 1 point
    JColvin

    micro-USB cables for Zedboard?

    Hi @GMA, As long as they are not "charging only" cables, then yes they will be able to transfer data as well. Naturally, the cables do not facilitate the software side of the data transfer, but there are a number of existing materials to help get the software side of things working. Let me know if you have any other questions. Thanks, JColvin
  29. 1 point
    Hi @sgrobler, I guess it hasn't been updated for OpenLogger; I personally wasn't aware of an Android app for WFL in the first place. I'll ask about the plans for that, though I suspect since I don't recall hearing about it that there aren't any immediate plans to get it updated. I do agree about the phone browser not being ideal; even in landscape mode, it's difficult to see any relevant details. Thanks, JColvin
  30. 1 point
    xc6lx45

    FIR compiler Amplitude

    Well, I'm not familiar with this particular tool. But at a quick glance, I think you need to set "Quantization" to e.g. "quantize only". Then the field "Coefficient fractional bits" becomes enabled. If it doesn't fall into place easily, start with a simple example, e.g. import a 0 0 256 0 0 FIR with 8 fractional bits and you should see 0 dB across the frequency response. Hint: for an order-of-magnitude cross-check you can get the DC gain of a FIR filter by summing its coefficients. In your example, this should be around 0.0001 for ~ -80 dB @ 0 Hz And PS: one possible explanation (this is a long shot) is that you designed for 12 bit coefficients and exported in 32 bits => +20
  31. 1 point
    jpeyron

    ZedBoard and PmodCAN

    Hi @YellowYoung, Welcome to the Digilent forums! The PmodCAN facilitates CAN communication to another device through the PL.The PmodCAN uses SPI communication to communicate between the host board and itself. It would not be able to connect to the CAN on the PS. To use the CAN bus on the PS you would need to use the MIO Pmod JE1 as discussed in the user guide for the Zedboard here in section 2.9.2 Digilent Pmod Compatible Headers (2x6). The user guide states the bank that the MIO pins are connected to a 3.3V bank so you would need to make a level shifting circuit for CAN communication to work since CAN uses voltage level as part of its communication. If all you need to do is communicate data from the Zedboard using CAN communication. Then you can send data from the PS to the PL and then send that data through the PmodCAN. Here is an Avnet forum thread that discusses sending data from the PS to the PL. Here is a Xilinx forum thread that initially discusses how they accomplished sending data from the PS to the PL. best regards, Jon
  32. 1 point
    xc6lx45

    FIR compiler Amplitude

    My first guess is that the tool needs to know the position of the decimal point of your number format. It's off by 20 bits (=> 1048576 => 120 dB). Fixed point knows only integers, so it's a matter of interpretation.
  33. 1 point
    bogdan.deac

    OpenCV and Pcam5-c

    Hi @Esti.A, I attached the files. filter2d_test.zip
  34. 1 point
    Yep, seen that they were back online. Thanks, Jon
  35. 1 point
    jomoengineer

    Howdy from NorCal

    Thanks Jon. And thanks for the links. Cheers, Jon
  36. 1 point
    Ionel

    Petalinux in Cora z7 not finding RTC

    Hello @gmodia Please try picocom: $ sudo picocom -b 115200 /dev/ttyUSB1 Note: this will work only after the device is powered on and the device /dev/ttyUSB1 is provided by your machine kernel. You could watch when that happens in a second terminal window by issuing: dmesg -w
  37. 1 point
    The example I posted would work for Linux or Mac with "common" tools installed. As to Windows... can't really help much there. git's not part of Python, it's used for managing code; you can achieve the same end result here by downloading the ZIP from https://github.com/bdlow/dlog-utils-portable/archive/master.zip and unzipping to a folder. Virtual environment support is a standard part of Python 3; you can skip that if you like but without virtual environments eventually your Python installation will end up like this: https://xkcd.com/1987/ Ah, of course, in Windows `activate` is a batch script not a shell script: https://www.techcoil.com/blog/how-to-create-a-python-3-virtual-environment-in-windows-10/
  38. 1 point
    @sgrobler: I've tweaked the project to hopefully make it simpler to install the dependencies (Kaitai Struct v0.9). If you have Python 3 installed, it should simply be a matter of: % git clone https://github.com/bdlow/dlog-utils-portable.git Cloning into 'dlog-utils-portable'... remote: Enumerating objects: 26, done. remote: Counting objects: 100% (26/26), done. remote: Compressing objects: 100% (19/19), done. remote: Total 26 (delta 8), reused 20 (delta 5), pack-reused 0 Unpacking objects: 100% (26/26), done. % cd dlog-utils-portable dlog-utils-portable% ls LICENSE dlog.ksy dlogcsv.py requirements.txt README.md dlog.py examples # set up and activate a Python virtual environment: dlog-utils-portable% python3 -m venv .venv dlog-utils-portable% . .venv/bin/activate # install the 0.9 runtime in the virtual environment: (.venv) dlog-utils-portable% pip install -e 'git+https://github.com/kaitai-io/kaitai_struct_python_runtime.git@0e3f6e0#egg=kaitaistruct' Obtaining kaitaistruct from git+https://github.com/kaitai-io/kaitai_struct_python_runtime.git@0e3f6e0#egg=kaitaistruct Cloning https://github.com/kaitai-io/kaitai_struct_python_runtime.git (to revision 0e3f6e0) to ./.venv/src/kaitaistruct Did not find branch or tag '0e3f6e0', assuming revision or ref. Installing collected packages: kaitaistruct Running setup.py develop for kaitaistruct Successfully installed kaitaistruct # run it! (.venv) dlog-utils-portable% ./dlogcsv.py ./examples/openlogger.dlog > openlogger.csv Header Information log format: openlogger stop reason: normal number of samples: 27097 voltage units: mV sample rate: 10E+3 Sa/s delay: 0 s number of channels: 3 channel map: [1, 2, 3] (.venv) dlog-utils-portable% less openlogger.csv
  39. 1 point
    Hi, a quick update: I released a new version 1.1 that supports variable address width in the protocol. Functionality is unchanged, but performance will improve for scattered writes and reads in the lower address range: 0x000000xx range saves 3 bytes per transaction, 0x0000xxxx 2 bytes and 0x00xxxxxx 1 byte. There was also a missing -datapath_only in the constraints, which made the timing report hard to read (the intention behind the set_max_delay constraint was simply "tool, don't make this path between clock domains any slower than x ns end-to-end").
  40. 1 point
    Jon, Thank you kindly for your help - everything worked just like you said! Best, Zhanneta
  41. 1 point
    Hi @FPGAMiner, Welcome to the Digilent Forums. We have not worked with Altera's IDE or on of their FPGA's. The GitHub link for the OdoCrypt FPGA Miner states under requirements that it currently only supports Intel (Altera) FPGAs on Linux hosts. We have not ported one of Altera's projects to work with Vivado/Xilinx FPGA's. We do have petalinux platforms for the Zybo Z7 here. I would think that after installing petalinux on the Zybo Z7 you would then need to duplicate their functions. Unfortunately we have no experience with this process and would not have useful advice. Hopefully one of the more experienced community members will have some helpful input for you. I would also suggest reaching out to the creator of the OdoCrypt FPGA Miner to see if they have any suggestions for getting this project working with a Xilinx FPGA. best regards, Jon
  42. 1 point
    D@n

    Bit error rate (BER) calculations

    @Ahmed Alfadhel, I like to use a basic LFSR when doing a BER test. The LFSR can be used to generate a pseudorandom bit-sequence in the transmitter. In the receiver, assuming you've used an LFSR, then there exists a linear combination of the input bits that will annihilate the sequence (turn all the bits to zero). You can then measure BER based upon the number of bits that are zero at the output. The biggest catch is that, depending upon the number of input bits required to generate the annihilator, you may end up with an estimate that's 3x larger than it needs to be (assuming a three tap annihilator). A little bit of scaling on the back end will then return this to the BER measurement you are looking for. The exception is that in really low BER environments, this method becomes too optimistic due to the math at the back end. This article should tell you what you need to build an LFSR. You'll probably want an LFSR with a longer period, though (google "maximal length LFSR"), and one that can be annihilated easily (google "feedthrough randomizer"). I know Sklar's Digital Communications has a table of polynomials you can use, as does Schneiers Applied Cryptography. You are also likely to find similar tables on line if you google for them. Dan
  43. 1 point
    jimge

    BASYS3 connection issues

    Hi all - I've searched through old threads and see some posts about this issue, but nothing in them has worked for me. I have a BASYS3 board, and I can't get Vivado to see it. I've tried on both Ubuntu and Windows 10. I'm trying to follow the simple LED tutorial on the Digilent web site. Here's what I've tried so far: - Made sure board is jumpered for JTAG and powered up - Made sure drivers were installed (manually went in and ran the batch files in cable_drivers/nt64 and ensured that both the pcusb and Digilent drivers successfully installed) and rebooted - Made sure the Basys3 board was copied over into board_files, shows up in the UI, and is the selected hardware for the project When I bring up hardware manager with the board plugged in and run auto connect, all I see is the local host server node with no devices under it. Running refresh_hw_server tells me no hardware targets are connected to the machine. Anyone have other ideas? Thanks! EDIT: Solved. Helps to use a USB cable that isn't power-only.
  44. 1 point
    Sduru

    Vivado sysnthesis fail..Pcam

    Hello Dear @jpeyron I've already solved the problem. It was related to selecting wrong language C instead of C++ when creating new application project. PCAM project was written in C++, but I wrongly selected C! After I corrected that mistake, now there is no any linking error. Thanks...
  45. 1 point
    >> new to fpga and zybo´╗┐ >> i want to use open cv but i dont know where to start from Just thinking aloud: Independently of making hardware work, it might be a good idea to forget everything about hardware and video. Spend some time with openCv and offline bitmap examples on a standard Linux machine, say a virtual Linux box or a Raspberry Pi. Can speak only for myself, but I rather fight my dragons one at a time, not all at once
  46. 1 point
    Hi @ammolytics, This forum section will work. It definitely sounds like an interesting project. The main hurdle that I'm seeing with this project is that you will either need multiple Discovery's and OpenLogger to collect all of the analog inputs and the digital inputs. Accelerometers tend to provide their information in a digital fashion (such as through SPI or I2C) so while the Analog Discovery 2 can read in this data, the OpenLogger is not able to directly interpret protocol messages. However, the Analog Discovery 2 needs to be connected to a laptop to store the data, which you stated you do not need. The 3 strain gauges will likely have analog outputs as well as the output from the Magnetospeed Chronograph that you linked, though I don't know if it provides 1 or 2 analog outputs (since it uses 2 hall effect sensors). So that is 3 analog inputs required, plus 2 digital inputs (from the 2 hall effect sensors), as well as 3 digital inputs that will likely require interpretation. Looking at the sources you linked, it does not appear the required sample rate will need to be incredibly fast (guessing based the links where it said the stress wave travels from receiver to muzzle in about 0.12 mS, or 120 microseconds). Based on this, you likely could use a 1 MHz sampling rate (1 microsecond resolution) to capture all of the data you needed, of which the Analog Discovery 2 can achieve, while the OpenLogger will be limited (while using 3 analog inputs) to 166.7 kS/s (6 microsecond resolution), though depending on how many sample points you need, this may be sufficient for you. The main thing I'm getting at is that I don't think that either the OpenLogger or the Analog Discovery 2 will an all-in-one solution for you; the Analog Discovery 2 because it only has 2 analog inputs and you need at least 3 (and it can't store data to an SD card), and the OpenLogger because it doesn't directly interpret data protocols that will likely be coming from the accelerometers. To be fair, the OpenLogger could in theory receive all of the bit-banged data accelerometer data on digital inputs and then you interpret them later, but the logging functionality (or at least the ability to read the logged data) isn't integrated yet and this also presumes that accelerometers will power on and start sampling data in the exact configuration you want upon start-up with no instructions provided to them which is not a guarantee. What I would probably recommend looking into would be using a microcontroller or microprocessor to collect the data and store it on an SD card, since there are a number of microcontollers that have both enough analog and digital inputs and you can program them to to interpret the protocol data from the accelerometers for you and send only the relevant data to an SD card. You'll likely need to use an external analog-to-digital converter if the voltages you are measuring are outside of the ranges that the on-board ADC can accept (usually either 0V to 3.3V or 0V to 5V and Magnetospeed sensor you linked was showing 7.6V to 9V readings). Let me know if you have any questions about this. Thanks, JColvin
  47. 1 point
    jpeyron

    Vivado sysnthesis fail..Pcam

    Hi @Sduru, I found a xilinx forum that that discusses this issue here. For their project the .project and .cproject files were referencing an obsolete hw_platform that no longer existed. They manually edited the files to the new hw_platform--now the design worked. Did you use the 2018.2 project from the release page here? Did you import the fsbl and pcam_vdma_hdmi from the sdk_appsrc folder in the Zybo-Z7-20-Pcam-5C-2018.2.1 folder? best regards, Jon
  48. 1 point
    Hi Ferda I am currently at the stage of designing an external adapter PCB similar to this presented video (I read the whole post about it on eevblog). This adapter should at least solve some of the problems you're talking about (eg stronger output based on LT1210 or BUF634). PS. Do you have a link to the program that the author of the attached video use?
  49. 1 point
    D@n

    Beginner DSP Projects

    @ho0pla, You should thank @zygot for such sensible advice: build it in Matlab or Octave, get it working, then port to hardware. Let me add another step in the middle, though, that I'm sure @zygot would agree with: Octave, then simulation, then hardware. After that, the sky's the limit! Well, you might want to study a particular application of interest as well. DSP is such a varied field, and so many things from so many fields are called DSP that ... well, it's hard for me to pontificate from here. Still, if you are interested in some examples, feel free to read some of ZipCPU's DSP articles on line. (The ZipCPU is the name of a CPU/processor I've built, and now blog about under the name ZipCPU.) They tend to hit on many topics surrounding DSP theory and implementation. Indeed, I recently posted a rather cool simulation demo of a spectrogram to github. There's a nice screenshot avaialble there too in order to give you an idea of how far you might get with simulation. Perhaps these ideas might stir up in your mind a project you'd like to try? Dan
  50. 1 point
    xc6lx45

    Beginner DSP Projects

    Well, if you want my opinion, DSP on FPGA is a fairly specialized niche application. It's a long walk to come up with a project that really fits into that niche, justifying an FPGA (rather pair a $0.50 FPGA for programmable IO with one or more high-end DSPs for the number crunching if someone claims "we need an FPGA"). For studying, it can be "interesting" in a sense that you get to know quite a few dragons on a first-name basis. But then, is it productive to spend weeks on fixed point math when everybody else uses floats on a DSP / CPU when "time-to-market" is #1 priority. Maybe not. DSP is more fun in Matlab (Octave). And there is no point in FPGA for performance unless you have exhausted the options at algorithm level (again, exceptions e.g. well-defined brute-force filtering problems) A lot of the online material is "sponsored" by companies that sell FPGA silicon by the square meter (Yessir. We have Floats!). But this is largely for the desperate and ill-informed (of course, there are viable use cases - say high volume basestations or automotive with need for EOL in a decade or two. As said, a niche application). When you take the direct route, you'll run into a question like, "how on earth could I implement an audio mixing console when the FPGA has only 96 multipliers". Challenge me or anybody who has read some books and you'll find it can be done on a single multiplier (say, 100 MHz at 96 kHz is 86 multiplications per sample for 12 channels. It's just an example. In reality I'd use a few with "maintainability" of the code my major concern). The point is, the skill ceiling is fairly high but so is the design effort. It only makes sense if I plan to sell at least a hundred gazillon devices. On the other hand, if you separate DSP and FPGA, you'll find that a lot of the Matlab (Octave) magic maps 1:1 to real life on any modern CPU platform by importing e.g. the "Eigen" library into my C code.