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  1. 2 points
    Hi @attila Thank you again for all the support you've provided me for the past weeks. I am now capable of receiving more than 409 characters using the Wrapper I created base from your example. It uses the Record acquisition mode and I set the buffer size to 3 million for now. I'll increase it when the need arises. I used 1 UART controller and branched out its Tx pin to 2 DIO pins of the AD2 (DIO #0 & 1). I transmitted 500 characters: (If Record mode is not the acquisition mode, the received result will be blank) For DIO # 0, it received: with a length of: For DIO #1, it received: with a length of: I could not have done it without your guidance, thank you again and more power to you and Digilent Best regards, Lesiastas
  2. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  3. 2 points
    kwilber

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  4. 2 points
    Hi @neocsc, Here is a verified Nexys Video HDMI project updated from Vivado 2016.4 to Vivado 2017.4. You should be able to find the updated project in the proj folder . Here is a GitHub project done in HDL using the clocking wizard, DVI2RGB and RGB2DVI IP Cores for another FPGA. Here is a unverified Nexys Video Vivado 2017.4 HDMI pass through project made from the linked Github project. In the next few days I should have the bandwidth to verify this project. thank you, Jon
  5. 2 points
    The warning you pasted is benign and simply means there are no ILAs present in your design. The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design. Finally, @elodg gives some great troubleshooting information in this thread.
  6. 2 points
    Hi @akhilahmed, In the mentioned video tutorial, the leds are controlled using "xgpio.h" library but the application is standalone. If you want to use a linux based application you have to use linux drivers for controlling. In the current Petalinux build, which is used in SDSoC platform, UIO driver is the best approach. Steps: 1. Vivado project generation: - Extract .dsa archive from /path_to_sdsoc_platform/zybo_z7_20/hw/zybo_z7_20.dsa - Launch Vivado - In Tcl Console: cd /path_to_extracted_dsa/prj - In Tcl Console: source rebuild.tcl - In this point you should have the vivado project which is the hardware component of SDSoC platform. Open Block Design. Change to Address Editor Tab. Here you will find the address for axi_gpio_led IP: 0x4122_0000 2. Petalinux UIO driver: - Launch SDx - Import zybo-z7-20 SDSoC platform - Create a new SDx linux based project using a sample application (e.g. array_zero_copy) - Build the project - Copy the files from /Dubug/sd_card to SD card - Plug the SD card in Zybo Z7. Make sure that the JP5 is set in SD position. Turn on the baord - Use your favorite serial terminal to interact with the board (115200, 8 data bits, 2 stop bits, none parity) - cd to /sys/class/uio - if you run ls you will get something like: uio0 uio1 uio2 uio3 uio4 uio5 - Now you have to iterate through all these directories and to search for the above mentioned axi_gpio_led address: 0x4122_0000 - For example: cat uio0/maps/map0/addr will output: 0x41220000, which means that the axi_gpio_led can be accessed using linux uio driver through uio0 device. - Code: #include <stdio.h> #include <stdlib.h> #include <sys/ioctl.h> #include <sys/mman.h> #include <stdint.h> #include <unistd.h> #include <fcntl.h> #define UIO_MEM_SIZE 65536 #define UIO_LED_PATH "/dev/uio0" void UioWrite32(uint8_t *uioMem, unsigned int offset, uint32_t data) { *((uint32_t*) (uioMem+offset)) = data; } uint32_t UioRead32(uint8_t *uioMem, unsigned int offset) { return *((uint32_t*) (uioMem+offset)); } void led_count_down(uint8_t *ledMem) { uint8_t count = 0xF; uint8_t index = 0; for (index = 0; index < 5; index++) { UioWrite32(ledMem, 0, count); count = count >> 1; sleep(1); } } int main() { // Set Leds as output int led_fd = open(UIO_LED_PATH, O_RDWR); uint8_t *ledMem = (uint8_t *) mmap( 0, UIO_MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, led_fd, (off_t)0); UioWrite32(ledMem, 4, 0x0); // Set all leds as output while(1) { // Start led count-down led_count_down(ledMem); } return 0; } - Build the project and copy the content of Debug/sd_card on SD sd_card - Power on the board and connect to it using a serial terminal - run the following commands: mount mmcblk0p1 /mnt cd /mnt ./project_name.elf - Result: A countdown should be displayed on leds.
  7. 2 points
    JColvin

    Arty A7 flash chip

    Hi @D@n, I believe the new part that is used in the Arty A7 boards (and other A7 boards) is now a Spansion S25FL128SAGMF100; based on old schematics, I believe this was added in Rev D of the Arty A7 (dated August 2017), though I do not know when that particular Rev was then released (or if it even was released) to the public. I confirmed that the Arty S7 also uses this part and I wouldn't be surprised if most of our other Artix 7 based boards use it now as well. I've requested that the chip name and images are updated in any appropriate tutorials and requested that the pdf version of the reference manual (updated wiki) is updated as well. Thanks, JColvin
  8. 1 point
    Hi @P. Fiery Thank you for the observations.
  9. 1 point
    D@n

    Verilog

    @Ahmed Alfadhel, Perhaps the most complete tutorial out there is asic-world's tutorial. You might also find it the most vacuous, since although it tells you all the details of the language it doesn't really give you the practice or the tools to move forward from there. There's also a litexsoc (IIRC) by enjoy-digital that I've heard about, but never looked into An alternative might be my own tutorial. Admittedly, it's only a beginner's tutorial. It'll only get you from blinky to a serial port with an attached FIFO. That said, it does go over a lot of FPGA Verilog design practice and principles. It also integrates learning how to use a simulator, in this case Verilator, and a formal verification tool, such as SymbiYosys, into your design process so that you can start learning how to build designs that work the first time they meet hardware. I'm also in the process of working to prepare an intermediate tutorial. For now, if you are interested, you'd need to find most of the information that would be in such a tutorial on my blog. (It's not all there ... yet, although there are articles on how to create AXI peripherals ..) Feel free to check it out. Let me know what you think, Dan
  10. 1 point
    Hi @jfranz-argo, @kharoonian, and @Franky32, I apologize for the delay. I have sent each of you a PM about this. Thanks, JColvin P.S. to other readers, be sure not have Digilent boards attached when you are reprogramming other FTDI devices. A long list of users will tell you it's an easy mistake to accidentally select the wrong device.
  11. 1 point
    Hey Paolo, I'm glad you found my videos helpful! I've been working on other projects, but if you have any other ideas for videos that you would find helpful let me know. Kaitlyn
  12. 1 point
    @ManserDimor Here's a general rule of thumb. Differential traces, whether laid out as differential or not must be length matched as best as possible. High speed bussed signals are usually length matched but normally this isn't nearly as critical as differential signalling; and this is usually done with a maximum data rate in mind. Everything else is usually assigned to the auto-router. Hand tuning traces is expensive and time consuming and usually there are a limited number that can be optimised with high ball count FPGA footprints. Usually, the focus is on external memory like DDR. If you need IO pins that are length matched then choose a board that makes it clear how well this was done. If the board vendor doesn't mention length matching then it was unlikely to have been done. Most of Digilent's boards with "high-speed" "differential" PMODS mention length matching in the reference manual. Some vendors offer a trace routing report of lengths for certain connectors. If differential signal traces are routed as true differential pairs then using them as single-ended signals might be problematic from a cross-coupling standpoint, especially if you don't take this into account. The only 3.3V differential IOSTANDARD supported by Series7 devices is TMDS and this is best done when the termination is as close to the receiver as possible. All of this does not necessarily mean that you can't design around a board's shortcomings to achieve some level of performance using a logic that the board wasn't designed for. This is one reason why all (most???) Series7 devices offer input delay management and in some cases output delay management features. There are boards from a few vendors with length matched GPIO on connectors are usually designed for high-speed. 2.56x2.56 mm connectors aren't that. Not many board vendors are going to go to the expense of designing a high performance board that they intend to sell at a cheap price. Final comment. If you are going to connect an external board or device to your FPGA board connector then you must assume the digital logic designer role required to do so.
  13. 1 point
    Hi @cfatt7 Yes, you can use the FDwfAnalogOutConfigure(..., -1, ...) to start channels synchronized. You can also use the FDwfAnalogOutMasterSet to specify the master channel, then starting master channel will also start the slave channels. This is important in case you are using external triggering or cross-triggering with other instruments. Specifying a finite run length is useful to keep different frequencies phase aligned, using the minimum frequency or greatest common divisor. Like 1kHz might be generate as 0.9999999kHz and 2kHz as 2.000000001kHz, which could shift slowly over time. In this case use 1ms (1/1kHz) run time. FDwfAnalogOutRunSet(..., ..., 1.0/min_freq); FDwfAnalogOutRepeatSet(..., ..., 0); See the WF SDK/ samples/ py/ AnalogOut_Sync.py examples
  14. 1 point
    Glenn

    USB Power

    Upon further reflection, I bet my switched cables do not have all the USB lines coming through. RPi only needs power via it's microUSB input.
  15. 1 point
    zygot

    Using tera term for two pmods

    Well I think that this is better stated as saying that most serial terminal applications can only connect to one COM port at a time. It is possible to mave multiple UARTs in your FPGA design and connect to multiple serial terminal applications. I like Putty myself, but there are other options. Another possibility is to look around in the Digilent Project Vault and see at least 3 project with source code that might accomplish what you want to do. If you instantiate your own UART you can access any number of internal registers or memory.
  16. 1 point
    jpeyron

    GPS Pmod

    Hi @cepwin, I'm glad you we able to get to the bottom of the issue. Thank you for sharing what happened. cheers, Jon
  17. 1 point
    D@n

    Custom IP

    @PoojaN, You're not the first person who has asked this. If you just want to blink an LED, then I'd recommend a different approach that avoids all the pain with AXI in the first place. (You don't need AXI ...) If you want to start interacting with AXI cores, then you'll need to learn AXI. Sadly, this isn't as simple as it sounds. Xilinx picked the AXI bus to connect all their components with. This may have something to do with their ARM integration, since if I understand correctly AXI is an ARM creation AXI is not a simple bus to work with. Unlike Wishbone, it has five channels associated with it each of which can stall. These are the read address channel, the write address channel, the write data channel, the read response channel and the write response channel. One bus failure, and your device will lock up. In my experience, using an ARM+FPGA chip, lockups could only be fixed by cycling the power leaving you ever wondering what had caused the problem. Part of the problem is that the AXI standard has no way of recovering following a dropped response other than a total system reset. As I've implemented Wishbone, you can just adjust one wire (the cycle line--but that's another story) and start over. You can even use a timeout to clear the bus if a peripheral has not responded within an expected period of time. Not so with AXI. AXI is so difficult to work with that not even Xilinx could get it right. (See the links above) When I first discovered these bugs, I wondered that no one had found them before. For example, two writes in a row would lose a response and lock up the bus if ever there was the slightest amount of backpressure on the return channel. (Something Wishbone doesn't have to deal with, since there's no way to stall a Wishbone acknowledgement) It would seem as though very few individuals ever simulated their cores with backpressure (i.e. either BREADY or RREADY signals low), and so they never noticed these bugs. Similarly, some configurations of the interconnect might trigger the bugs while others wouldn't. Imagine adjusting the glue that holds your design together only to find your design starts failing. What would you blame? The interconnect, right? When in fact it was their demonstration core logic at fault that everyone was copying. I've now fielded several questions in the last several months alone on Xilinx's forums from users who've struggled with these bugs. If you do searches, you'll discover that folks have been struggling with these sorts of problems ever since Xilinx started using AXI. In one recent post, a software engineer posted that his FPGA engineer had left, leaving them with a "working" design. He then adjusted the software within the design and the whole design now froze any time he tried to write to their special IP core twice in succession. I'm hoping Xilinx will fix these bugs (soon). I haven't checked their latest release since reporting them, but I do expect them to fix the bugs in the near future. It's not just Xilinx either. I'm currently verifying the (ASIC) soft core of a major (unnamed) vendor. Much to my surprise, despite a team of highly paid professional engineers working to produce this amazingly complex core , and despite the fact that they created a simplified subset of the AXI interface standard to work with ... they still didn't get the AXI interface right. Realizing how difficult this was, I tried to simplify the task by creating a couple of cores. One showing how to build a bug-free AXI-lite slave (link above), another showing how to build a bug-free AXI slave (link above again). I also shared an AXI bridge implementation that, if you place your core downstream of it, you'd be guaranteed to meet the AXI protocol--even if it slowed you down a touch. I also shared the code for verifying that an AXI-lite component works--you are free to try it out yourself to know if your core still works after changing it. If you like using Wishbone, I've posted an AXI-lite to Wishbone bridge, or even a Wishbone to AXI bridge in case you want to access your DRAM memory. I also think you'll find that all of these cores, save perhaps the bus fault isolator core, will have better performance than Xilinx's logic ever had. Whether or not you use these options (or give up on AXI as I've tried to do) ... well, that's up to you. Forget what the sales brochures tell you, we aren't playing with legos here. There's more required to hook things together then just plugging them into each other--especially if you want something that works reliably when you are done. Just want something simple? Learn Verilog or VHDL. At least then you'll be the one responsible for your own bugs. Dan
  18. 1 point
    You can find newer version 1.0.0.76 in the description of the video: https://www.youtube.com/watch?v=4d3hc-9zBaI
  19. 1 point
    yes, for an application with basic requirements, like receiver gain control this will probably work just fine (it's equivalent to an analog envelope detector). Now it needs a fairly high bandwidth margin between the modulation and the carrier, and that may make it problematic in more sophisticated DSP applications (say "polar" signal processing when I try to reconstruct the signal from the envelope) where the tolerable noise level is orders of magnitude lower.
  20. 1 point
    Hi @Ahmed Alfadhel I had the C code handy because I have been working on an atan2(y,x) implementation for FPGAs, and had been testing ideas. I left it in C because I don't really know your requirements, but I wanted to give you a working algorithm, complete with proof that it does work, and so you can tinker with it, see how it works, and make use of it. Oh, and I must admit that it was also because I am also lazy 😀 But seriously: - I don't know if you use VHDL or Verilog, or some HLS tool - I don't know if your inputs are 4 bits or 40 bits long, - I don''t know if you need the answer to be within 10% or 0.0001% - I don't know if it has to run at 40Mhz or 400Mhz - I don't know if you have 1000s of cycles to process each sample, or just one. - I don't even know if you need the algorithm at all! But it has been written to be trivially converted to any HDL as it only uses bit shifts and addition/subtraction. But maybe more importantly you can then use it during any subsequent debugging to verify that you correctly implemented it. For an example of how trivial it is to convert to HDL: if(x > 0) { x += -ty/8; y += tx/8;} else { x += ty/8; y += -tx/8;} could be implemented as IF x(x'high) = '0' THEN x := x - resize(y(y'high downto 3), y'length); y := y + resize(x(x'high downto 3), x'length); ELSE x := x + resize(y(y'high downto 3), y'length); y := y - resize(x(x'high downto 3), x'length); END IF My suggestion is that should you choose to use it, compile the C program, making the main() function a sort of test bench, and then work out exactly what you need to implement in your HDL., You will then spend very little time writing, debugging and improving the HDL because you will have a very clear idea of what you are implementing.
  21. 1 point
    Hi @pikeaero, Welcome to the Digilent forums! best regards, Jon
  22. 1 point
    attila

    Scope custom math channel limitations?

    Hi @P. Fiery You could use the View/Logging/Script to create an up-sampled reference channel like this: var rg = [] var v2 = 0 Scope.Channel1.data.forEach(function(v1){ rg.push((v1+v2)/2) rg.push(v1) v2 = v1 }) // upsampling by 2 doubles the sample rate Scope.Ref1.setData(rg, 2*Scope.Time.Rate.value)
  23. 1 point
    Nothing to worry about if only one is up at a time. It would mean that the frequencies of adjacent oscillators affect each other if they are running at the same time ("injection pulling", to the point that they agree on a common frequency ("locking"). Consider the oscillator as an amplifier with a feedback loop. The feedback path plus phase shift lead to a fairly narrow frequency response around the oscillation frequency or harmonically related frequencies). Weird things can happen with the gain - while it is unity in average steady-state operation, the circuit can get highly sensitive to external interference that is (near)-correlated with the oscillator's own signal. Wikipedia: Perhaps the first to document these effects was Christiaan Huygens, the inventor of the pendulum clock, who was surprised to note that two pendulum clocks which normally would keep slightly different time nonetheless became perfectly synchronized when hung from a common beam
  24. 1 point
    jpeyron

    Pmod da3 reconstruction filter

    Hi @lwew96, We have not used a reconstruction filter. I did find a paper that discusses a reconstruction filter with the AD5541 here. Hopefully one of the more experienced community members will have some input for you as well. best regards, Jon
  25. 1 point
    Hi @kuc3, Welcome to the Digilent Forums! I have moved your thread to a sub-section where more experienced embedded linux engineers look. best regards, Jon
  26. 1 point
    Hi, For sw part I use Xilinx DMA driver (interface to VDMA IP core) and modified ADI AXI HDMI DRM driver for exposing frame buffer device to GUI sw (e.g. Qt). You can see driver bindings in above attached zyboz7-20.devicetree-1.zip (pl.dtsi). All video memory transfers to FPGA are managed by this two drivers.
  27. 1 point
    Yep, seen that they were back online. Thanks, Jon
  28. 1 point
    jomoengineer

    Howdy from NorCal

    Thanks Jon. And thanks for the links. Cheers, Jon
  29. 1 point
    jpeyron

    hdmi ip clocking error

    Hi @askhunter, I did a little more searching and found a forum thread here where the customer is having a similar issue. A community member also posted a pass through zynq project that should be useful for your project. best regards, Jon
  30. 1 point
    For the Protocol / SPI-I2C /Spy mode you should specify the approximate (or highest) protocol frequency which will be used to filter transient glitches, like ringing on clock signal transition. The Errors you get indicate the signals are not correctly captured. - make sure to have proper grounding between the devices/circuits - use twisted wires (signal/ground) to reduce EMI - use logic analyzer and/or scope to verify the captured data / voltage levels at higher sample rate at least 10x the protocol frequency Like here in the Logic Analyzer you can see a case when the samples are noisy:
  31. 1 point
    @longboard, Yeah, that's really confusing isn't it? At issue is the fact that many of these chips are specified in Mega BITS not BYTES. So the 1Gib is mean to refer to a one gigabit memory, which is also a 128 megabyte memory. That's what the parentheses are trying to tell you. Where this becomes a real problem is that I've always learned that a MiB is a reference to a million bytes, 10^6 bytes, rather than a mega byte, or 2^20 bytes. The proper acronyms, IMHO, should be Gb, GB, Mb, and MB rather than GiB or MiB which are entirely misleading. As for the memory, listed as 16 Meg x 8 x 8, that's a reference to 8-banks of 16-mega words or memory, where each word is 8-bits wide. In other words, the memory has 16MB*8 or 128MB of storage. You could alternatively say it had 1Gb of memory, which would be the same thing, but this is often confused with 1GB of memory--hence the desire for the parentheses again. Dan
  32. 1 point
    HI xc6lx45: Well, to my surprise, when I got home and loaded the .BIT file onto the board...it works perfectly. [1:0]sw is changing the frequency the the led is blinking at properly. So this tells me that I don't quite have my testbed code done properly. I tried to attach it into this text but it kept getting reformatted so I've simply attached the actual file. If somebody could look at it and tell me what (if anything) I've done wrong I'd greatly appreciate it. THANKS! NOTE: In the actual module code, above, I had changed the CASE choices to the 0, 1st, 2nd and 3rd flip-flops in order to better see the led changing value on the wave panel. However I've changed the code back to the actual flip-flops I wanted; the 26th, 25th, 24th and 23rd flip-flops. As I said...the board is working perfectly now and the switch setting are appropriately changing the led blinking frequency. It HAS to be something wrong with the TestBench code...or me not using the simulator properly. THANKS MUCH! clock_divider.tb
  33. 1 point
    Hi @Jaraqui Peixe, Unfortunately, Digilent does not have the ability to obtain these licenses for you with regards to Xilinx negotiations. I do not doubt that the Spartan 3E Starter Boards you have are as good as new and work as such, but the reality is that last variant of ISE 14.7 that could support the FPGA chips on the Basys 2 and the Spartan 3E (both over 10 years old), was released by Xilinx back in 2013, so active support on these boards is limited as the required software will not install on newer OS's (at least the Windows variants anyway). As @xc6lx45, it is possible to make it work though. What I would probably recommend is looking into the newer 7 series boards, such as the Basys 3 (the most similar to the Basys 2) or if you would want access to more memory than is provided in BRAM, both the Arty A7 and the Nexys A7 have on-board DDR memory. All of these boards work with Microblaze and are supported by the free Vivado WebPACK from Xilinx (which is license-free if that is a factor for you and includes Microblaze). Naturally, there is no guarantee that the Vivado software that supports these Artix 7 FPGA chips will become end-of-life'd, but I can at least say from Digilent's end that I have not heard of this happening in the near future. Thanks, JColvin
  34. 1 point
    jpeyron

    Nexys 2 - transistor part number

    Hi @CVu, Glad to hear that replacing the transistor fix the issue. Thank you for sharing what you did. best regards, Jon
  35. 1 point
    jpeyron

    Nexys 2 - transistor part number

    Hi @CVu, Welcome to the Digilent Forums! Q1 information is below: NTS2101P Single P-Channel Power Mosfet 1.4A, 8VSOT-323 (SC-70) best regards, Jon
  36. 1 point
    attila

    AD2 waveForms script

    Hi @omur // start capture and wait to be finished Logic1.single() Logic1.wait() // on AD by default the Logic Analyzer and Wavegen have the same 4064 buffer var datam = Logic1.Channels.Bus.data var data_norm = [] datam.forEach(function(v){data_norm.push(v/4095)}) plot1.Y1.data = data_norm Wavegen1.Channel1.Mode.text = "Custom" Wavegen1.Custom.set("mycustom", data_norm) Wavegen1.Channel1.Custom.Type.text = "mycustom" Wavegen1.run()
  37. 1 point
    Hi @kmesne, We responded to your other question here with some detail, but I will try to elaborate a little bit more here. The Pmod COLOR is not intended to detect colors from any sort of distance, so you would need it next to the red/green light indicator and then have it transmit data to the main controller for the car as opposed to be mounted on the car (unless the red/green indicator was on the car itself). I believe the Pmod COLOR could detect the green in a green cube, but it would need to be fairly well lit up due to the limitations of the sensor itself. As a bit of perspective, this will be a large and non-trivial state machine (especially for first semester project) with a lot of conditions to be covered; is light red or green to control the enable bit on 2+ H-bridge drivers running the motor, which needs to be checked frequently in order to obey traffic laws, as well as the enable bit being toggled as appropriate when changing input directions if the vehicle can go in reverse to avoid burning out the h-bridges, pwm control over the enable pin to allow the vehicle to turn; all done over (presumably) 3 remote systems communicating with each other; the controller with the direction buttons, the color sensor detecting the light change, and the RC vehicle itself. Which system/input will have priority in the state machine and how often will you need to check each input to provide a "smooth driving experience" will all be things that you need to consider. Some good resources for VHDL basics can be found at asic-world.com and fpga4fun.com, as well as this page that discusses state machine construction in VHDL. Thanks, JColvin
  38. 1 point
    You might have a look at Trenz Electronics "Zynqberry". I think they managed to get one of the cameras to work (not sure). What I do remember is that the board has some custom resistor circuitry to additional pins for the required low-speed signaling.
  39. 1 point
    are you maybe using a low-speed analog output with 200 ohms series resistor? Check the schematic of the board for a direct output.
  40. 1 point
    Well that's a pretty horrible looking 5 MHz signal coming directly out of an MMCM. It does remind me of the characteristic response of a particular passive component to a pulse, from decades ago when I took my intro electronics course. What do you think? Remind you of anything? I didn't mention the idea of scope probe compensation. It sure doesn't look like something that even a cheapo compensated probe would present for a low frequency signal out of a functioning FPGA pin into a high impedance load. Past that there are a number of usual suspects... but something is fundamentally wrong with your test setup.
  41. 1 point
    kotra sharmila

    sdsoc_opencv error

    Hi , Thank you very much for this platform its showing video i/o demo and build perfectly i will try with my own project if i got any doubts i will ask you. Regards, K Sharmila
  42. 1 point
    Hi @Amin, I know our content team is planning on updating our Petalinux projects. We currently do not have an ETA for this. Here is the Petalinux Support for Digilent Boards table that shows what Petalinux projects we have for our development boards and has a link to them as well. To use our most recent Petalinux release for the Zybo-Z7-20 I would suggest to download Vivado/SDK and Petalinux 2017.4. I would also suggest reading the Petalinux projects detailed readme as well. thank you, Jon
  43. 1 point
    xc6lx45

    FFT / iFFT / RS - Basys3

    OK that starts to make more sense. So one channel is reference signal e.g. transmitted signal, one channel the received reflection. Capture both, FFT, multiply (don't forget the conjugate), iFFT. On the bright side, in this specific case you can solve the circularity issues mentioned above with sufficient zero padding on the transmit signal (rule of thumb: Add enough zeros until all reflections have died down to negligible level). This may be easier said than done with a hardware FFT, though... Resolution is limited to the sample rate. If you want to do better, you can interpolate by stealing lines 315..345 here . Needless to say, this calculation needs to be done on a microcontroller or the like. In double precision it's usually accurate to 1 % of a sample. For a reference algorithm, have a look here (this is more complex and somewhat heuristic but has proven itself over the years). With noise-free data this can be accurate to about one nanosample.
  44. 1 point
    attila

    external p/s for analog discovery 2

    Szia @GaborG Unfortunately Analog Discovery and Digital Discovery are not working with RaspberryPI.
  45. 1 point
    Hi @jli853, I reached out to one of our design engineers about this forum thread. They responded that "Unless you do a non-blocking (overlapped) transfer the time it takes to execute the function will include not only the time to transfer the data over USB but also to shift it onto the JTAG scan chain. When the function returns all data has been transferred to the target JTAG device. How long that takes is going to very with the TCK frequency, as well as the PC side hardware and operating system. I don’t have any measured data to provide." thank you, Jon
  46. 1 point
    They are to get a negative supply out of the positive digital output from the uC. Since the output of the uC is between 0 ... 3.3 V max. VREF1V5 is the node determining at which point the IC10A will switch from positive output to negative and vice versa. The opamp will always attempt to keep the difference between inverting and non-inverting inputs zero. VREF3V3 is a pullup of the inverting input, if the inverting input is pulled below 1.5V, the IC10A output will become positive in order to bring the inverting input back to 1.5V. On the other hand, when the inverting input is above 1.5V, the output of the IC10A will become negative to bring the inverting input back to 1.5V. I guess VREF3V0 could have been a higher voltage as well. But VREF1V5 should be as close to the center of the uC supply as possible in order to achieve symmetric output and the best resolution thereof. I'm also guessing they were not willing to rely on a stable supply voltage from the linear 3.3V regulator and probably already required a precision 3V reference for other purposes.
  47. 1 point
    jpeyron

    Zedboard WiFi usage

    Hi @harika, Glad to hear you were able to get the bitstream to generate. cheers, Jon
  48. 1 point
    shahbaz

    How to read from SD card on ZYBO

    hi @jpeyron, I followed the guide at GitHub under Readme in PMODSD. can you please guide me step wise on how to start from block design and than going to SDK and running the demo. I have added the pmodsd and zynq PS IPs, after auto connection and running the generate bitstream I get following error. I need your guidance at this
  49. 1 point
    OK thanks. Yes, updating that tutorial would save a lot of time and confusion. I later noticed that Xilinx's page for 2017.2 has a bit more description relating to free WebPACK than the page for 2017.3, though it's still not clear how to invoke the free aspect. Further confusion is added by the Xilinx page you arrive at from Vivado's License Manager, as that page omits the Activation-based licenses, and the licenses it does show include a Free one for pre-2015, as though you can't license 2016 and later for free. Evidently that doesn't mean you can't use 2016 and later, it means that no license is required, and you don't need to be using the License Manager at all!
  50. 1 point
    hamster

    MMCM dynamic clocking

    I feel a bit bad about posting a minor novel here, but here is an example of going from "5 cycles on, 5 off" (i.e. divide by 10) to "10 on, 10 off" (device by 20). The VCO is initially to 800 MHz with CLK0 being VCO divide by 8.... so after config you get 100MHz. Push the button and you get 800/20 = 40MHz, release the button and you get 80MHz. It is all really hairy in practice! EDIT: Through experimentation I just found that you don't need to reset the MMCM if you are not changing the VCO frequency. So the 'rst' signal in the code below isn't needed (and LOCKED will stay asserted). -------------------------------------------------------------------------------------------------------- -- Playing with the MMCM DRP ports. -- see https://www.xilinx.com/support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf -- for the Dynamic Reconviguration Port addresses -------------------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity mmcm_reset is Port ( clk_100 : in STD_LOGIC; btn_raw : in STD_LOGIC; led : out STD_LOGIC_VECTOR (15 downto 0)); end mmcm_reset; architecture Behavioral of mmcm_reset is signal btn_meta : std_logic := '0'; signal btn : std_logic := '0'; signal speed_select : std_logic := '0'; signal counter : unsigned(26 downto 0) := (others => '0'); signal debounce : unsigned(15 downto 0) := (others => '0'); signal clk_switched : std_logic := '0'; signal clk_fb : std_logic := '0'; type t_state is (state_idle_fast, state_go_slow_1, state_go_slow_2, state_go_slow_3, state_idle_slow, state_go_fast_1, state_go_fast_2, state_go_fast_3); signal state : t_state := state_idle_fast; ----------------------------------------------------------------------------- --- This is the CLKOUT0 ClkReg1 address - the only register to be played with ----------------------------------------------------------------------------- signal daddr : std_logic_vector(6 downto 0) := "0001000"; signal do : std_logic_vector(15 downto 0) := (others => '0'); signal drdy : std_logic := '0'; signal den : std_logic := '0'; signal di : std_logic_vector(15 downto 0) := (others => '0'); signal dwe : std_logic := '0'; signal rst : std_logic := '0'; begin MMCME2_ADV_inst : MMCME2_ADV generic map ( BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW) CLKFBOUT_MULT_F => 8.0, -- Multiply value for all CLKOUT (2.000-64.000). CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000). -- CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). CLKIN1_PERIOD => 10.0, CLKIN2_PERIOD => 0.0, -- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128) CLKOUT1_DIVIDE => 1, CLKOUT2_DIVIDE => 1, CLKOUT3_DIVIDE => 1, CLKOUT4_DIVIDE => 1, CLKOUT5_DIVIDE => 1, CLKOUT6_DIVIDE => 1, CLKOUT0_DIVIDE_F => 8.0, -- Divide amount for CLKOUT0 (1.000-128.000). -- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.01-0.99). CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT2_DUTY_CYCLE => 0.5, CLKOUT3_DUTY_CYCLE => 0.5, CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5, CLKOUT6_DUTY_CYCLE => 0.5, -- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000). CLKOUT0_PHASE => 0.0, CLKOUT1_PHASE => 0.0, CLKOUT2_PHASE => 0.0, CLKOUT3_PHASE => 0.0, CLKOUT4_PHASE => 0.0, CLKOUT5_PHASE => 0.0, CLKOUT6_PHASE => 0.0, CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE) COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL DIVCLK_DIVIDE => 1, -- Master division value (1-106) -- REF_JITTER: Reference input jitter in UI (0.000-0.999). REF_JITTER1 => 0.0, REF_JITTER2 => 0.0, STARTUP_WAIT => FALSE, -- Delays DONE until MMCM is locked (FALSE, TRUE) -- Spread Spectrum: Spread Spectrum Attributes SS_EN => "FALSE", -- Enables spread spectrum (FALSE, TRUE) SS_MODE => "CENTER_HIGH", -- CENTER_HIGH, CENTER_LOW, DOWN_HIGH, DOWN_LOW SS_MOD_PERIOD => 10000, -- Spread spectrum modulation period (ns) (VALUES) -- USE_FINE_PS: Fine phase shift enable (TRUE/FALSE) CLKFBOUT_USE_FINE_PS => FALSE, CLKOUT0_USE_FINE_PS => FALSE, CLKOUT1_USE_FINE_PS => FALSE, CLKOUT2_USE_FINE_PS => FALSE, CLKOUT3_USE_FINE_PS => FALSE, CLKOUT4_USE_FINE_PS => FALSE, CLKOUT5_USE_FINE_PS => FALSE, CLKOUT6_USE_FINE_PS => FALSE ) port map ( -- Clock Outputs: 1-bit (each) output: User configurable clock outputs CLKOUT0 => clk_switched, CLKOUT0B => open, CLKOUT1 => open, CLKOUT1B => open, CLKOUT2 => open, CLKOUT2B => open, CLKOUT3 => open, CLKOUT3B => open, CLKOUT4 => open, CLKOUT5 => open, CLKOUT6 => open, -- Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs PSDONE => open, -- Feedback Clocks: 1-bit (each) output: Clock feedback ports CLKFBOUT => clk_fb, CLKFBOUTB => open, -- Status Ports: 1-bit (each) output: MMCM status ports CLKFBSTOPPED => open, CLKINSTOPPED => open, LOCKED => open, -- Clock Inputs: 1-bit (each) input: Clock inputs CLKIN1 => clk_100, CLKIN2 => '0', -- Control Ports: 1-bit (each) input: MMCM control ports CLKINSEL => '1', PWRDWN => '0', -- 1-bit input: Power-down RST => rst, -- 1-bit input: Reset -- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports DCLK => clk_100, -- 1-bit input: DRP clock DO => DO, -- 16-bit output: DRP data DRDY => DRDY, -- 1-bit output: DRP ready -- DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports DADDR => DADDR, -- 7-bit input: DRP address DEN => DEN, -- 1-bit input: DRP enable DI => DI, -- 16-bit input: DRP data DWE => DWE, -- 1-bit input: DRP write enable -- Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs PSCLK => '0', PSEN => '0', PSINCDEC => '0', -- Feedback Clocks: 1-bit (each) input: Clock feedback ports CLKFBIN => clk_fb ); speed_change_fsm: process(clk_100) begin if rising_edge(clk_100) then di <= (others => '0'); dwe <= '0'; den <= '0'; case state is when state_idle_fast => if speed_select = '1'then state <= state_go_slow_1; -- High 10 Low 10 di <= "0001" & "001010" & "001010"; dwe <= '1'; den <= '1'; end if; when state_go_slow_1 => if drdy = '1' then state <= state_go_slow_2; end if; when state_go_slow_2 => rst <= '1'; state <= state_go_slow_3; when state_go_slow_3 => rst <= '0'; state <= state_idle_slow; when state_idle_slow => di <= (others => '0'); if speed_select = '0' and drdy = '0' then state <= state_go_fast_1; -- High 5 Low 5 di <= "0001" & "000101" & "000101"; dwe <= '1'; den <= '1'; end if; when state_go_fast_1 => if drdy = '1' then state <= state_go_fast_2; end if; when state_go_fast_2 => rst <= '1'; state <= state_go_fast_3; when state_go_fast_3 => rst <= '0'; state <= state_idle_fast; end case; end if; end process; dbounce_proc: process(clk_100) begin if rising_edge(clk_100) then if speed_select = btn then debounce <= (others => '0'); elsif debounce(debounce'high) = '1' then speed_select <= not speed_select; else debounce <= debounce + 1; end if; -- Syncronise the button btn <= btn_meta; btn_meta <= btn_raw; end if; end process; show_speed_proc: process(clk_switched) begin if rising_edge(clk_switched) then counter <= counter + 1; led(7 downto 0) <= std_logic_vector(counter(counter'high downto counter'high-7)); end if; end process; led(15) <= speed_select; end Behavioral;