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  1. 4 points
    attila

    WaveForms beta download

    3.13.22 Windows: digilent.waveforms_beta_v3.13.22_64bit.exe digilent.waveforms_beta_v3.13.22_32bit.exe MacOS: digilent.waveforms_beta_v3.13.22.dmg Linux 64bit: digilent.waveforms_beta_3.13.22_amd64.deb digilent.waveforms_beta_3.13.22.x86_64.rpm Linux 32bit: digilent.waveforms_beta_3.13.22_i386.deb digilent.waveforms_beta_3.13.22.i686.rpm Linux ARM 64bit: digilent.waveforms_beta_3.13.22_arm64.deb digilent.waveforms_beta_3.13.22.aarch64.rpm Linux ARM 32bit: digilent.waveforms_beta_3.13.22_armhf.deb digilent.waveforms_beta_3.13.22.armhf.rpm Fixing known bugs 3.13.21 digilent.waveforms_beta_v3.13.21_64bit.exe Added: - Logic Analyzer Export All Events - AD2 7th device configuration Fixed: - Script plot with high offset/range ratio 3.13.20 Windows: digilent.waveforms_beta_v3.13.20-2_64bit.exe digilent.waveforms_beta_v3.13.20-2_32bit.exe MacOS: digilent.waveforms_beta_v3.13.20.dmg Linux 64bit: digilent.waveforms_beta_3.13.20_amd64.deb digilent.waveforms_beta_3.13.20.x86_64.rpm Linux ARM 64bit: digilent.waveforms_beta_3.13.20_arm64.deb digilent.waveforms_beta_3.13.20.aarch64.rpm Linux ARM 32bit: digilent.waveforms_beta_3.13.20_armhf.deb digilent.waveforms_beta_3.13.20.armhf.rpm Patch for RaspberryPi4B ERC 2 with Digital Discovery and Analog Discovery 1/2 with 2nd device configuration. Replace frequency/bandwidth limits option with warning. Fixing cleanup process, random WF app crash. 3.13.19 Windows: digilent.waveforms_beta_v3.13.19_64bit.exe digilent.waveforms_beta_v3.13.19_32bit.exe MacOS: digilent.waveforms_beta_v3.13.19.dmg Linux 64bit: digilent.waveforms_beta_3.13.19_amd64.deb digilent.waveforms_beta_3.13.19.x86_64.rpm Linux ARM 64bit: digilent.waveforms_beta_3.13.19_arm64.deb digilent.waveforms_beta_3.13.19.aarch64.rpm Linux ARM 32bit: digilent.waveforms_beta_3.13.19_armhf.deb digilent.waveforms_beta_3.13.19.armhf.rpm Fixing ERC 0x2 Linux and Raspberry Pi 4 B with AD, AD2, DD 3.13.18 digilent.waveforms_beta_v3.13.18_64bit.exe digilent.waveforms_beta_v3.13.18.dmg digilent.waveforms_beta_3.13.18_amd64.deb digilent.waveforms_beta_3.13.18.x86_64.rpm - Logic Analyzer - I2C interpreter remove restart, stop timing requirement - name option for Add Signal dialog - fixing analog curve in idle state and signed representation - fixing first value alignment - Select option for Event view - Cursors view: - name field - positioning plot on cursor row selection - Workspace: - multiple file selection for Extract - Compare tool based on capture device serial number 3.13.17 digilent.waveforms_beta_v3.13.17_64bit.exe Fixing know bugs 3.13.16 digilent.waveforms_beta_v3.13.16_64bit.exe Changed: - Network Analyzer rate improvement, Custom offset sweep - Logic Analyzer allowing large single captures Fixing know bugs 3.13.14 digilent.waveforms_beta_v3.13.14_64bit.exe Changed: - Saving workspace/project to temporary file first - Impedance Analyzer rate improvement Fixing known bugs 3.13.13 digilent.waveforms_beta_v3.13.13_64bit.exe Adding: - Logic Analyzer Import Binary, Script Logic.AddTab Fixing known bugs 3.13.12 digilent.waveforms_beta_v3.13.12_64bit.exe digilent.waveforms_beta_v3.13.12.dmg digilent.waveforms_beta_3.13.12_amd64.deb digilent.waveforms_beta_3.13.12.x86_64.rpm digilent.waveforms_beta_3.13.12_armhf.deb Fixing known bugs - Digital Discovery Logic Analyzer - application arguments 3.13.11 digilent.waveforms_beta_v3.13.11_64bit.exe Added: - FDwfDigitalSpiIdleSet Fixing known bugs 3.13.10 digilent.waveforms_beta_v3.13.10_64bit.exe digilent.waveforms_beta_v3.13.10.dmg digilent.waveforms_beta_3.13.10_amd64.deb digilent.waveforms_beta_3.13.10.x86_64.rpm Added: - Logic Analyzer: - Manchester interpreter - Trigger on CAN data Fixing known bugs 3.13.8 digilent.waveforms_beta_v3.13.8_64bit.exe digilent.waveforms_beta_3.13.8_amd64.deb digilent.waveforms_beta_3.13.8.x86_64.rpm Fixed: - Digital Discovery jitter 3.13.6 digilent.waveforms_beta_v3.13.6_64bit.exe digilent.waveforms_beta_v3.13.6.dmg digilent.waveforms_beta_3.13.6_amd64.deb digilent.waveforms_beta_3.13.6.x86_64.rpm ARM64: digilent.waveforms_beta_3.13.6_arm64.deb digilent.adept.runtime_2.20.0-arm64.deb digilent.adept.utilities_2.3.0-arm64.deb Fixing known bugs 3.13.1 digilent.waveforms_beta_v3.13.1_64bit.exe digilent.waveforms_beta_v3.13.1.dmg Added: - Play mode for Digital Discovery in Logic Analyzer - Protocol/UART Save Raw data Fixed: - Pattern Generator preview 3.11.34 digilent.waveforms_beta_v3.11.34_64bit.exe digilent.waveforms_beta_v3.11.34.dmg digilent.waveforms_beta_3.11.34_amd64.deb digilent.waveforms_beta_3.11.34.x86_64.rpm Fixing known bugs. 3.11.33 digilent.waveforms_beta_v3.11.33_64bit.exe digilent.waveforms_beta_v3.11.33.dmg digilent.waveforms_beta_3.11.33_amd64.deb digilent.waveforms_beta_3.11.33.x86_64.rpm Added: - Protocol: - SPI/I2C frequency filter option - SpiFlash (P5Q, M25P16) interpreter option for Spy - Network: - Radian unit for phase plot Fixing known bugs. 3.11.32 digilent.waveforms_beta_v3.11.32_64bit.exe digilent.waveforms_beta_3.11.32_amd64.deb digilent.waveforms_beta_3.11.32.x86_64.rpm Changed: - Protocol: CAN RX re-synchronization for rate tolerance, +/-10% Fixing known bugs. 3.11.31 digilent.waveforms_beta_v3.11.31_64bit.exe digilent.waveforms_beta_v3.11.31.dmg digilent.waveforms_beta_3.11.31_amd64.deb digilent.waveforms_beta_3.11.31.x86_64.rpm Added: - Script: access to windows, like Scope.window.size = [600, 400] Changed: - Logic: - CAN interpreter re-synchronization to increase rate tolerance - CAN trigger ignore substitute remote request bit - Protocol: using Digital Discovery system frequency adjustment Fixes: - Patterns: preview 3.11.30 digilent.waveforms_beta_v3.11.30_64bit.exe digilent.waveforms_beta_v3.11.30.dmg digilent.waveforms_beta_3.11.30_amd64.deb digilent.waveforms_beta_3.11.30.x86_64.rpm Fixing known bugs 3.11.29 digilent.waveforms_beta_v3.11.29_64bit.exe digilent.waveforms_beta_v3.11.29_32bit.exe digilent.waveforms_beta_v3.11.29.dmg digilent.waveforms_beta_3.11.29_amd64.deb digilent.waveforms_beta_3.11.29.x86_64.rpm Fixing known bugs 3.11.28 digilent.waveforms_beta_v3.11.28_64bit.exe digilent.waveforms_beta_3.11.28_amd64.deb digilent.waveforms_beta_3.11.28.x86_64.rpm Added: - Script: - find and replace - clear output button and function - Ctrl+Tab - Save All, Open multiple files 3.11.27 digilent.waveforms_beta_v3.11.27_64bit.exe digilent.waveforms_beta_v3.11.27.dmg digilent.waveforms_beta_3.11.27_amd64.deb digilent.waveforms_beta_3.11.27.x86_64.rpm Fixes and Help update 3.11.26 digilent.waveforms_beta_v3.11.26_64bit.exe digilent.waveforms_beta_v3.11.26.dmg digilent.waveforms_beta_3.11.26_amd64.deb digilent.waveforms_beta_3.11.26.x86_64.rpm Added: - Script: - multiple files for individual scripts or optional include Fixed: - Logic Analyzer: - keep order in Bus signals 3.11.25 digilent.waveforms_beta_v3.11.25_64bit.exe digilent.waveforms_beta_3.11.25_amd64.deb digilent.waveforms_beta_3.11.25.x86_64.rpm Fixed: - Protocol I2C Read with Script 3.11.24 digilent.waveforms_beta_v3.11.24_64bit.exe digilent.waveforms_beta_v3.11.24.dmg digilent.waveforms_beta_3.11.24_amd64.deb digilent.waveforms_beta_3.11.24.x86_64.rpm Added: - Wavegen: - period setting next to frequency Changed: - Protocol: - AVR programmer speed, functions, script access Fixed: - Network Analyzer: - phase averaging 3.11.22 digilent.waveforms_beta_v3.11.22_64bit.exe digilent.waveforms_beta_v3.11.22.dmg (not certified) digilent.waveforms_beta_3.11.22_amd64.deb digilent.waveforms_beta_3.11.22.x86_64.rpm Added: - Logic Analyzer: - SPI interpreter with MOSI/MOSI - HDMI CEC interpreter, trigger on: start, source, destination - Portocol: - AVR programmed: Flash, EEPROM, Fuse, Lock, Calibration - Scope/Logic remembers as default option: Show Attenuation, Acquire Noise, Multiple Scale - Pattern Generator negative delay option Changed: - Pattern Generator: - clock duty round up 3.11.21 digilent.waveforms_beta_v3.11.21_64bit.exe Fixed: - Patterns preview 3.11.20 digilent.waveforms_beta_v3.11.20_64bit.exe Added: - shared workspace list when running multiple applications Fixed: - Digital Discovery trigger position - Patterns preview for pulse - other minor fixes 3.11.19 digilent.waveforms_beta_v3.11.19_64bit.exe Added: - Patterns Delay option for signal/bus Fixed: - Digital Discovery system frequency adjustment 3.11.18 digilent.waveforms_beta_v3.11.18_64bit.exe Fixed: - Supplies for EExplorer and Analog Discovery 1 - Logic Analyzer Inputs for Digital Discovery 3.11.17 digilent.waveforms_beta_v3.11.17_64bit.exe Added: - Spectrum Units: V/vHz, dBm, dBm/vHz, dBm/vMHz - Digital Discovery: - system frequency (Pattern Generator and Logic Analyzer) fine adjustment from Supplies window 3.11.16 digilent.waveforms_beta_v3.11.16_64bit.exe Added: - Spectrum: - Units: dBm, dBmHz, dBmMHz Fixed: - Wavegen: Sync option 3.11.15 digilent.waveforms_beta_v3.11.15_64bit.exe Added: - SDK: - VB/C# ushort and uinteger modes for FDwfDigitalInStatusData/2/Noise/2 - replacing BOOL and BYTE types - manual update - Logic Analyzer: - 100 MHz limit option for Digital Discovery Fixed: - Spectrum: Persistence view axis labels for log scales - SDK: VB/C# wrappers FDwfAnalogInStatusData16 3.11.14 digilent.waveforms_beta_v3.11.14_64bit.exe digilent.waveforms_beta_3.11.14_amd64.deb digilent.waveforms_beta_3.11.14.x86_64.rpm Added: - Script access to Logic Analyzer measurements - System Monitor in Supplies window for AD1, AD2, DD Fixed: - SDK DwfParamOnClose continue running after re-open 3.11.13 digilent.waveforms_beta_v3.11.13_64bit.exe Added: - Network/Impedance Analyzer usage with constant frequency, start=stop - quick measure, cursors, horizontal axis as percentage 3.11.12 digilent.waveforms_beta_v3.11.12_64bit.exe digilent.waveforms_beta_3.11.12_amd64.deb digilent.waveforms_beta_3.11.12.x86_64.rpm Added: - Import data from file option for Spectrum, Network and Impedance Analyzer - trace toolbar width setting for Impedance Analyzer - AnalogOutIn_PlayRecord.py example playing mono and recording to stereo WAV file - FDwfAnalogImpedanceStatusInput phase normalization Fixed: - Analog Discovery 2 USB power monitor false 1A readings - wrong default reference for dBV in Spectrum Analyzer 3.11.11 digilent.waveforms_beta_v3.11.11_64bit.exe Added: - Logic Analyzer Bus interpreter: - either Clock edge option - sampling delay relative to edge - Events view lists sample for each edge when Clock signal is selected 3.11.10 digilent.waveforms_beta_v3.11.10_64bit.exe Added: - Scope scale for XYZ and Spectrogram 3D views - Export EPS image format - support for multiple transfers in Protocol/I2C/Sensor loop function 3.11.9 digilent.waveforms_beta_v3.11.9_64bit.exe Added: - Scope Spectrogram 3D surface view, for 64bit Windows 3.11.8 digilent.waveforms_beta_v3.11.8_64bit.exe digilent.waveforms_beta_v3.11.8.dmg digilent.waveforms_beta_3.11.8_amd64.deb digilent.waveforms_beta_3.11.8.x86_64.rpm Added: - horizontal cursors for Scope/FFT, Spectrum and Impedance Analyzer - cursor delta as decade for logarithmic scales - Scope: - simple Math channel operations: RMS, ATan - LockIn amplifier as Math channel - XYZ 3D graph, for 64bit Windows Fixed: - Scope/Audio/Tempo option 3.11.7 digilent.waveforms_beta_v3.11.7_64bit.exe digilent.waveforms_beta_v3.11.7.dmg digilent.waveforms_beta_3.11.7_amd64.deb digilent.waveforms_beta_3.11.7.x86_64.rpm minor fixes and improvements 3.11.6 digilent.waveforms_beta_v3.11.6_64bit.exe digilent.waveforms_beta_v3.11.6.dmg digilent.waveforms_beta_3.11.6_amd64.deb digilent.waveforms_beta_3.11.6.x86_64.rpm Added: - Protocol - UART Spy - Max Lines option: log limit to prevent application slowdown - Line Wrap option - tooltips for UI controls listing Script access path - application and script Font options - dark theme support for Script 3.11.5 digilent.waveforms_beta_v3.11.5_64bit.exe Added: - Script open/save text file - application argument: -script myscript.txt/js Fixed: - warnings at low record rates 3.11.4 digilent.waveforms_beta_v3.11.4_64bit.exe Added: - Scope: - set/reset zero offset in each channel option - precision option for measurements Fixed: - Script: access to traces and channels from Instrument.Export - unit conversions V to Ṽ, A to à - I2S 32 bit data 3.11.3 digilent.waveforms_beta_v3.11.3_64bit.exe digilent.waveforms_beta_3.11.3_amd64.deb digilent.waveforms_beta_3.11.3.x86_64.rpm Fixes 3.11.2 digilent.waveforms_beta_v3.11.2_64bit.exe digilent.waveforms_beta_3.11.2_amd64.deb digilent.waveforms_beta_3.11.2.x86_64.rpm Added: - Spectrum, Network and Impedance Analyzer store time data when this view is open Fixed: - runscript argument - loading of docked views geometry 3.11.1 digilent.waveforms_beta_v3.11.1_64bit.exe digilent.waveforms_beta_3.11.1_amd64.deb digilent.waveforms_beta_3.11.1.x86_64.rpm Added: - Scope: out of range warning in measurements - Protocol/UART: - support up to 32bit/word - TX/RX format: text, binary, decimal, hex - Wheel Direction option - Logic Analyzer: option to swap previous/next events - Spectrum Analyzer: allowing higher number of BINs for CZT 3.10.7 digilent.waveforms_beta_v3.10.7_64bit.exe Added: - Spectrum: logarithmic magnitude scale for voltage units - Protocol: datetime stamp for SPI/I2C Spy Fixes 3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom math channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Network Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.
  2. 3 points
    For anyone else out there who's struggling with DDR3 SDRAM on the Arty A7, here's a project for Vivado 2019.2 that builds out-of-box and successfully reads / writes (via the MIG user interface) to / from memory. Hopefully this'll save someone the pain I went through figuring out how to interface with the DDR-SDRAM via Verilog. Arty-SDRAM.zip
  3. 3 points
    Hi everyone, LINX can be installed on the Raspberry Pi 4. The LINX 3.0 Target Manual Install Process (https://www.labviewmakerhub.com/doku.php?id=learn:libraries:linx:misc:target-manual-install) did not work due to changes in the latest version of Raspbian. Here is the procedure that I used to install LINX. The procedure also works on the Raspberry Pi 2B, Pi 3A+, Pi 3B and Pi 3B+ running Raspbian Buster. 1. Setup the Raspberry Pi using the latest Raspbian Buster Image. 2. Change the default password for the Pi account on the Raspberry Pi. 3. Setup a WiFi or Ethernet connection from the Raspberry Pi to your router. 4. Enable SSH on the Raspberry Pi. 5. SSH into the Raspberry Pi or open a terminal window on the Raspberry Pi desktop. 6. Check that the Raspberry Pi can access the Internet by entering the command ping -c 4 raspberrypi.org 7. Enter the commands shown in bold below. Note: The text may wrap due to the web browser window size. I recommend copying the text into a text editor to see the original formatting. The commands are in the attached file linx_install_commands.txt # Enable i2c and spi sudo raspi-config nonint do_i2c 0 sudo raspi-config nonint do_spi 0 # Update Raspbian sudo apt-get update sudo apt-get dist-upgrade -y # Install LINX sudo sh -c 'echo "deb [trusted=yes] http://feeds.labviewmakerhub.com/debian/ binary/" >> /etc/apt/sources.list' sudo apt-get update sudo apt-get install -y lvrt-schroot # Move the nisysserver.service and labview.service files to the systemctl folder sudo mv /etc/systemd/system/multi-user.target.wants/nisysserver.service /lib/systemd/system sudo mv /etc/systemd/system/multi-user.target.wants/labview.service /lib/systemd/system # link liblinxdevice.so to the Raspberry PI device driver file liblinxdevice_rpi2.so sudo schroot -c labview -d /usr/lib -- ln -s liblinxdevice_rpi2.so liblinxdevice.so # Enable the nisysserver.service and labview.service to start on boot sudo systemctl enable nisysserver.service sudo systemctl enable labview.service # Start the nisysserver.service and labview.service sudo systemctl start nisysserver.service sudo systemctl start labview.service You should now be able to connect to the Raspberry Pi from the LabVIEW Project Explorer. Cheers, Andy. linx_install_commands.txt
  4. 3 points
    Ana-Maria Balas

    MTDS PMOD Connection issue

    Hello @WillTx, 1. There is an IP for Pmod MTDS with the drivers you need to make your Pmod MTDS working. It also contains 10 demos from which you can learn a lot. You can find it here : https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodMTDS_v1_0. You need to download the entire vivado-library (from here) then follow the tutorial for using Pmod IP cores in Vivado. 2. Your block design after adding the Pmod MTDS IP: 3. You can use the board flow to automatically connect to JB Pmod connector without a XDC constrain file (as it shows in the tutorial at step 3). You need to install the board files first. If you want to use the Cora-Z7-07S-Master.xdc constraint file, below are the lines corresponding to JB Pmod connector : 4. Please follow the REAME.txt found in drivers/PmodMTDS_v1_0/examples/ Cheers, Ana-Maria
  5. 2 points
    Hi, as a simple (oversimplified?) answer, designing for higher clock speed requires higher effort (possibly "much" higher effort), and the resulting optimizations make the code harder to work with. Using the clocking wizard to generate a 500 MHz PLL is easy (try it). But writing logic at those frequencies is a different story (e.g. try to implement a conventional counter that divides down to 1 Hz. Why do all those XYX_CARRY signals show up in the timing report already at synthesis?). You also need to distinguish between what is feasible in plain logic fabric, and what can be done with dedicated "hard-macro" IP blocks such as SERDES.
  6. 2 points
    zygot

    Access to the GPIO with the API

    I'm not competent to lecture on software best practices but this topic merits discussion. Perhaps a few comments will kick one off and lure people better qualified than me to participate. There are ways of accessing hardware from software applications in just about anyway you choose. That doesn't mean that hey are all ideal or even acceptable. As a rule, using well worn libraries are preferred. In general they are not the fastest or the easiest or most simple way to interact with hardware. For safety, consistency, and orderliness they are better than reference by address. One concept is hard to argue against. If there is a possibility that another application or process has access to the same hardware then direct manipulation of hardware is a very dangerous thing to do. For some embedded projects you are guaranteed that only your code is running. This doesn't mean that direct access is a wise choice, especially if you have levels of interrupts running. For embedded systems that have an OS or RTOS where hardware is specifically isolated from end user applications by design, direct access of hardware is rather foolish because you have no control over what code the processor(s) is running a any given instant. Worse yet direct manipulation of hardware creates a situation in which neither you nor your OS can know what the state of your hardware is at any given moment. You can always alter your OS by adding kernel mode drivers if the standard ones don't fit your needs. The bottom line is understand the consequences for your design choices and code safely. You are guaranteed to pay for bad choices. For software development a general rule of thumb is that if what you are doing is direct and simple then it's likely a bad idea.
  7. 2 points
    JColvin

    Let me tell you why I HATE Digilent

    I do have to say that I was concerned when I initially clicked on this thread...but I think I'll let it stay. 😉 Please let us know if you have any questions about using the products! Thanks, JColvin P.S. I definitely sent this forum thread to our Scopes and Instruments product manager with minimal context to see what her reaction is.
  8. 2 points
    It's been too long ago but I do remember taking the scenic side journey into investigating performance of floating point on Intel processors. Mostly what I remember is that it was interesting, informing, had unexpected surprises and was a valuable exercise. Just recommending the excursion to anyone interested in 'bit exactness'.
  9. 2 points
    hamster

    RISC-V RV32I CPU/controller

    I've just posted my holiday project to Github - Rudi-RV32I - https://github.com/hamsternz/Rudi-RV32I It is a 32-bit CPU, memory and peripherals for a simple RISC-V microcontroller-sized system for use in an FPGA. A very compact implementation and can use under 750 LUTs and as little as two block RAMs - < 10% of an Artix-7 15T. All instructions can run in a single cycle, at around 50MHz to 75MHz. Actual performance currently depends on the complexity of system bus. It has full support for the RISC-V RV32I instructions, and has supporting files that allow you to use the RISC-V GNU toolchain (i.e. standard GCC C compiler) to compile programs and run them on your FPGA board. Here is an example of the sort of code I'm running on it - a simple echo test:, that counts characters on the GPIO port that I have connected to the LEDs. // These match the address of the peripherals on the system bus. volatile char *serial_tx = (char *)0xE0000000; volatile char *serial_tx_full = (char *)0xE0000004; volatile char *serial_rx = (char *)0xE0000008; volatile char *serial_rx_empty = (char *)0xE000000C; volatile int *gpio_value = (int *)0xE0000010; volatile int *gpio_direction = (int *)0xE0000014; int getchar(void) { // Wait until status is zero while(*serial_rx_empty) { } // Output character return *serial_rx; } int putchar(int c) { // Wait until status is zero while(*serial_tx_full) { } // Output character *serial_tx = c; return c; } int puts(char *s) { int n = 0; while(*s) { putchar(*s); s++; n++; } return n; } int test_program(void) { puts("System restart\r\n"); /* Run a serial port echo */ *gpio_direction = 0xFFFF; while(1) { putchar(getchar()); *gpio_value = *gpio_value + 1; } return 0; } As it doesn't have interrupts it isn't really a general purpose CPU, but somebody might find it useful for command and control of a larger FPGA project (converting button presses or serial data into control signals). It is released under the MIT license, so you can do pretty much whatever you want with it. Oh, all resources are inferred, so it is easily ported to different vendor FPGAs (unlike vendor IP controllers)
  10. 2 points
    @Vishnuk Here's a tutorial that discusses how to build both UARTs and FIFOs. Dan
  11. 2 points
    I've spent some time since my first post trying to figure out what's in store for users with Vitis. With Vivado 2019.2 + Vitis you still need a Linux host to develop Petalinux applications. It was a chore, but I did manage to install Petalinux 2019.1 onto a Ubuntu 18.04 VM running in HyperV on my Win10 Pro box. This PC has 32 GB ram so I can allocate 8 GB to the VM. I haven't as yet actually created a project with the Petalinux tool this way yet. My plan is to wait and see how well Xilinx develops the tools with the next release before moving to 2019.2 and the new paradigm. Note that Vivado 2019.2 also breaks even Xilinx IP created in previous versions. For now I'm sticking with VIvado 2019.1 and Petalinux 2019.1. In 2019.2 tools Vivado and Vitis are not integrated. You still have to export hardware but you can't launch Vitis from Vivado. I'm assuming that at some point in the future users will start off in Vitis and launch Vivado from within that IDE. ** It's been my experience that overall performance with Linux VMs in WIn10 is poor unless you start with one of the 'optimized' quick start images from Msoft. Unfortunately, there is no way to change the default disk size of 12 GB, which is way too small do doing anything useful... like even install Petalinux. You can resize the VM disk size after creating the VM but you still need to install a disk management tool like Gparted onto your VM to re-size the Unbuntu partition to make use of the expanded disk size. Needless to say all of this should be done before completely setting up and updating the VM. The whole process of installing Petalinux was rather messy and time consuming. And HyperV is... well Msoft, so get used to frustration, pain and misery.
  12. 2 points
    Hello Frankly and welcome to our forum. Here are 2 patches that can be applied on top of a Petalinux 2019.1 project to allow reading the OTP MAC and configure it to do so. You can try applying them on 2018.2. Message us back if you have any issues. Cosmin 0001-Z7-20-allow-reading-MAC-address-from-OTP.patch 0002-Z7-20-use-OTP-MAC.patch
  13. 2 points
    Hello @Bryan_S, Here is a demo project for Cmod S6 from https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/start. I looked into the source files and there is clk_gen_50MHz.vhd. You can see in the top.vhd file how the clk_gen_50MHz is instantiated and used. I don't know what is the clk16x in your code, but here are some source files for serial port serialport_v3.zip The sources are for Nexys4 DDR which has a 100 MHz system clock. But in your case, if you use the clk_gen_50MHz, you'll have a 50 MHz clock instead of 100 MHz, 9600 baud rate, as shown in the UART_RX_CTRL.vhd file. The same for UART_TX_CTRL.vhd. I don't know if you'll use the sources from above, but I hope it helps. Best regards, Ana-Maria Balas
  14. 2 points
    Hello @bitslip, Things are a little bit more complicated. Indeed, for changing the resolution you have to rewrite some registers. But you also need to make sure that the Video Trimming controller ip generates the required constants for you resolution. I wouldn't recommend to write all the needed registers from the control interface (it would be agonising) Instead I would go with the existent logic for changing the resolution, which is adding a new structure with all the register values. As an example, you can check the OV5640.H file. I much simple and quicker solution would be to use our video scaller ip. This ip was written in HLS and it was used in the fmc pcam adapter demo for re-scalling the video at a 640x480 resolution. You can check the design in here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-fmc-pcam-adapter-demo/start Best Regards, Bogdan Vanca
  15. 2 points
    Hi @attila Thank you again for all the support you've provided me for the past weeks. I am now capable of receiving more than 409 characters using the Wrapper I created base from your example. It uses the Record acquisition mode and I set the buffer size to 3 million for now. I'll increase it when the need arises. I used 1 UART controller and branched out its Tx pin to 2 DIO pins of the AD2 (DIO #0 & 1). I transmitted 500 characters: (If Record mode is not the acquisition mode, the received result will be blank) For DIO # 0, it received: with a length of: For DIO #1, it received: with a length of: I could not have done it without your guidance, thank you again and more power to you and Digilent Best regards, Lesiastas
  16. 2 points
    I own three of FMC equipped boards that you mention and frequently use at least one on a regular basis. Just for arguments sake; lets say that I want to design my own FMC mezzanine card using all of those differential pairs. Where do I find the trace routing report letting me know what the trace lengths are for the Genesys2, Nexys Video and Zedboard?
  17. 2 points
    Hi all, Quick update here. I've got binaries built for Mac and Linux (Ubuntu) and have updated the documentation to link to them. You may also download the Windows, Mac or Linux binaries by following the links I just gave you. If you encounter any issues whatsoever, submit in issue on the GitHub page and I'll set to fixing them straight away. Regards, AndrewHolzer
  18. 2 points
    Hey Paolo, I'm glad you found my videos helpful! I've been working on other projects, but if you have any other ideas for videos that you would find helpful let me know. Kaitlyn
  19. 2 points
    Yes, that cable is suitable from connection perspective. Still, there are functionality issues that you must be concerned. Most of the Pmods communicate using protocols like SPI, I2C, etc. This is specified on the Pmod datasheet. This means that the pins corresponding on the maching connector (on the system board) must implement that specific functionality. Normally using a FPGA board will be easier to configure Pmod pins to the needed functionality. Still, as you use a microcontroller board, this might be more difficult or even impossible. Please check if the pins associated to the Pmod rows correspond with the associated function on the Pmod. Another possibility is to re-configure the pins if your microcontroller allows pins reconfiguration. Please check (in the board schematic) which microcontroller pins are connected to the Pmod connector, and then check (in the microcontroller datasheet) the functions for these pins. Good luck.
  20. 2 points
    D@n

    FAT32 with Zybo Z7

    @sgandhi, Welcome to data processing. The sad reality is that text files aren't good for this kind of thing. It's not an FPGA particular thing, but rather a basic reality. 1) Text files tend to take up too much space, and 2) they require processing to get the data into a format usable by an algorithm. One way to solve this problem, which I've done in the past with great success, is to rearrange the file so that's it's a binary file containing a large homogeneous area of elements all of the same type. In my case, I wanted a file that could be easily ingested (or produced) by MATLAB. I chose a binary format that had a header, followed by an NxM dimensional matrix of all single-precision floats. (You can choose whatever base type you want, but single-precision floats were useful for my application.) The header started with three fields: 1) First, there was a short marker to declare that this was the file type. I used 4-capital text letters for this marker. That was then followed by the 2) number of columns in the table, and then 3) the offset to the start of the table. This allowed me to place information about the data in further header fields, while still allowing the processor to skip directly from the beginning header to the data in question. Further, because the data was all of the same type, I could just about copy it directly into memory without doing any transformations, and to then operate on it there. It did help that the data was produced on a system with the same endianness as the system it was read from ... Dan
  21. 2 points
    artvvb

    Zybo Z7 Pcam 5C Demo - Warnings

    To add a little bit to what Jon said, these warnings appear to be ignorable. They all relate to design choices made when connecting custom IP in the block design. Typically, even when designing with Xilinx IP, many warnings are seen in the project. These messages are there to help get information on why something may be causing bigger problems later (errors, critical warnings, something not working in actual hardware). Note that even some critical warnings may be ignored. -Arthur
  22. 2 points
    There is no code to draw any shape as you observed since it was/is a work in progress. Thus it was excluded by default from `rootfs`. However it was mentioned by mistake in the first link you mentioned. https://reference.digilentinc.com/reference/software/petalinux/start The issue has been corrected.
  23. 2 points
    Hi, Sorry to barge in, but if anybody can point me to the Hibbert Transformer info I would be very grateful. However, here is an FPGA friendly way to calculate mag = sqrt(x*x+y*y), with about a 99% accuracy. You can easily see the pattern to get whatever accuracy you need. #include <math.h> #include <stdio.h> #define M_SCALE (16) /* Scaling for the magnitude calc */ void cordic_mag(int x,int y, int *mag) { int tx, ty; x *= M_SCALE; y *= M_SCALE; /* This step makes the CORDIC gain about 2 */ if(y < 0) { x = -(x+x/4-x/32-x/256); y = -(y+y/4-y/32-y/256); } else { x = (x+x/4-x/32-x/256); y = (y+y/4-y/32-y/256); } tx = x; ty = y; if(x > 0) { x += -ty/1; y += tx/1;} else { x += ty/1; y += -tx/1;} tx = x; ty = y; if(x > 0) { x += -ty/2; y += tx/2;} else { x += ty/2; y += -tx/2;} tx = x; ty = y; if(x > 0) { x += -ty/4; y += tx/4;} else { x += ty/4; y += -tx/4;} tx = x; ty = y; if(x > 0) { x += -ty/8; y += tx/8;} else { x += ty/8; y += -tx/8;} tx = x; ty = y; if(x > 0) { x += -ty/16; y += tx/16;} else { x += ty/16; y += -tx/16;} *mag = ty/M_SCALE/2; /* the 2 is to remove the CORDIC gain */ } int main(int argc, char *argv[]) { int i; int cases = 300; printf("Irput Calculated CORDIC Error\n"); for(i = 0; i < cases; i++) { float angle = 2*M_PI*i/cases; int x = sin(angle)*20000; int y = cos(angle)*20000; int mag, a_mag = (int)sqrt(x*x+y*y); cordic_mag(x,y, &mag); printf("%6i %6i = %6i vs %6i %4i\n", x, y, a_mag, mag, mag-a_mag); } } Oh, here is the output with a couple more iterations added. Irput Calculated CORDIC Error 0 20000 = 20000 vs 19999 -1 418 19995 = 19999 vs 19995 -4 837 19982 = 19999 vs 20001 2 1255 19960 = 19999 vs 19998 -1 1673 19929 = 19999 vs 19995 -4 2090 19890 = 19999 vs 20001 2 2506 19842 = 19999 vs 19998 -1 2921 19785 = 19999 vs 19996 -3 3335 19719 = 19999 vs 20001 2 3747 19645 = 19999 vs 19998 -1 4158 19562 = 19999 vs 19996 -3 4567 19471 = 19999 vs 20001 2 4973 19371 = 19999 vs 19997 -2 5378 19263 = 19999 vs 19996 -3 5780 19146 = 19999 vs 20001 2 6180 19021 = 19999 vs 19998 -1 6577 18887 = 19999 vs 19999 0 6971 18745 = 19999 vs 20001 2 7362 18595 = 19999 vs 19993 -6
  24. 2 points
    xc6lx45

    Enevlope Detection using FPGA board

    Well yes and no. The question I'd ask is, can you use a local oscillator somewhere in your signal path with a 90 degree offset replica. In many cases this is trivially easy ("trivially" because I can e.g. divide digitally from double frequency or somewhat less trivially, use, say, a polyphase filter. In any way, it's probably easier on the LO than on the information signal because it's a single discrete frequency at a time, where the Hilbert transform approach needs to deal with the information signal bandwidth). If so, downconvert with sine and cosine ("direct conversion") and the result will be just the same. After lowpass filtering, square, add, take square-root, there's your envelope . When throughput / cost matters (think "Envelope tracking" on cellphones) it is not uncommon to design RTL in square-of-envelope units to avoid the square root operation. Or if accuracy is not that critical, consider a nonlinear bit level approximation see "root of less evil, R. Lyons". Of course, Hilbert transform is a viable alternative, just a FIR filter (if complex-valued). In case you can't tell the answer right away, I recommend you do the experiment in the design tools what happens if you try to reach 0 Hz (hint, "Time-bandwidth product, Mr. Heisenberg". Eventually it boils down to fractional bandwidth and phase-shifting DC remains an unsolved problem...).
  25. 2 points
    Hi @Lesiastas In the SDK the digital-in functions provides raw data, this needs to be interpreted in the custom application or script. See the SDK/ samples/ py/ DigitalIn_Spi_Spy.py An example UART interpreter can be found in the WF application/ Logic Analyzer/ Custom
  26. 2 points
    Hey guys, I've made some experiments that could be interesting for your as well. I put tap water into my ceramic container, I heated it to different temperatures and measured the impedance every 5 degrees. You can see the values between 60 ° Celsius (140 ° Fahrenheit) and 5 ° Celsius (41 ° Fahrenheit). Red is 60 Celsius, blue is 5 Celsius and there are 10 steps between them.
  27. 2 points
    Thanks for the update @JColvin; obviously not what we'd like to hear in so far as lack of resources behind the product but the communications is appreciated. TBH, the dlog-utils code is... not great. The majority of the code is in type conversion and formatting (i.e. not germane to the actual processing of the data); I'm not surprised to hear it's problematic in updating it for OpenLogger as hard-coded assumptions on the data header abound (e.g. endianness; I presume the author is banking on that never changing, which may well be the case but it is in the format spec). As a reference implementation it hides the important data structure information in amongst language-specific type gymnastics. In contrast the Kaitai Struct approach removes all of that, and puts the data format front and centre, is trivially extensible (you update the struct definition and rebuild the library, done), and works "everywhere". If it were my decision I'd dump the current dlog-utils and start again based on Kaitai Struct, the result would be: a proper definition of the data format (rather than users having to reverse engineer the cpp code and troll the forums) a couple of dozen of lines of code for the reference Digilent implementation and most importantly would be useful/portable in any language/environment that Kaitai Struct supports (C++/STL, C#, Go, Java, JavaScript, Lua, Perl, PHP, Python, Ruby) As an example, what is implemented in nearly 180 LOC dlog-utils.cpp is under a dozen lines in the dlog-utils-portable Python example (`dlog = Dlog.from_file(args.inputfile)` followed by a `write_csv`), with far greater flexibility in terms of handling future variations on data formats, and better output formatting 🙂 Given that Digilent have very limited resources for this project it's important they're used wisely, switching to Kaitai Struct is easily the best bang for buck we can ask for. (BTW, it might sound like I'm a shill for Kaitai Struct - nope, I'm just a satisfied user and first discovered it when writing dlog-utils-portable... I once wrote code to process structured binary data in the same way as dlog-utils, but I've now seen the light 🙂
  28. 1 point
    Thank you Attila, Now we have time stamps on start with every data packages so that we can calculate delay time between commands and commands. Nice to have time stamps on stops hence we can calculate actual clock rate of each I2C and SPI data frame. Thank you and Best regards, Wayne Chen 06/20/2020
  29. 1 point
    zygot

    Nexys4DDR Clock Speed

    So, most FPGA development boards have at least one external clock module available for FPGA internal clocking. Your first steps are to dedicate some time to reading about the FPGA device on your board. But before that you need to have a minimal ability to read the schematics for your board. Fortunately, Digilent does provide them. The schematic for your board shows IC9 as a 100 MHz clock module with a single-ended clock going to pin E3 on the FPGA. Forget about Virtual clocks for now. You need to understand your device. At a minimum read the User's Guides for Series7 SelectIO and Clocking. Also read through the VIvado tools User Guide, especially about the available design flows and how the tools support them. There is a well worn method for creating a clock with one frequency out of a different clock having another frequency. They are the Phase Lock Loop. There are two general varieties ( at least for the purposes of this discussion ) analog and digital. The MMCM uses those techniques. You can derive a clock having almost any frequency from the 100 MHz external clock from IC9 with a lower, higher or the same frequency. You can also define the phase offset between the original clock and the derived clocks. This is a basic feature of programmable devices that make them so flexible. The PLL in a myriad of forms has been around for well before programmable devices were created. Use the Xilinx Document Navigator and read, read, and then read some more. Don't expect to absorb everything at once. It'll take some time and many re-reads for the details to sink in. BTW while you don't have to understand PLL techniques it does help to have a basic understanding of the types, how they work, and the trade offs for deciding on your output clock parameters relative to your input clock depending on how it is derived. The subject is complex enough to make a whole career out of... and more than a few people have done just that. As a break from all of that reading take some time to open the Vivado IP clocking wizard and run through setting up a derived clock that you want. There's a user's manual for all of the Xilinx IP to help understand what you are doing. The wizard will create instantiation templates in the whatever HDL the project settings are to help use it. Only people who really understand what they are doing should use HDL primitives for using clock resources. I almost always use the wizard unless there isn't a suitable one available for my device. The tools and your design will just get along better that way. You do have to understand what the wizards are doing and not assume that it's what you want to do. Also, since we are talking clocks it's a good idea to read the datasheet AC switching specifications for your FPGA device and speed grade so that you don't do something stupid.
  30. 1 point
    HJM

    defect power supply AD2

    thank you attila for your real good support - but the sugggested repair has not shown any positive result - as I already assumed for this kind of error, there must be affected a lot of circuits by the -20V coupled to the GND line (the lab power supply may have delivered up to 2 A until shut-down) and this may have killed something hidden ! Fortunatly the price of the AD2 module is quite affordable - so we will buy a new one (as in principle it is a really got device for some tests) - perhaps we will try to connect it to the PC over an USB isolator (can you recommend a specific brand that you have succesful tested?) Best regards and thanks again HJM
  31. 1 point
    Well OK, what I wrote was maybe not accurate to the final digit ... What I meant is this "The IEEE standard goes further than just requiring the use of a guard digit. It gives an algorithm for addition, subtraction, multiplication, division and square root, and requires that implementations produce the same result as that algorithm. Thus, when a program is moved from one machine to another, the results of the basic operations will be the same in every bit if both machines support the IEEE standard. This greatly simplifies the porting of programs. Other uses of this precise specification are given in Exactly Rounded Operations." Intel got quite some publicity on their division bug so I'd assume those should work properly (note, not a word about logarithms) but yea, this is not my specialty area
  32. 1 point
    chcollin

    Is Atlys HDMI 2.0 compliant ?

    Got my answer : "Unfortunately the Atlys is unable to handle 1080p60Hz because of the timing requirements of its FPGA. This is not something that can be changed via an update. The reason the Atlys can't handle a 1080p60Hz signal is because it requires deserialization/serialization at a rate of well over 1 Gb/s, and the Atlys can only handle deserialization/serialization at a max of 950 Mb/s." Is-1080p60-video-possible-at-all-with-a-Spartan-6-board-Atlys
  33. 1 point
    @youngpark, The CmodS7 has only 3.3V I/O banks. You will not be able to generate anything other than 3.3V outputs. I took a quick glance at the schematic and didn't see any length matched GPIO pairs. Depending upon the performance you need, this is often a requirement. You might still be able to break the rules and create two LVCMOS3V3 digital outputs, each opposite each other, to make this happen but it doesn't appear as though the board was designed to support such a requirement. If you choose to do that, then let me recommend you use two ODDR primitives, each with opposite polarity, to try to make this work. That'll at least help you get the timing right. Dan
  34. 1 point
    Physically, nothing is different. It was a labeling thing when the chipKIT logo was removed.
  35. 1 point
    JColvin

    PMODs - Spec 1.2.0

    Hi @andresb, I apologize for the delay. The best way to determine if they are complaint with specification 1.2.0 is by looking at their respect Resource Center (such as the Pmod AD1). On the right-hand side under Electrical, you will see the Specification version that the Pmod is currently compliant with. The Pmod Interface Specification 1.2.0 is available directly here: https://reference.digilentinc.com/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf. Let me know if you have any questions about this. Thanks, JColvin
  36. 1 point
    Hopefully. when Digilent spins the next CMOD they will provide a better arrangement for using the configuration circuitry with an external power supply. Even as a standalone module configured from flash 1 Vcc pin and one GND pin is less than ideal, and likely problematic if the FPGA is driving or receiving a number of single-ended signals.
  37. 1 point
    Hi @satvik, I apologize for the delay. The reason the Cora Z7-07s is not present in Vivado 2015.4 and 2016.1 is because Xilinx had not added those parts to their software. From what I know, the XC7Z007S chip (the SoC present on the Cora board) was not added to the Vivado WebPACK version until 2016.3. Otherwise, if you are looking to follow Digilent made examples for the Cora Z7-07s, I would recommend using Vivado 2017.4 or 2018.2 as those are the versions of Vivado that we have made examples for the Cora Z7, which you can find in the Cora Z7's Resource Center. Thanks, JColvin
  38. 1 point
    xc6lx45

    I bricked my CMOD-A7

    Thinking aloud: Is it even possible to "brick" an Artix from Flash? On Zynq it is if the FSBL breaks JTAG, and the solution to the problem without boot mode jumpers is to short one of the flash pins to GND via a paper-clip at power-up. But on Artix? Can't remember having seen such a thing. Through EFUSE, yes, but that's a different story. If you like, you can try this if it's a 35T (use ADC capture at 700 k, it stresses the JTAG port to capacity). For example, it might give an FTDI error. Or if it works, you know that JTAG is OK.
  39. 1 point
    FYI, Attila is on vacation returning on Oct. 9th.
  40. 1 point
    Glenn

    USB Power

    Upon further reflection, I bet my switched cables do not have all the USB lines coming through. RPi only needs power via it's microUSB input.
  41. 1 point
    Hi @m72 The 1kHz is generated from the 100MHz system clock with 50% duty. The 1.1kHz is actually generated as 1.099989kHz with 49.9945% duty. Due to this the 180* phase, the middle falls in low level which gets used as initial value. For the next release I have modified the duty to round up, so the 1.1kHz will have 50.005499945% duty and the 180* phase will start high. I'm also adding negative delay for the next version. Thank you for the observation. Current version: Next version:
  42. 1 point
    Hi @m72 The preview is further fixed. I hope there are no more issues with this: https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ Here you have the project: EMU_2CH_EACH_V10 (2).dwf3work
  43. 1 point
    Bianca

    JTAG-HS2 firmware erased by accident

    Hi @Chouchene, You have a private message. Regards, Bianca
  44. 1 point
    Hi @osti 1. The Sync mode on Digital Discovery uses re-sampling at 1.25ns (800MHz) resolution. This uses the device triggering mechanism, so when using Sync mode the trigger options are not available. 2. At the moment only 100MHz base frequency is supported. I'm planning to add option to be able to fine adjust this frequency, like: 50.00836820083682, 50.00985221674877, 50.01197604790419, ... 98.86567164179104, 98.87323943661971, 98.88, ... ,99.97714285714285, 100 MHz
  45. 1 point
    jpeyron

    zynq c code feedback needed

    Hi @dmeads_10, It looks like the setdirection function is not correct in your attached sdk code. I believe the LED should be 0x0 and SWITCH should be 0x1. Here is the Getting started with zynq tutorial. Below is the SDK code for linking the switches to the LEDs and btns to the uart usb bridge. I have attached a screen shot of the vivado block design. I would suggest using the Digilent board files for the Arty-Z7-10. The installation tutorial is here. You would not need to use an xdc file and the board tab would allow you to easily add the switches,led and buttons to the design. The getting started with ZYNQ tutorial linked above is basically the same process for the arty-Z7-10 just different number of components and a different zynq board. Best regards, Jon
  46. 1 point
    xc6lx45

    xadc_zynq

    I'd recommend you spend a working week "researching" the electrical-engineering aspects. The ADC may look just as an afterthought to DSP but it will require significant engineering resources (plan for several / many man-months). Long is the list of bright-eyed students / researchers / engineers / managers who have learned the hard way that there is a bit more to the problem than finding two boards with the same connector... Hint, check how much latency you can tolerate and research "digitizer" cards for PC (or PXI platform). If you don't need a closed-loop real-time system, don't design for a closed-loop realtime system.
  47. 1 point
    @sungsik, So let me shoot in the dark and ramble and see if it helps clarify your question. There are many ways you can design things on a Zynq. You can create state machines like you did before on the Spartan 6, making logic just like before that will work without a CPU. Indeed, you can still control I/Os like before if you want. The AXI GPIO core may be nice, but it is certainly not required. You can create AXI slave cores. Anything you create with a slave interface can be connected to the ARM in the Zynq and can interact with the ARM. This is typically very useful for controlling peripherals from the PS. You would write software commands to interact with your device, and off you go. This might be the easy way to interact with the AXI GPIO, but it is by no means the only way. There's also a discussion to be had about where the O/S / Application division will be within your software and how to write a proper device tree entry for IP cores that will be controlled from Linux. You can also create AXI master cores in PL. Your AXI masters can then be used to drive AXI slaves. So, for example, if you wanted to control the AXI GPIO as a state machine on board, all you would need to do is to connect an AXI master to it to do so. This would apply to any DDRx SDRAM as well. Yes, it is possible to connect an AXI master to multiple slaves, this requires an interconnect however. Which method you choose is up to you, the designer, and the specific and particular needs of your project. For example, logic is limited but fast, whereas software tends to be abundant but not nearly as fast. Further, most CPU software will produce (fairly) unpredictable timing, where as timing can be tightly controlled from the PL. Hopefully these ramblings will at least suggest where the conversation might go next. Dan
  48. 1 point
    Hi @Foisal Ahmed, We are very sorry for the inconvenience. The PDF version of our reference manual for the basys 3 wasn't updated with the additional information on the WIKI version of the reference manual. This will be fix shortly. The WIKI version of the reference manual here states : "Some Basys 3s have been loaded with a Flash device from Spansion (part number S25FL032), while others have been loaded with a Macronix device (part number MX25L3233FMI-08G). The part loaded on any particular board can be determined by checking the part number and manufacturer logo printed on the Flash IC itself, as seen in the images below." If MX25L3233FMI is not an option in Vivado 2015.1 i would suggest to install a newer version of Vivado. I would suggest Vivado 2017.4 or higher. best regards, Jon
  49. 1 point
    attila

    Math on FFT traces

    Hi @lab!fyi In the Network Analyzer extended option lets you use Wavegen channels at up to 20MHz and with external up to 50MHz. In the Spectrum Analyzer you can select frequency range up to 10MHz but with auto option lets you set Stop frequency up to 50MHz. Selecting the dB unit will let you specify custom reference, for dBm I think it should be 0.316V
  50. 1 point
    Hi @AvnetRH, I haven't ever worked with this particular power supply so I do not know if this is true, but there is a possibility that the Xilinx Development boards may refer to development boards that Digilent sells (such as the Arty). After getting some more information from our sales team (since the part is not directly available on our website), it seems you will need to email our sales team, sales at digilentinc dot com, to be able to request that specific power supply. Thank you, JColvin