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Showing content with the highest reputation since 11/05/19 in all areas

  1. 2 points
    Hello @Bryan_S, Here is a demo project for Cmod S6 from https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/start. I looked into the source files and there is clk_gen_50MHz.vhd. You can see in the top.vhd file how the clk_gen_50MHz is instantiated and used. I don't know what is the clk16x in your code, but here are some source files for serial port serialport_v3.zip The sources are for Nexys4 DDR which has a 100 MHz system clock. But in your case, if you use the clk_gen_50MHz, you'll have a 50 MHz clock instead of 100 MHz, 9600 baud rate, as shown in the UART_RX_CTRL.vhd file. The same for UART_TX_CTRL.vhd. I don't know if you'll use the sources from above, but I hope it helps. Best regards, Ana-Maria Balas
  2. 1 point
    Hey All, We recently posted a new version of WaveForms Live which ads some new features. This blog post lists all the changes in the update.
  3. 1 point
    Hi @sgrobler, I think it's entirely possible to include a timestamp in a log header when starting a session from a connected host. I'll put this on my list of additions & fixes, put some thought into a proper solution and get to work on it. I'll personally message you once I've made the changes (and you'll probably see a blog post about them as well). Regards, AndrewHolzer
  4. 1 point
    Hi @Bryan_S, We don't have the necessary resources to investigate/correct the code of your project. However the source code I provided to you above, is readable and you can test it with your project. Just integrate the clk_gen_50MHz.vhd and UART_RX_CTRL.vhd files to your project. I think those files are all you need. Cheers, Ana-Maria
  5. 1 point
    Sometimes people mistakenly try to create a derived baud rate clock that closely matches the baud rate. UARTs should be able to accommodate a significant variation of baud rate error, perhaps 15% or so. So a better way to think of it, particularly on the receive side is creating lots of samples and keeping data transitions near the middle of a baud's worth of sample units. This means that clocking the UART entity at a high clock rate, providing a lot of samples per baud period, will be optimal. A 50 MHz clock for 115200 baud is fine but I've been using a 100 MHz clock for 921600 baud that's reliable. Don't think or hope... simulate, simulate.. and simulate some more. The first thing that I'd do if made custodian for someone else's code would be to simulate everything until I understood it. Reading source text often not sufficient and commentary is rarely accurate. There are a number of UART based projects in the Digilent Project Vault, some with testbench HDL tha might be helpful.
  6. 1 point

    Problems FFT IP CORE v 9.0

    @Kenny, If you are an FPGA beginner, then ... I would start somewhere else. I would recommend starting by learning how to debug FPGA designs. The problem with FPGA development is that, unlike software, you have little to no insight into what's going on within the FPGA. There are a couple keys to success: Being able to insure your design works as intended before placing it onto the FPGA. Simulation and formal methods work wonders for this task. Unlike debugging on hardware, both of these approaches to debugging offer you the ability to investigate every wire/signal/connection within your design for bugs. If you are unfamiliar with these tools, then I would recommend my own tutorial on the topic. Being able to debug your design once it gets to hardware. This should be a last resort since its so painful to do, but it is a needed resort. To do this, it helps to be able to give the hardware commands and see responses. It helps to be able to get traces from within the design showing how it is (or isn't) working. I discuss this sort of thing at length on my blog under the topic of the "debugging bus (links to articles here)", although others have used Xilinx's ILA + MicroBlaze for some of these tasks. Either way, welcome to the journey! Dan
  7. 1 point
    You are welcome, we are happy that the flash is programmed. Unfortunately this project seems to be marked as having internal use. And maybe this is the reason you get so many problems, as the documentation is not detailed enough.
  8. 1 point
    Hello, Since you mentioned that you successfully built the mcs file you can choose an alternate way to program the flash. Instead of using the SDK (the recommended way in the mentioned readme), let's use Vivado. Please open Vivado, do not open a project. In the the welcome screen please open Tasks/Hardware manager. Then Open Target / Autoconnect, you should see your FPGA in the Hardware tree. Right click on FPGA, select "Add Configuration Memory device ...". Select s25fl128sxxxxxx0-spi-x1_x2_x4. Then right click on the flash device you just added in the Hardware tree, select "Program Configuration Memory Device ..." and select your mcs file to be programmed. Please note that the board used for this caption uses a different FPGA. On the other hand, if you want to address the errors you mentioned in your previous post, most probably you lack the (HDL) top wrapper. Please right click on system.bd, select "Create HDL wrapper ..." and then rebuild. Good luck.
  9. 1 point
    Hi @Lesiastas No. You should leave it as it is. From your question I thought you are using the WF application. To reduce the device connection/opening latency use the on-close param. To 'intelligently' stop the recording process you could analyzer the received data chunks (samples) and when there is no UART activity on the lines for X time (N samples). This depends on you project...
  10. 1 point
    Hi @sgrobler, I am able to successfully connect to my phones WiFi hotspot on firmware 1.3.0. I get the same message pop-up as you regarding the firmware update required, but I click the "OK" option and then select the Instrument Panel where-upon am I greeted with the same message, choose OK again, and then I am brought to the Instrument Panel where I am able to successfully run the OpenLogger. I do agree though that the pop-up message should not be occurring though. I have reached to @AndrewHolzer to help address this. Thank you for the feedback, JColvin
  11. 1 point

    Problems with PetaLinux for Zybo Z7-10

    1) https://github.com/Digilent/Petalinux-Zybo-Z7-10 2) Download the BSP and decompress it. BOOT.BIN and image.ub are in pre-built/linux/images
  12. 1 point

    Working with DA4 PMOD on Nexys4

    Thanks a lot Arthur, I am a beginner in Vivado so I didn't know about its simulation tool. I have now used it and solved most of the issues in the code and got the PMOD DA4 module to run correctly. I have attached the working file here in case someone else needs it. Thanks, Mohsen DA4_v11_working.vhd
  13. 1 point
    Ana-Maria Balas

    ZYNQ UART Issue

    Hello @Irfan, Which board are you using ? Also could you post a screenshot of your block design ? Cheers, Ana-Maria
  14. 1 point
    Hi @Lesiastas As initialization when you application starts, before calling open set the following option to 0/Run: dwf.FDwfParamSet(DwfParamOnClose, c_int(0)) # 0 = run, 1 = stop, 2 = shutdown 2 - open always takes 'long' time (~300ms) since the device is powered down on close and reprogrammed on each opening 1 - device remains powered but the outputs are stopped on close, this takes a few ms on open/close * 0 - device continues the output after close (waveform, pattern generation, supplies), the open/close are fast * *The first open after power up will take 'long' time since the device needs to be programmed.
  15. 1 point
    Hi @AvnetRH, I haven't ever worked with this particular power supply so I do not know if this is true, but there is a possibility that the Xilinx Development boards may refer to development boards that Digilent sells (such as the Arty). After getting some more information from our sales team (since the part is not directly available on our website), it seems you will need to email our sales team, sales at digilentinc dot com, to be able to request that specific power supply. Thank you, JColvin