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Showing content with the highest reputation since 07/06/20 in all areas

  1. 1 point

    USB audio on PYNQ-Z1

    Hi @tara901, I need to know some more info before we go further. What Linux are you using on the target and where did you get it? What USB-Mic are you trying to use? -Ciprian
  2. 1 point


    So cable drivers must be installed if you can program the FPGA. As to why you cannot run Hello world, check the logs for clues on whether elf download succeeds and could even try debug to see where the processor is stuck at. SDK terminal show a crash of some sort.
  3. 1 point


    Did you forget to install the cable drivers perhaps? https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug973-vivado-release-notes-install-license.pdf#G5.401934
  4. 1 point
    Hi @g3333t, It is possible to do this. You would need to do some networking to get this set up though. One option would be to open a port on your router and then forwarding the traffic to the OpenScope MZ. At that point you would just need an address that is accessible via the internet at large which you put into WaveFormsLive when connecting via network, which will be dictated by your ISP. Alternatively, you could set up a VPN connection between your remote computer and a VPN server on your home network that has the OpenScope MZ/WaveFormsLive available and SSH into it, but that would be a bit more work to get going. Thanks, JColvin
  5. 1 point
    Tim S.

    SPI Memory Tester: IPI-BD for Zynq

    Hi @JColvin, I'd be glad to have the project(s) shared with the community on Digilent's own Wiki pages. Note that I'll do my best to keep the Git repository copacetic. Thanks! Tim S.
  6. 1 point


    I don't think what you are trying to do is possible. Library xfopencv, Xilinx's OpenCV implementation for HLS, much like the original one assumes there is an OS.
  7. 1 point

    16 Bit Parallel Output read

    Dear Attila, Thanks for your kind help, yes it worked. I am now able to see the data. The next task that I want to achieve is to be able to feed the same data through my DigiLent device to my device. So I want to use the patterns functionality of the WaveForms programm. So my question is could this data now be some how fed into the WF software ? Thanks in advance for your kind feedback.
  8. 1 point

    2.7 Voltage cap on mesurements

    Ah, of course! Thank you very much!
  9. 1 point

    Not a Marvell or TI Ethernet PHY

    Hi @trayres, You are correct in that the LWIP doesn't readily support Realtek devices, though I do not why this decision was made on Xilinx's end. You can view a couple of threads about this error on the Xilinx forum here and here as well as a discussion on the Xilinx GitHub here where extra material to support other PHYs was offered to be added, but declined anyway. I know that Digilent did make an update to more readily support Realtek PHY's for 2019.1 as mentioned in this specific post here: https://forum.digilentinc.com/topic/18837-ethernet-on-genesys-2-board/?do=findComment&comment=53349; the post was for the Genesys 2, but will also apply to the Nexys Video. Thanks, JColvin
  10. 1 point
    Hi @jonesthechip You will have to download and install Adept Runtime and WaveForms packages. Depending on the used OS architecture the 32bit ARM (Raspberry Pi, Ubuntu 32bit arm...) or 64bit ARM (Ubuntu 64bit arm)variants. https://mautic.digilentinc.com/adept-runtime-download https://mautic.digilentinc.com/waveforms-download Install by double-click or from terminal with the commands: $ sudo dpkg -i digilent.adept.runtime_2.20.1-armhf.deb digilent.waveforms_3.14.2_armhf.deb or $ sudo dpkg -i digilent.adept.runtime_2.20.1-arm64.deb digilent.waveforms_3.14.2_arm64.deb
  11. 1 point

    Waveforms does not open (Windows 10)

    Hi @jowell88 I have not see such issue so far. Which software version are you using? Try opening WF in safe mode. This will open the app without loading the last settings, file history...
  12. 1 point
    Hi, I solved this problem and I will answer here if it can help someone. The problem is that the RFID module crosses RX and TX (DTE device) as can be seen from the scheme in my previous post. This makes that TX from the RFID module is connected to T1OUT and RX to R2IN in pmod rs232 (see this). The solution was to swap RX and TX in the RS232 side, i.e., before connecting to the pmod rs232. It took me two days full time to figure this out...bear always in mind that this pmod rs232 module is configured in DCE mode! Regards.
  13. 1 point

    Measuring Average Current

    Hi @Nikosant03 Having the shunt on the GND side will require rail-to-rail amp or a negative rail to supply it. You could also use a fully differential amplifier since the AD scope inputs are differential. I think an inst-amp should give the best results: https://en.wikipedia.org/wiki/Instrumentation_amplifier Sorry but I'm not an electronics engineer to projects such or to suggest exact parts.
  14. 1 point

    Measuring Average Current

    Hi @Nikosant03 Such low shunt resistor voltages should be amplified by an instrumentation amplifier and this connected to the Scope input.
  15. 1 point

    2.7 Voltage cap on mesurements

    Hi @Amund You have configured the Scope Channel 1 to 5V pk2pk range. This, with the default 0V offset will have input range of about +/-2.5V The AD has 2 input ranges approximately 5Vpk2pk and 50Vpk2pk. Use: dwf.FDwfAnalogInChannelRangeSet(hdwf, c_int(0), c_double(50))
  16. 1 point
    Tim S.

    SPI Memory Tester: IPI-BD and VHDL

    Hi to the community. I would like to mention that I have posted a FPGA design that memory byte tests the Pmod SF3 with 256Mbit N25Q flash chip. You can find a link to this project at http://timothystotts.github.io/. The name of the project is fpga-serial-mem-tester-1 . The project sources contain some features beyond testing the QSPI flash chip. Regards, Tim S.
  17. 1 point

    2.7 Voltage cap on mesurements

    Hi @Amund, I have moved your thread to a more appropriate section of the forum where the engineer more experienced with the scripts associated with the WaveForms software will be able to see and respond to your question. Thanks, JColvin
  18. 1 point

    Scope Continuous Record and Save *.csv

    Truly amazing how versatile your software is! This works great. Thank you. Screenshot below for future lurkers and my future self. Bit off topic now, but is there a command to reset "Measurements"? (Yet again, I cannot find it via this forum or documentation) Is there a more thorough API documentation available somewhere?
  19. 1 point

    Question about I2C protocol trigger

    Hi @attila, Thanks for the answer. I did not noticed that I can type in the value. It's working now just like the picture below.
  20. 1 point

    Measuring Average Current

    Hi @Nikosant03 1. The Average Measurement is the average current you wanted earlier. 2. The Sample Mode can be found under each Channel gear drop-down, it is by default on Average. 3. For such low current/voltage measurement the signal should be amplified ! The Scope resolution is about 300uA, the same level than the voltage you are measuring. 4. The Scope inputs are differential. For better result you should use differential measurement on the shunt resistor, like 1+ -> Rsh -> 1- 5. You should take in account the 1M probe impedance, 1.8uA with 1.8V/1M 6. To improve the measurement, to reduce the offset error, temperature drift: Perform a capture with the measurement setup but disconnected load, then under Time Options select Zero Offset and OK. 7. You can use Record mode to capture more samples to improve Measurements.
  21. 1 point
    Tim S.

    MuxSSD driver for the Pmod SSD

    I authored a minimal Vivado IP design to control a single Pmod SSD with extension cable on a single jack of a FPGA board. The IP is called MuxSSD and allows writing either digit at any time with no need to use a fast GPIO trick in the application C code. This driver is part of my previously mentioned Accelerometer Tester design. The project is hosted at: https://github.com/timothystotts/fpga-serial-acl-tester-1 . Tim S.
  22. 1 point

    Genesys 2 restock date.

    Hi @tuskiomi, I'm not aware of anything in the works, but I (or other incredibly helpful people on this forum) may be able to recommend an alternate board for you if you let us know what you are looking to do in your project. Thanks, JColvin
  23. 1 point

    Genesys 2 restock date.

    Hi @tuskiomi, Based on the listing for the Genesys 2 on our store page https://store.digilentinc.com/genesys-2-kintex-7-fpga-development-board/, I believe it will be available again in September 2020 (thanks virus). I have not seen anything indicating if this timeline has changed. Thanks, JColvin
  24. 1 point

    Nexys A7-100

    Does the board have power? Is LED "LD22" lit? The board can get power from the USB port, from a barrel connector, or from a battery/power supply connected to JP3/JP12. You need to make sure the jumpers are set correctly to correspond to the power source you're using. It's marked on the board's silkscreen, so it's easy to check and to set. Do you have the USB cable plugged into the "Prog/UART" USB port or the "USB Host" port? Your USB cable needs to be plugged into the "Prog/UART" port to supply power to the board and/or program the FPGA. Also, and this may be too obvious, so excuse me for pointing it out, the board has a power on/off switch next to the barrel connector--this switch needs to be in the "ON" position.
  25. 1 point


    Hi @[email protected], The correct link for the dual camera release (using 2018.2) is available here: https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-Dual-Camera/releases. Thanks, JColvin
  26. 1 point


    Hi @[email protected], I have reached out again to another engineer more familiar with the Pcams; I am not certain what the problem might be. To clarify, were you experiencing the same problem with the dual camera demo? Thanks, JColvin
  27. 1 point

    Fun with Phasors!

    To all, I've updated the archive with a new version of the OCTAVE script that allows Linux users to change modes and waveforms, all from one place. Windows users now have a choice of using OCTAVE or Putty to use the demo. Unfortunately, Putty on Linux doesn't support pasting text or sending files.
  28. 1 point

    WaveForms counter?

    Hello Attila, yes that would do the job (I have to remember subtract one from the totalizer though). But still I have such a feeling this is just emulation of counter by means of Logic analyzers Trigger. According to WaveForms concept (set of laboratory devices in one software), i would suggest to add counter among devices in Welcome window. Thank You for the solution anyway. Have a nice day! Ondrej
  29. 1 point
    True but you'll need some means to break down the problem into smaller pieces that can be debugged individually. Otherwise you have this big black box and the information "it doesn't work". I'm not trying to sell you any methodology, simple answers or miracle tools - I would cut most corners myself if I had to do a similar job but you may need a little more "scaffolding" if doing it for the first time. A lot more if learning FPGA design along the way. BTW, the current consumption of your codec might serve as quick-and-dirty indicator that your register writes are going through (works for a module, not sure if this will help you)..
  30. 1 point


    Hi @[email protected], The cables look good. Does the camera which looks like it's attached to Port C work? Do you get an errors in the serial terminal with regards to the cameras attached to ports A and B? I presume you are not getting anything on the screen output based on the phrase "I couldn't turn on Port A, Port B cameras" Thanks, JColvin
  31. 1 point

    Arty A7 flash clock

    Hi @[email protected] and @zygot, I apologize for the long delay. The pin is indeed still present on L16 on page 6 of the schematic and is almost certainly the intended use of that pin. I'm not sure why it's not the .xdc (or if it ever was, since realistically the .xdc was copied over from the original Arty .xdc before a bunch of other Arty branded boards were introduced), so I'm working to confirm that there isn't some reason that the pin should not be in the .xdc and then we get it added in. Thanks, JColvin
  32. 1 point

    How to Find Trigger Rate?

    Hi @jpaulus There is no dedicated trigger frequency measurement available. It was supported very long time ago, but it was not too popular. It was removed and the device resource reused for other features. Now you could use the following setup to measure the trigger rate: 1. You can connect Trigger 1 to DIO 0 wire. 2. Configure Settings/ Device Manager/ Trigger 1 = Scope Detector. 3. In Logic Analyzer configure Sync capture with Clock on DIO 0 4. Use a Script to measure the time it takes to have certain amount of triggers. var t = Date.now() Logic.single() Logic.wait() t = 0.001*(Date.now()-t) // milliseconds to seconds print(Logic.Time.Samples.value/t) // rate = trigger count / time
  33. 1 point
    Ok, found the problem after reading this post, which described sort-of similar problems: https://forum.digilentinc.com/topic/19306-digital-discovery-spi-repeating-trigger-problem/ If I install the latest beta version (3.13.22 beta) the DD devices work as expected (generated frequency within ~ 10 ppm). Also, the input side (sampling an externally generated clock) is much more stable. So it seems to be a firmware bug in the current 'official' release which is fixed in the beta. Hopefully a new official release will be out soon.
  34. 1 point

    Pmod I2S2

    It looks like I was looking at the output sample rates rather than the input sample rates on that same page; I have adjusted the reference manual to only reflect the lone single speed sample rate. Thank you for pointing out this error.
  35. 1 point

    Pmod I2S2

    Hi @Rainer, I'll look into this some more. The CS5343 datasheet on page 9 does explicitly list both of these two sample rates, though I'm not sure of the difference between them as of yet. Thanks, JColvin
  36. 1 point


    Hi @[email protected], I am not sure what the issue might be. I have reached out to another engineer for their input on this. Thanks, JColvin
  37. 1 point

    ADC bits and resolution

    got the answer here: thanks anyway
  38. 1 point
    Hi @m72 You could use "Not Ends with" or "Not Contains", Filter: "K"
  39. 1 point
    @[email protected] @zygot Quick update: the Xilinx clock domain crossing macros work fine and I have eliminated the timing exceptions. Thanks for your input.
  40. 1 point

    Video RAM in DDR

    On a slightly higher level of conceptualization, for something like a video buffer. I do want to point out that a lot of solutions to FPGA design problems have nothing to do with programmable logic or HDL or development flow. While being given a relatively easy path to constructing complex structures may get you so far... they also only get you so far, and are limited in how you can use a very limited set of structures. Better to learn about video, and older ways of implementing video and constructing those structures. There's a danger to having a false sense of accomplishment and thinking that you've overcome a particular design obstacle, when in fact you've just used a borrowed toy that you can't keep. Like most things in life, the quality and usefulness of things that you acquire are directly tied to the amount of work and effort put into obtaining them. Perhpas. one day, the only source flow for FPGA development will be an AI that you say " Hey Vivi, I'd like to do.....". I for one, am not waiting with eager anticipation for such a day when man is dumber than his robotic creations or can't imagine without them.
  41. 1 point

    Video RAM in DDR

    @Ciprian, I'm glad that you decided to add a bit more shading to a very important philosophical concept. It's hard to capture all of the important facets in one post reply. While you are correct that I do advocate for what is a harder, slower and more demanding design source choice in going all HDL, I do understand that there are projects and people for whom that might not be the best choice. No one know how hard it is to maintain a demo so that customers can replicate a project over the course of even a few Vivado revisions than the fine people at Digilent. A high percentage of posts to the FPGA forum revolve around user's inability to merely build demos created in older versions of Vivado. What I can say with certainty on that subject is that I have HDL code that I wrote 20 years ago, not even for a Xilinx target device, that I can still use today. No hassle, just add the source to my current project. True, some use basic resources like block memory or clock generators that are implemented differently from device family to device family or vendor to vendor, but even those are pretty simple to change. A recent version of Vivado broke all HDL source code using its own basic resource IP. But fixing the issue isn't a major headache. As long as I record notes about the design process and document my code well I never lose the IP that I write, nor the understanding of how to address a design problem. If your design relied on IP that was free and was changed to requiring a license there's only only one option, which is to keep an older version of Vivado around to use the 'free' IP. The quotes around free are there because free always has a cost in one form or another. The 'free' IP and board design flow can certainly produce a result in a short period of time but it also comes with not so obvious strings attached. Some of these strings you've pointed out. The truth is that it takes time and commitment to get to the point where anyone can master FPGA development to the point where you can have the confidence to tackle complicated projects with all HDL source code. My argument is that the board design approach entices novices into thinking that you can do substantial FPGA development without the HDL skills. I say, after you have the skills then perhaps you are in a position to evaluate whether or not the 'free' IP is worth the cost. I liken the board design flow to a walled garden, but perhaps a sandbox is a more appropriate analogy. Sure, there are things that you can do without much knowledge or hassle in the sandbox but eventually you will get bored with the limited toys available to you and need to add your own HDL anyway. And no one like having their limited selection of toy taken away form them once they are relied on. To my way of thinking, the hard arduous path to working with programmable devices is the inevitable path if you are going to keep doing FPGA design for any length of time. If you have any interest of doing FPGA development professionally, then you have better have the skills and experience in figuring out how to find your own conceptual design solutions and strategies for debugging designs and verifying designs. The board design approach provides little or no support for the really important skills needed to be self-sufficient. I completely agree with the premise that it is up individuals to decide what design source flow is best for them or their project. And considering all points of view and the experiences of others is an important part of that decision making process.
  42. 1 point

    cmod S7 zyboZ7 connection

    UART over Pmod.
  43. 1 point
    Hello @SamuelCroteau, Did you checked the chapter https://reference.digilentinc.com/learn/courses/unit-3/start#appendix_clcd_custom_characters for creating custom characters? you can use it to create the Tetris blocks. You can found the source code for the Unit 3 course at the bottom of the page https://reference.digilentinc.com/reference/microprocessor/basys-mx3/start Also you can find some info here: https://www.makerguides.com/character-lcd-arduino-tutorial/ You also have some libraries here which I found them useful: https://github.com/fdebrabander/Arduino-LiquidCrystal-I2C-library
  44. 1 point
    Hi @STEAMClown, I apologize for the delay. I did some digging since I've personally never even heard of this board before, and while I was not able to find any written documentation (I suspect there isn't any to be found), I was able to locate the schematics for this board which I have attached, though it doesn't look like there are any hidden gems with this board. Let me know if you have any questions. Thanks, JColvin LIN sch.pdf
  45. 1 point
    New Digital Discovery user. I did not purchase this device for its excellent documentation or thorough applications examples (which are not so great), but because it can capture SPI at 800MHz with the special adapter. I understand that the Digital Discovery will stream the captured data to memory and I can save it to disk. I'm debugging a difficult SPI issue, and need to see as much detail as possible (hence the 800MHz). Out test code captures some 30,000 rows of 14 consecutive 14-bit reads at an SPI clock speed of 27.5 MHz. This is a whole lot of data. We need to see the protocol capture results and compare it with what our embedded system is reporting. We read a very slow, clean R/C ramp (falling), gather all the data, and create a statistical plot which tells us how many "hits" we get on a certain bin value. Here's a snip: In this example, and despite the fact that our input ramp is changing in a very linear fashion (and therefore we should see equal distribution), decimal 4083 (ending in 100011) has far fewer hits than those adjacent. Each column (in the green) is a single SPI read of our ADC. We do 14 through DMA (very fast), and then repeat without much delay. I thought Digital Discovery would (a) trigger on the falling chip select, and (b) keep recording the data stream (ignoring subsequent chip select cycles). It doesn't. Instead, it captures the first 14 samples and no more data after that. Hopefully it's possible to trigger on CS (going low) and just keep sampling until I press stop. (Ideally if there's a timeout value allowing us to stop once CS stays high for a certain duration, that would be ideal). Finally, I have no idea how to save my data to a file and in a certain format. My setup: Please help this new user. I suspect it's simple, but the online docs are not very revealing, and experimentation isn't getting me far. Thanks!
  46. 1 point

    Xc9536 jtag

    Hi @Jpyro1, In general, the Digilent programming cables are not compatible with the 9500 series CLPDs. There is one comment from another user on our Forum here, https://forum.digilentinc.com/topic/3607-jtag-usb-programming-xilinx-9536-with-impact/?do=findComment&comment=13548, that says they were able to program a 9536 CPLD by creating an SVF file with iMPACT and then program the device through Adept. I do want to clarify that those of us here at Digilent have not attempted this though, so I can't vouch for this method. Let me know if you have any questions about this. Thanks, JColvin