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Showing content with the highest reputation since 06/29/20 in Posts

  1. 1 point

    cmod S7 zyboZ7 connection

    UART over Pmod.
  2. 1 point

    Video RAM in DDR

    @Dannny, Hey, for what it's worth you've taught me something about the Mig that I haven't found out for myself yet. I guess that's the utility of having a forum where people can ask questions and get nswers from a variety of perspectives is all about. Everyone can learn things and get a little seed of inquiry implanted into the back of their minds. You never know what can happen.
  3. 1 point

    Video RAM in DDR

    Thanks all of you. I was hoping that I can live without VDMA, but it seems that I have to do it anyway. The main reason for this exercise is to have fun and to learn something new. I found basic blocks for the embedded linux on github or opencores and I already tested some of them. So, I'm getting more and more units to work :-)... But the Video RAM is first "blocker" on the way. I'll look into other examples as well. If any of you have some other ideas, don't hesitate to share them :-)... Thanks.
  4. 1 point

    Video RAM in DDR

    @Ciprian, I understand why there's a desire to stuff Linux into some FPGA designs. In fact you've fleshed out a few of the difficult problems that someone taking the HDL flow must solve on their own quite well for me. @Dannny has discovered one of the other conundrums which is trying to fit an idea into an FPGA platform as opposed to choosing an FPGA platform appropriate to your idea. Sometimes the choice of external memory designed into a board limits comes with unforeseen restrictions. You've also nicely exposed another problem in that even if you can get a non-ZYNQ platform running some form of Linux that doesn't necessarily resolve your problems. Furthermore, using the limited IP available with the MiccroBlaze comes with a problem that only appears after many weeks of work. What if you need your DDR video buffer to work differently or better? Then what? Likely, you have to do all of the stuff that you correctly point out is very hard to do. I don't know what the purpose of the design exercise is. If I had to execute a design that leveraged open source Linux source material I'd certainly want to do it on a ZYNQ platform. But the typical Z7000 family FPGA board is not a wonderful Linux platform if you need performance. Creating a custom Linux build reasonably scaled to the resources of you FPGA platform is not easy. If you are trying to work out how a processor driven DDR video frame buffer might be implemented you will end up knowing a lot more doing it yourself then relying on IP that you don't understand or can't easily modify. There's nothing wrong with slapping together a quick MicroBlaze design using available IP from your FPGA vendor, if learning how to do that flow is the goal or if all you want to do is get to a point where you've accomplished something. Having something that you can adapt to any FPGA platform or project is a different matter. Developing something that you can easily rework or improve is another matter, except that you don't realize it until you've invested a lot of time into getting to the point of having a design that you hope can be a springboard into something better. Hopefully, having some idea of the obstacles that lie ahead will help make for good early design decisions. I know, it's complicated.
  5. 1 point

    Zybo z7 evaluation

    Hi Pier, I'm a bit confused, where do the signals come from? Do you have two external sources or do you generate them in the FPGA? Similarly, do you want to a analog output of the resulting signal or do you only need the samples? -Ciprian
  6. 1 point
    Ana-Maria Balas

    PMOD I2S2 IP

    Yes, I've already give him the link with some Reference projects which contains also pdf files with documentation for each project, and it explains very well the Uart component which is used with the PmodRS232 (in Interface Reference Component from the Reference projects). The info is there... https://reference.digilentinc.com/reference/pmod/pmodrs232/start?&_ga=2.200020910.1057145837.1593523143-180711290.1584371590#reference_projects
  7. 1 point
    Hi all, I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: https://github.com/amb5l/tyto_project I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline. Grateful for any feedback.
  8. 1 point

    Open Logger : Function Gen issue ..

    Hi @Raghunathan, Could you attach a picture of your settings? I was unable to replicate the situation regarding the peak to peak voltage (my screenshot is using 50 Hz, but 60 Hz did the same as well). With regards to the square wave appearing curved, I was only able to see this when I zoomed in so that the time base was at 2 uS/division or less but at that point you are just viewing the output settling time of the requested change which should be about 580 nS as noted on slide 91 on the detailed Microchip Masters Presentation. Thanks, JColvin
  9. 1 point
    Ana-Maria Balas

    pmod AD1 or DA1 digilent

    Hello @farzan, 1. The first critical messages doesn't affect your project. It means that the IP was tested with a project that was created with a different board than yours,but this doesn't have any impact on your project, because it is a generic IP that can be used with all Digilent boards. 2. Because you have errors, then the SDK project cannot be build and therefore you cannot program the FPGA. You have to solve the errors first. The error say that the project you created overflowed the maximum capacity of your allocated BRAM memory with 92408 bytes. This means that you didn't allocate enough internal BRAM memory for the Microblaze processor. You must go back to Vivado project, select the Address Editor tab, then increase the microblaze_0_local_memory for Data and for Instruction to maximum I think 1MB should work. Rerun the generation of bitstream and update the Linker Script (right click on the project name in SDK and Generate Linker Script )
  10. 1 point
    I've got a little update on this project. I managed to get this thing running, by using modified register settings from raspiraw repository on github. So it is definitely possible to use this camera with Zybo Z7-20 board. However I did this with my own MIPI receiver, didn't check compatibility with Xilinx IP-core. Following image is only with white balance correction.
  11. 1 point
    I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: https://github.com/amb5l/tyto_project I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline.
  12. 1 point

    new Nexys Video example designs

    @amb5l, You might want to consider posting this to the Digilent Project Vault, where it belongs. By posting it to where lots of FPGA related questions are posted every day your visibility will disappear making it invisible to most visitors. Just a thought.
  13. 1 point
    Hello @macellan, That's because you've already added one. I can see it under the XADC System monitor.
  14. 1 point

    Microblaze issues for a beginner

    Hi @macellan, Could you attach a picture of your block design? The description of your steps sound correct (and the running connection automation can add some more items depending on when individual pieces of the block diagram was added and when connection automation was run). As for when different pieces were added to the block diagram, it can make a difference, but really only during the Connection Automation and Block Automation when you tell Vivado what sort of connections you would like it to make. Otherwise, the 2018.2 guide should work fine for 2019.1. Thanks, JColvin
  15. 1 point

    Microblaze issues for a beginner

    Hi, >> but I feel like lost in documents Welcome to FPGAs. This is pretty much the name of the game (but it also makes the struggle worthwhile - if it were easy, everybody would do it 🙂 ). As a general direction, a solid (basic) tutorial is good but don't expect to be led by the hand all the way. The constant version changes make this quite difficult (good news: it means there is technological progress ... well at least in theory but the guys from the marketing department said so and they'll surely know ...). More specific directions: Have a look at Microblaze MCS. It's fairly simple - set up the most basic system with some BRAM (=memory "internal" to the FPGA fabric) and one UART. Once you've got that printing "Hello World" - which is mostly a question of baud rates and not mixing Tx/Rx pins, you can add features one by one and the sky is the limit. Well, at least until the little girl next door pulls out her Raspberry Pi, running four cores at 10x the clock frequency - don't complain no one told you: by absolute standards, the performance of any softcore CPU is pathetic, compared to a regular ASIC CPU on the same technology node. So eventually you'll have to move into FPGA territory, or it makes little sense except as a learning exercise.