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Showing content with the highest reputation since 11/13/19 in Posts

  1. 1 point
    asmi

    ARTY-A7-100 MIG Clock & Reset Requirement

    I wonder if there is a single post by @D@n which doesn't include shameless plugs to his projects...😫 Now, directly to OP's questions: Yes you do. This is why "Clocking wizard" IP is being used (it instantiates MCMM internally). No, reference clock (clk_ref_i) is ALWAYS 200 MHz no matter what.It's fed into IDELAYCTRL blocks which control delay elements used inside MIG. You can select it in MIG wizard, but the choice is limited based on your memory's frequency. For DDR3(L) 333 MHz MIG wizard doesn't allow you to select 100 MHz as allowed input frequency due to the way MCMM is used inside MIG, as well some of its' limitations (only single fractional divider per MCMM). Since you always need to feed 200 MHz into MIG no matter what and there is only single clock source on Arty board, you will have no choice but to use MCMM, so you might as well use it to also generate input system clock. sys_rst signal is an active-low asynchronous reset, you can connect it to board's reset signal (again if polarity is right). It isn't required unless your design is supposed to withstand and properly handle system resets. It's used to bring everything to a known initial state so that memory initialization can be performed and functionality is restored if due to some bugs your HW is not working properly. I never actually tried using it, but I think it won't work out-of-box because of clocks needed to be provided - example design assumes they come directly from IO CC pins. But you can modify it to get it to work, and that shouldn't be that difficult. Same goes for status signals tg_compare_error, init_calib_complete - you can connect them to onboard LEDs provided that polarity is right (might need to inverse depending on how LEDs are wired on a board).
  2. 1 point
    zygot

    Advanced topics

    I certainly won't argue against reading the available literature form Xilinx or Intel; tutorials, reference manuals, etc. A problem with diving into "advanced topics" is that it's hard to wrap your mind around everything by trying to absorb complicated information in a vacuum. It certainly doesn't hurt to be familiar with material on timing closure and constraints. Don't just stick with one vendor. I highly advise that you understand how Intel's or maybe even Actel's timing analysis tools work. Getting into trouble, as it were, is pretty easy. Dealing with it is probably easier with a structured approach. So, one idea for a structured approach is to browse the many Application Notes that are available from the vendors. Often they come with design files demonstrating concepts. This might be an easier way to dip your toes into deeper waters without your eyes glazing over. The reality is that simple designs often don't require much attention to timing and placement constraints but complex high clock rate designs often do. Quite a few application demo delve into advanced concepts. The nice things with this path is that you usually get some sort of analysis and explanation of the theory behind ways of dealing with complexity. One easy path to complication is, as has been pointed out above, understanding pipelining to achieve substantially higher data rates for a given design. This will introduce you to timing closure concepts, latency, valid data scope, and other issues quickly, but with specific issues to resolve. First you need to understand the AC switching specifications for your particular device so as to make the project feasible. For real FPGA design situations what takes place beyond the IO pins is critical; but this is no longer FPGA development but digital design. Ideally, one would start with understanding digital design before trying to do FPGA development; but the is no right or wrong path to enlightenment. If you aren't competent at doing high level simulation and writing useful behavioral and RTL testbenches the you aren't ready for the other advanced topics. Well, for now that's my 2 cent contribution. Bon Voyage!
  3. 1 point
    D@n

    Advanced topics

    For CDC, consider these articles on 1) basic CDCs, 2) formally verifying asynchronous designs, and 3) Asynchronous FIFOs. For speed optimizations, you'll need to learn about pipelining. Here's an article on pipeline control. Dan
  4. 1 point
    xc6lx45

    Advanced topics

    one recommendation, but check out whether it works for you: Keshab K. Parhi "VLSI Digital Signal Processing Systems: Design and Implementation" It's a very old (pre-FPGA) book, but it'll be as relevant in 20 years since the theory does not change. You can find a condensed version in the lecture slides. Pick what appears interesting: https://www.win.tue.nl/~wsinmak/Education/2IN35/Parhi/ ------- Reading through the Xilinx documentation might be a good idea. There are those people who read manuals and those who don't. Usually it's easy to tell the difference... I'd skim quickly over parts that don't seem relevant at the moment (which may be 99 %, definitely too much material to read cover-to-cover) and spend time with those parts that seem interesting or immediately relevant. ------------ For a practical example regarding timing, speed optimization, critical path, you can try this simple project: implement a pseudorandom sequence (e.g. 9 or 24 bits) and compare against a same-size number that is an input to the block (not hardcoded, e.g. set by switches). This is a simple AD-converter and you can test with a LED that it works. Then try to run at as high clock speed as you can manage e.g. 300 or 400 MHz. Understand all the warnings, fix those that are relevant (some are not but you should understand why), especially the ones related to inputs ("switches") and outputs ("LED").
  5. 1 point
    BogdanVanca

    Basys 3 HW Target shutdown (Vivado)

    Hi @giamico, This happens when you lose the connection with the Board. Please try on with a different USB cable.
  6. 1 point
    JColvin

    PMODs - Spec 1.2.0

    Hi @andresb, I apologize for the delay. The best way to determine if they are complaint with specification 1.2.0 is by looking at their respect Resource Center (such as the Pmod AD1). On the right-hand side under Electrical, you will see the Specification version that the Pmod is currently compliant with. The Pmod Interface Specification 1.2.0 is available directly here: https://reference.digilentinc.com/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf. Let me know if you have any questions about this. Thanks, JColvin
  7. 1 point
    tom21091

    iic setup failure

    Its sounds to me like a memory issue as well. It looks to me like you are accessing the correct memory location. This isn't a problem with the cache. I think I've had issues with the Smart Connect IP before. Try recreating the block design without the Smart Connect IP. Try running connection automation and unchecking the object (MIG?) that wants to add a SmartConnect IP. -Tommy
  8. 1 point
    I'm glad you worked it out! Best regards, Ana-Maria
  9. 1 point
    Hi @Takashi "The Yaka mein", I apologize for the delay. I am not certain why that particular power supply is not included for the Japan export version of the kit that Xilinx makes. Your guess that it could be a certification issue would make sense, though I do not know this for certain since that particular power supply isn't sold directly on our website as per this forum thread here. I will ask and find out if somebody at Digilent happens to know the reason the power supply would be excluded from the Japan export version, though it may be better to reach out to Xilinx as they are the ones who made that choice for their kit. Thanks, JColvin
  10. 1 point
    OK, I'll try an wrap this up and go on to other things. You'll notice that my "help" has not been in the form of providing code examples, answering your questions directly or providing exactly what it is that you are looking for. Others have done that so you are being pretty well serviced in that regard. What I'd like to do is try and expand your perspective. Intelligence, educational degrees, and even to an extent experience are all nice things to have when trying achieve success in any endeavour. In my experience, attitude, having a structure to your thinking and problem solving efforts, being willing to continually challenge your assumptions and work product are far more important in determining what kind of experiences you'll have in life. This is true whether you are a student waiting to enter professional life or even a seasoned old hand just playing around with a new FPGA board. Believe me I understand the desire for immediate (OK immediate is a relative term ) gratification in seeing your project perform. You'll sustain your interest in FPGA or any other other endeavour far longer by forcing other goals into you thinking. My advice: - Your brain is telling you something when it complains that the tool ( in this case VHDL ) that you're using is confusing and flawed ( this is my interpretation of your comment ). The truth is that no tool is perfect for all tasks, or perfect for any for that matter ) but when multitudes of people use the same tool and achieve success the problem is not likely the tool. Your brain is telling you that perhaps you need to learn how to use your tools. So, I advise you to put off, if you can, getting your project to work until you are comfortable using your tool of choice. This will make your eyes roll... in VHDL integers aren't infinite... in fact the largest integer is a signed 32-bit value. Ouch! But the explicit advice here is to learn to listen to your brain and figure out what it is trying to tell you. That's the best advice I have to offer. - Do read and try to understand well written code, and try to figure out why it is well written code, from experienced people even if the goal of their task is not very interesting. In life the shortest distance between two points is rarely a straight line. Somewhere in the documentation for OCTAVE the authors mention a quote from a book of my youth "How to build a Telescope". I'm paraphrasing here but the quote goes like this: " It takes less time to build a 5" mirror and an 8" mirror than it does to build an 8" mirror". As you probably don't have the book I'll explain. The reference is to the skill involved in hand grinding and polishing a glass bank into a shape suitable for use as an optical mirror that could be used in building a telescope. If you read the book you'll realize that what's involved in ending up with a usable 8" mirror is far more challenging than for a 5" mirror.You'll waste far less time and glass honing your skills and training your brain, hands and eyes trying to achieve what you really want by preparing yourself with a succession of less demanding objectives. This advice works for just about any endeavour.