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  1. 2 points
    Hello Frankly and welcome to our forum. Here are 2 patches that can be applied on top of a Petalinux 2019.1 project to allow reading the OTP MAC and configure it to do so. You can try applying them on 2018.2. Message us back if you have any issues. Cosmin 0001-Z7-20-allow-reading-MAC-address-from-OTP.patch 0002-Z7-20-use-OTP-MAC.patch
  2. 1 point
    xc6lx45

    hard working FPGA...

    1920x1080, 60 FPS, every pixel is recalculated for each new frame. Standard Julia set with 29 iterations limit. 100 % DSP utilization on a CMOD A7 (35); 9e9 multiplications per second in 25 bits still running on USB power if getting a little warm. Probably more to come later ... stay tuned 🙂
  3. 1 point
    hamster

    Bitstream problem with Basys 3

    Seen the problem. You need to define both o1[0] and o1[1] in your constraints, as o1 is a vector of two signals. At the moment you are trying to attach both signals to the same pin, hence the error. Ditto for o2, o3 and o4.
  4. 1 point
    @artvvb Arthur, thanks for the detailed reply. This is the information I needed to move forward. My HDL wrapper is Verilog, which threw me off when I got the error messages about VHDL. In the top level settings the target language is set for Verilog. I'm not aware of another setting somewhere that would affect this. From the example you provided, when the IIC port is made external and the HDL wrapper is updated to account for this, I did not realize before that the IOBUF buffers were instantiated and that the _io signals are then made available to make my pin assignment in my .xdc file. This is the information I needed and I can see how the tristate is being handled. I have tested this by assigning pins on different connectors than the ones pre-defined for I2C and PMOD in the board definition files. After adding the pullup constraints it all works fine and I can now use other available I/O pins.
  5. 1 point
    Ionel

    Zedboard - how to run ramdisk FS in ram

    @m3atwad You can find this option by issuing: petaliux-config Then go to Image Packing Configuration -> Root filesystem type (???????) ---> INITRAMFS.
  6. 1 point
    Hi @spri The drift is cause by the resulting dividers, like: 100e6Hz/30/100Hz ~= 33M333 ~= 30.(00030) Hz 100e6Hz/60/100Hz ~= 16M666 ~= 60.00240 Hz You should use for 30Hz division of 33M332, which will be 2x of 16M666. For other frequencies, the divider to have a low common multiple. You could also set run-length to longest or common multiple period, like for 30/60Hz: dwf.FDwfDigitalOutRunSet(hdwf, c_double(1.0/30)) dwf.FDwfDigitalOutRepeatSet(hdwf, c_int(0))
  7. 1 point
    D@n

    making differential output Clock

    @youngpark, The CmodS7 has only 3.3V I/O banks. You will not be able to generate anything other than 3.3V outputs. I took a quick glance at the schematic and didn't see any length matched GPIO pairs. Depending upon the performance you need, this is often a requirement. You might still be able to break the rules and create two LVCMOS3V3 digital outputs, each opposite each other, to make this happen but it doesn't appear as though the board was designed to support such a requirement. If you choose to do that, then let me recommend you use two ODDR primitives, each with opposite polarity, to try to make this work. That'll at least help you get the timing right. Dan
  8. 1 point
    Hi @tip.can19, The CYINIT pin appears to be an initialization bit, presumably to have the IP block to prepare itself for incoming data. It looks like this Xilinx thread addresses this in more detail. Thanks, JColvin
  9. 1 point
    D@n

    making differential output Clock

    @youngpark, Can you share what board you are using? Some boards are voltage agile, some are not. You are also posting in the MicroController section, usually reserved for PIC based boards, and getting FPGA answers. Was this your intent? Dan
  10. 1 point
    Hi @Lesiastas The simple captures can be performed in a few millisecond. With the default device configuration of Analog Discovery you have 4096 samples / digital channel. With the 4th configuration you have 16384 sample / channel. See the examples in the WF SDK, like DigitalIn_Spi_Spy.py: #dwf.FDwfDeviceOpen(c_int(-1), byref(hdwf)) # device configuration of index 3 (4th) for Analog Discovery has 16kS digital-in buffer dwf.FDwfDeviceConfigOpen(c_int(-1), c_int(3), byref(hdwf)) For repeated captures you don't have to rearm the instrument. The new capture is automatically started after the data is fetched from the device. This, to improve the capture rate. dwf.FDwfDigitalInConfigure(hdwf, c_bool(False), c_bool(True)) for iTrigger in range(100): # new acquisition is started automatically after done state while True: dwf.FDwfDigitalInStatus(hdwf, c_int(1), byref(sts)) if sts.value == DwfStateDone.value : break dwf.FDwfDigitalInStatusData(hdwf, rgwSamples, 2*cSamples)
  11. 1 point
    Hi @V94, If you are just trying to run the Embedded Vision Demo to confirm it works, all you need to do is copy the BOOT.bin file (located in the bin folder of the Embedded Vision Demo source files that are linked within the PDF you attached) onto a microSD card. If you are wanting to view the project files, you would need to open up Xilinx SDK 2017.4 (opening Vivado 2017.4 is only necessary if you want to make changes to the block design), choose the Workspace location (I choose the sdk folder within the Embedded Vision Demo folder), and then go to File -> Import -> General -> Existing Projects into Workspace, and then click Next. The first radio button option where it says "Select root directory" will have a Browse button; click Browse and select the same sdk folder within the Embedded Vision Demo folder. 5 checked projects should appear in the white box area consisting of the fsbl, fsbl_bsp, pcam_vdma_hdmi, pcam_vdma_hdmi_bsp, and the system_wrapper_hw_platform_0. If all 5 of those are checked, go ahead and click Finish. You will then be able to see the source code and make changes to the project from there. Let me know if you have any questions. Thanks, JColvin
  12. 1 point
    Ciprian

    making differential output Clock

    Hi @youngpark, Well I don't know for sure why its not working for you but I would recommend a different approach. The most important thing for you is to make sure that the clock gets propagated throug the design using the clock path and this is done using an ODDR primitive. Therefore I suggest using this aproch: The clock forwarder can be found on our github in the vivado-library. You will also have to constrain it. For this please take a look in the ug903 provided by Xilinx specifically starting page 31. Good Luck -Ciprian
  13. 1 point
    juliosilva

    4 analog Channel.

    Hello, I have an AD2 that I love. Sometimes I need 4 analog channels... if I buy other AD2 can I have 4 channels in the scope? I think not and I need to open 2 apps, if so is there a way that I can get the graph of both and join then on only 1 and take measurements after acquisition? Or is best to buy a 4ch scope? In this case what is the suggestions around the same price of AD2? Thanks!
  14. 1 point
    Hello @shantaramj, The IP has it's own constraints and set-ups that would fail if you reset them in a different Vivado Version. Please use the recommended version of Vivado for this project, go trough syntesys, implementation and generate bitstream. If everything works as expected you can open the project in 2018.2, but please make sure that you don't reset the output products for this ip. If you need although to go trough a reset, please lock the ip before doing that. Best Regards, Bogdan Vanca
  15. 1 point
    I receive and process serial data in this hack: http://hamsterworks.co.nz/mediawiki/index.php/PmodMAXSONAR It looks for an R character, then takes numeric ('0' to '9' ) that appear after that.
  16. 1 point
    I think that you could use Zybo Z7 with Pcam 5C and Pmod WiFi. Here are some useful projects which you can modify them and adapt them to your needs : Zybo Z7 -20 Pcam 5C Demo : https://github.com/Digilent/Zybo-Z7-20-pcam-5c Pmod Wi-FI IP and some exemples : https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodWIFI_v1_0
  17. 1 point
    D@n

    Genesys 2 SD card slot

    @DanK, I've been using this code for working with SD Cards recently. So far, I've been successful reading and writing files. While I've used the reset, and while I start the design with the SD card in reset, I'm not quite certain that it actually resets the card like it's supposed to. I had some test failures along the way to getting this working that suggest that the reset didn't truly pull power from the card as well as removing the card from the board did. Dan
  18. 1 point
    Physically, nothing is different. It was a labeling thing when the chipKIT logo was removed.
  19. 1 point
    Hi @Devendra Pundir Can you try removing U82 from your PCB and see if that solves the problem? 30pF is a lot of added capacitance for the USB data lines and is likely what's causing the issue. Thanks, Michael
  20. 1 point
    attila

    Analog Discovery 2 stopped working

    Hi @DanielF The auxiliary supply of the AD2 has under/over-voltage protection. The USB 2.0 port voltage should be around 5V. Higher voltages, above 6.5V could damage the device. Defective HUBs or using unregulated/defective supplies for this could output higher voltages killing the USB devices. In the following posts you can find troubleshooting tips:
  21. 1 point
    It is possible to mux PL pins to ZYNQ PS peripherals. You can, for instance use one PS UART connected to the MIO pins as normal and connect a second PS UART to PL IO pins. For a two pin UART interface this pretty easy to do. For an Ethernet interface not so easy. It sounds to me as if what you want to do is leverage your ZYNQ platform into something that let's you experiment with Verilog designs. You can certainly start with the board design flow to experiment with exchanging data between the PS and PL Verilog code. Simply adding GPIO ports that connect to PMODs would be a place to start. Later you can experiment with using BRAM or you own IP. Personally, I find that having Vivado create a toplevel HDL source that I control works best; but I'm pretty comfortable with HDL design. In my case I create my own HDL toplevel design source and instantiate the board design HDL code. This make connecting HDL code to open ports and pins straight-forward. If you can afford it I strongly urge you to consider buying a cheap non-ARM based FPGA development board to learn Verilog development. It's just a lot less complicated. There are a number of options for nice <$100 FPGA boards, though the best one's for the money might not be Xilinx based. Once you figure out how to implement something in HDL that you can interact with using , say a UART, then try an integrate your HDL into the ZYNQ platform. There is HDL code projects on other areas of the Digilent forums to play with to help get started. A UART is the easiest interface for debugging or connecting an HDL design to PC applications. For <$10 a good 3.3V TTL USB UART breakout module or cable is indespensibe. It is also possible to tie off the PS and just use your board as an FPGA platform; this is not something that I'd recommend. In the end you should choose the best strategy for you. Just don't be afraid to ditch a processor based design because it seems daunting. Before you are ready to implement a 6502 soft processor with peripherals in logic you should be comfortable implementing, simulating, and debugging "peripherals" in the HDL of your choice. At least that's the view from where I sit.
  22. 1 point
    Hello, First, As you may think you have to write your own UART vhdl/verilog module, with an RS323 interface. After you make sure that it works correctly, you have to add to your code and axi lite interface. There are two ways for doing that: 1. You add it by your own, and keep your code as a module. 2. Package your module as an custom ip and use the template given by Xilinx. Personally, I will probably go with the second option. And that is because, the template is clearly written and commented. Inside this template there is a state machine that gives you access to a couple of registers.Trough these registers you can pass data from PL to PS side. After you have your own IP, you can add it into a block design and connect it trough the AXI Interconnect. On this stage your IP will have it's own address into the address editor. With that, you can access trough the lite interface each individual register. Best Regards, Bogdan Vanca
  23. 1 point
    asmi

    ARTY-A7-100 MIG Clock & Reset Requirement

    I wonder if there is a single post by @D@n which doesn't include shameless plugs to his projects...😫 Now, directly to OP's questions: Yes you do. This is why "Clocking wizard" IP is being used (it instantiates MCMM internally). No, reference clock (clk_ref_i) is ALWAYS 200 MHz no matter what.It's fed into IDELAYCTRL blocks which control delay elements used inside MIG. You can select it in MIG wizard, but the choice is limited based on your memory's frequency. For DDR3(L) 333 MHz MIG wizard doesn't allow you to select 100 MHz as allowed input frequency due to the way MCMM is used inside MIG, as well some of its' limitations (only single fractional divider per MCMM). Since you always need to feed 200 MHz into MIG no matter what and there is only single clock source on Arty board, you will have no choice but to use MCMM, so you might as well use it to also generate input system clock. sys_rst signal is an active-low asynchronous reset, you can connect it to board's reset signal (again if polarity is right). It isn't required unless your design is supposed to withstand and properly handle system resets. It's used to bring everything to a known initial state so that memory initialization can be performed and functionality is restored if due to some bugs your HW is not working properly. I never actually tried using it, but I think it won't work out-of-box because of clocks needed to be provided - example design assumes they come directly from IO CC pins. But you can modify it to get it to work, and that shouldn't be that difficult. Same goes for status signals tg_compare_error, init_calib_complete - you can connect them to onboard LEDs provided that polarity is right (might need to inverse depending on how LEDs are wired on a board).
  24. 1 point
    JColvin

    MPLab Chipkit Import Issues

    Hi @D4ILYD0SE, I haven't used this importer before (Digilent works with their own Digilent Core now), but I tested nearly the same setup (exception is that I have MPLAB X 3.60 rather than a newer version, all other pieces the same version as you), but encountered the same error. The way that project is copied to a different location so that can be imported seems strange to me since I would expect that it needs more information to import, but that is what the tutorial states, so I followed it. My guess now is that either the newer chipKIT Cores are no longer compatible with the importer tool that has a 2017 date (perhaps unlikely based on my limited knowledge of how cores are designed, but I don't know this for certain) or the Arduino IDE had something changed. If I get a successful import on one of these older revisions, I'll let you know. Thanks, JColvin
  25. 1 point
    zygot

    Advanced topics

    I certainly won't argue against reading the available literature form Xilinx or Intel; tutorials, reference manuals, etc. A problem with diving into "advanced topics" is that it's hard to wrap your mind around everything by trying to absorb complicated information in a vacuum. It certainly doesn't hurt to be familiar with material on timing closure and constraints. Don't just stick with one vendor. I highly advise that you understand how Intel's or maybe even Actel's timing analysis tools work. Getting into trouble, as it were, is pretty easy. Dealing with it is probably easier with a structured approach. So, one idea for a structured approach is to browse the many Application Notes that are available from the vendors. Often they come with design files demonstrating concepts. This might be an easier way to dip your toes into deeper waters without your eyes glazing over. The reality is that simple designs often don't require much attention to timing and placement constraints but complex high clock rate designs often do. Quite a few application demo delve into advanced concepts. The nice things with this path is that you usually get some sort of analysis and explanation of the theory behind ways of dealing with complexity. One easy path to complication is, as has been pointed out above, understanding pipelining to achieve substantially higher data rates for a given design. This will introduce you to timing closure concepts, latency, valid data scope, and other issues quickly, but with specific issues to resolve. First you need to understand the AC switching specifications for your particular device so as to make the project feasible. For real FPGA design situations what takes place beyond the IO pins is critical; but this is no longer FPGA development but digital design. Ideally, one would start with understanding digital design before trying to do FPGA development; but the is no right or wrong path to enlightenment. If you aren't competent at doing high level simulation and writing useful behavioral and RTL testbenches the you aren't ready for the other advanced topics. Well, for now that's my 2 cent contribution. Bon Voyage!
  26. 1 point
    D@n

    Advanced topics

    For CDC, consider these articles on 1) basic CDCs, 2) formally verifying asynchronous designs, and 3) Asynchronous FIFOs. For speed optimizations, you'll need to learn about pipelining. Here's an article on pipeline control. Dan
  27. 1 point
    xc6lx45

    Advanced topics

    one recommendation, but check out whether it works for you: Keshab K. Parhi "VLSI Digital Signal Processing Systems: Design and Implementation" It's a very old (pre-FPGA) book, but it'll be as relevant in 20 years since the theory does not change. You can find a condensed version in the lecture slides. Pick what appears interesting: https://www.win.tue.nl/~wsinmak/Education/2IN35/Parhi/ ------- Reading through the Xilinx documentation might be a good idea. There are those people who read manuals and those who don't. Usually it's easy to tell the difference... I'd skim quickly over parts that don't seem relevant at the moment (which may be 99 %, definitely too much material to read cover-to-cover) and spend time with those parts that seem interesting or immediately relevant. ------------ For a practical example regarding timing, speed optimization, critical path, you can try this simple project: implement a pseudorandom sequence (e.g. 9 or 24 bits) and compare against a same-size number that is an input to the block (not hardcoded, e.g. set by switches). This is a simple AD-converter and you can test with a LED that it works. Then try to run at as high clock speed as you can manage e.g. 300 or 400 MHz. Understand all the warnings, fix those that are relevant (some are not but you should understand why), especially the ones related to inputs ("switches") and outputs ("LED").
  28. 1 point
    BogdanVanca

    Basys 3 HW Target shutdown (Vivado)

    Hi @giamico, This happens when you lose the connection with the Board. Please try on with a different USB cable.
  29. 1 point
    JColvin

    PMODs - Spec 1.2.0

    Hi @andresb, I apologize for the delay. The best way to determine if they are complaint with specification 1.2.0 is by looking at their respect Resource Center (such as the Pmod AD1). On the right-hand side under Electrical, you will see the Specification version that the Pmod is currently compliant with. The Pmod Interface Specification 1.2.0 is available directly here: https://reference.digilentinc.com/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf. Let me know if you have any questions about this. Thanks, JColvin
  30. 1 point
    tom21091

    iic setup failure

    Its sounds to me like a memory issue as well. It looks to me like you are accessing the correct memory location. This isn't a problem with the cache. I think I've had issues with the Smart Connect IP before. Try recreating the block design without the Smart Connect IP. Try running connection automation and unchecking the object (MIG?) that wants to add a SmartConnect IP. -Tommy
  31. 1 point
    Hi @vinodcxlv You have functions to read data from binary and text file, see the examples and Help tab. The Script tool supports JSON if you want to use it, but it does not apply settings from such data.
  32. 1 point
    I'm glad you worked it out! Best regards, Ana-Maria
  33. 1 point
    Hi @Lesiastas Public Shared Function AD2_RecordStart(ByVal hdwf As Integer, ByVal fReconfigure As Integer, ByVal fStart As Integer, ByVal fReadData As Integer, ByRef sts As Byte, ByVal cSamples As Integer, ByVal cBuffer As Integer, ByRef cAvailable As Integer, ByRef cLost As Integer, ByRef cCorrupted As Integer, ByRef rgData() As Byte) As Integer 'Record Parameters ReDim rgData(cSamples) Dim fOverflow As Boolean : fOverflow = False Dim iSample As Integer : iSample = 0 Dim cIdle as Integer = 0 Dim nIdle as Integer = 3*100 ''''' 100 bit long idle If cSamples > cBuffer Then ' record While iSample < cSamples If FDwfDigitalInStatus(hdwf, fReadData, sts) = 0 Then Return 0 End If If sts = DwfStateDone Or sts = DwfStateTriggered Then FDwfDigitalInStatusRecord(hdwf, cAvailable, cLost, cCorrupted) If cLost <> 0 Or cCorrupted <> 0 Then fOverflow = True End If cAvailable = Math.Min(cAvailable, cSamples - iSample) Dim rgTemp(cAvailable) As Byte ' in other programming languages use pass pointer to rgData[iSample] FDwfDigitalInStatusData(hdwf, rgTemp, 1 * cAvailable) For i = 0 To cAvailable - 1 rgData(iSample) = rgTemp(i) iSample = iSample + 1 If (rgTemp(i) & 3) = 3 cIdle += 1 Else cIdle = 0 End If Next If cIdle > nIdle Exit While End If End If If sts = DwfStateDone Then Exit While End If End While Else While True If FDwfDigitalInStatus(hdwf, 1, sts) = 0 Then Return 0 End If If sts = DwfStateDone Then Exit While End If End While iSample = rgData.Length FDwfDigitalInStatusData(hdwf, rgData, 1 * rgData.Length) End If End Function
  34. 1 point
    Arty7_Lover

    Vitis HW Platform in Arty7-20

    Thanks, a lot. Your kind and easy answer is greatly helpful to me.
  35. 1 point
    artvvb

    Vitis HW Platform in Arty7-20

    Hi @Arty7_Lover Unfortunately the Arty Z7 does not yet officially support Vitis. That said, you can still use the Arty Z7 with Vivado 2019.2 and Vitis. The workflow for creating a basic embedded application has not changed much from previous version of Vivado with Xilinx SDK, described here. In order to create a application project, you must have a hardware specification (.xsa file) that targets the board. This hardware specification is exported from a Vivado project (File > Export > Export Hardware). I have attached both a project and specification for the Arty Z7-20 to this post. The project only uses the GPIOs and Zynq preset from our board files. Once you have a specification, you can launch Vitis. In the new application project dialog in the image you posted, if you click on the + button at the top left, you can choose a custom specification for your project. This can be any XSA file that supports the Arty Z7-20, whether you are using mine, or exported your own. If you keep clicking next through the dialog, you are able to choose an application template. This works the same as it did in Xilinx SDK. I have attached a zipped Vitis workspace with a hardware platform and a slightly modified Hello World application. The Arty can then be programmed from Vitis through the Xilinx > Program FPGA dialog, provided that the XSA included a bitstream. The application can be run by right clicking on the system project or application project and clicking Run As > Launch on Hardware. I hope that this provided a decent starting point. Thanks, Arthur vitis_export_archive.ide.zip arty_z7_20_base.xsa Arty-Z7-20-Base.xpr.zip
  36. 1 point
    Hi @sgrobler, I think it's entirely possible to include a timestamp in a log header when starting a session from a connected host. I'll put this on my list of additions & fixes, put some thought into a proper solution and get to work on it. I'll personally message you once I've made the changes (and you'll probably see a blog post about them as well). Regards, AndrewHolzer
  37. 1 point
    Hi @Takashi "The Yaka mein", I apologize for the delay. I am not certain why that particular power supply is not included for the Japan export version of the kit that Xilinx makes. Your guess that it could be a certification issue would make sense, though I do not know this for certain since that particular power supply isn't sold directly on our website as per this forum thread here. I will ask and find out if somebody at Digilent happens to know the reason the power supply would be excluded from the Japan export version, though it may be better to reach out to Xilinx as they are the ones who made that choice for their kit. Thanks, JColvin
  38. 1 point
    I reproduced the problem somehow. You need to make sure that you follow the exact steps as they are described in the tutorial: 1. Connect your PC to your Nexys 4 DDR using an Ethernet cable. 2. Make sure you set the static TCP/IPv4 address "192.168.1.XX” for your PC, where XX is a value between 2 and 255, but not 10. This is important because the board and the PC has to be in the same network , so that's why you set "192.168.1" which is the Network Identifier. The XX is the Host Identifier. Below is a screenshot of the connection through serial port and what it displays when you run the application. 3. Connect to Tera Term using the board IP : 192.168.1.10. You need to open a new connection and set 192.168.1.10, Telnet, TCP port 7. Cheers, Ana-Maria
  39. 1 point
    Hi @Asha Devi, Thank you for sharing the source and the screenshot. The errors you are seeing say that there are multiple definitions of the ComposeHTMLGetALS function. That is happening because you are including HTMLGetals.cpp in deWebIOServerSrc.cpp. You can fix this by removing #include "./HTMLGetals.cpp" and writing a ComposeHTMLGetALS function declaration in deWebIOServerSrc.cpp or (better yet) a HTMLGetals.h header file that gets included into deWebIOServerSrc.cpp. AndrewHolzer
  40. 1 point
    OK, I'll try an wrap this up and go on to other things. You'll notice that my "help" has not been in the form of providing code examples, answering your questions directly or providing exactly what it is that you are looking for. Others have done that so you are being pretty well serviced in that regard. What I'd like to do is try and expand your perspective. Intelligence, educational degrees, and even to an extent experience are all nice things to have when trying achieve success in any endeavour. In my experience, attitude, having a structure to your thinking and problem solving efforts, being willing to continually challenge your assumptions and work product are far more important in determining what kind of experiences you'll have in life. This is true whether you are a student waiting to enter professional life or even a seasoned old hand just playing around with a new FPGA board. Believe me I understand the desire for immediate (OK immediate is a relative term ) gratification in seeing your project perform. You'll sustain your interest in FPGA or any other other endeavour far longer by forcing other goals into you thinking. My advice: - Your brain is telling you something when it complains that the tool ( in this case VHDL ) that you're using is confusing and flawed ( this is my interpretation of your comment ). The truth is that no tool is perfect for all tasks, or perfect for any for that matter ) but when multitudes of people use the same tool and achieve success the problem is not likely the tool. Your brain is telling you that perhaps you need to learn how to use your tools. So, I advise you to put off, if you can, getting your project to work until you are comfortable using your tool of choice. This will make your eyes roll... in VHDL integers aren't infinite... in fact the largest integer is a signed 32-bit value. Ouch! But the explicit advice here is to learn to listen to your brain and figure out what it is trying to tell you. That's the best advice I have to offer. - Do read and try to understand well written code, and try to figure out why it is well written code, from experienced people even if the goal of their task is not very interesting. In life the shortest distance between two points is rarely a straight line. Somewhere in the documentation for OCTAVE the authors mention a quote from a book of my youth "How to build a Telescope". I'm paraphrasing here but the quote goes like this: " It takes less time to build a 5" mirror and an 8" mirror than it does to build an 8" mirror". As you probably don't have the book I'll explain. The reference is to the skill involved in hand grinding and polishing a glass bank into a shape suitable for use as an optical mirror that could be used in building a telescope. If you read the book you'll realize that what's involved in ending up with a usable 8" mirror is far more challenging than for a 5" mirror.You'll waste far less time and glass honing your skills and training your brain, hands and eyes trying to achieve what you really want by preparing yourself with a succession of less demanding objectives. This advice works for just about any endeavour.