Popular Content

Showing content with the highest reputation since 10/22/19 in all areas

  1. 2 points
    Hello @Bryan_S, Here is a demo project for Cmod S6 from https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/start. I looked into the source files and there is clk_gen_50MHz.vhd. You can see in the top.vhd file how the clk_gen_50MHz is instantiated and used. I don't know what is the clk16x in your code, but here are some source files for serial port serialport_v3.zip The sources are for Nexys4 DDR which has a 100 MHz system clock. But in your case, if you use the clk_gen_50MHz, you'll have a 50 MHz clock instead of 100 MHz, 9600 baud rate, as shown in the UART_RX_CTRL.vhd file. The same for UART_TX_CTRL.vhd. I don't know if you'll use the sources from above, but I hope it helps. Best regards, Ana-Maria Balas
  2. 2 points
    Hello @bitslip, Things are a little bit more complicated. Indeed, for changing the resolution you have to rewrite some registers. But you also need to make sure that the Video Trimming controller ip generates the required constants for you resolution. I wouldn't recommend to write all the needed registers from the control interface (it would be agonising) Instead I would go with the existent logic for changing the resolution, which is adding a new structure with all the register values. As an example, you can check the OV5640.H file. I much simple and quicker solution would be to use our video scaller ip. This ip was written in HLS and it was used in the fmc pcam adapter demo for re-scalling the video at a 640x480 resolution. You can check the design in here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-fmc-pcam-adapter-demo/start Best Regards, Bogdan Vanca
  3. 1 point

    ARTY-A7-100 MIG Clock & Reset Requirement

    I wonder if there is a single post by @D@n which doesn't include shameless plugs to his projects...😫 Now, directly to OP's questions: Yes you do. This is why "Clocking wizard" IP is being used (it instantiates MCMM internally). No, reference clock (clk_ref_i) is ALWAYS 200 MHz no matter what.It's fed into IDELAYCTRL blocks which control delay elements used inside MIG. You can select it in MIG wizard, but the choice is limited based on your memory's frequency. For DDR3(L) 333 MHz MIG wizard doesn't allow you to select 100 MHz as allowed input frequency due to the way MCMM is used inside MIG, as well some of its' limitations (only single fractional divider per MCMM). Since you always need to feed 200 MHz into MIG no matter what and there is only single clock source on Arty board, you will have no choice but to use MCMM, so you might as well use it to also generate input system clock. sys_rst signal is an active-low asynchronous reset, you can connect it to board's reset signal (again if polarity is right). It isn't required unless your design is supposed to withstand and properly handle system resets. It's used to bring everything to a known initial state so that memory initialization can be performed and functionality is restored if due to some bugs your HW is not working properly. I never actually tried using it, but I think it won't work out-of-box because of clocks needed to be provided - example design assumes they come directly from IO CC pins. But you can modify it to get it to work, and that shouldn't be that difficult. Same goes for status signals tg_compare_error, init_calib_complete - you can connect them to onboard LEDs provided that polarity is right (might need to inverse depending on how LEDs are wired on a board).
  4. 1 point

    Advanced topics

    I certainly won't argue against reading the available literature form Xilinx or Intel; tutorials, reference manuals, etc. A problem with diving into "advanced topics" is that it's hard to wrap your mind around everything by trying to absorb complicated information in a vacuum. It certainly doesn't hurt to be familiar with material on timing closure and constraints. Don't just stick with one vendor. I highly advise that you understand how Intel's or maybe even Actel's timing analysis tools work. Getting into trouble, as it were, is pretty easy. Dealing with it is probably easier with a structured approach. So, one idea for a structured approach is to browse the many Application Notes that are available from the vendors. Often they come with design files demonstrating concepts. This might be an easier way to dip your toes into deeper waters without your eyes glazing over. The reality is that simple designs often don't require much attention to timing and placement constraints but complex high clock rate designs often do. Quite a few application demo delve into advanced concepts. The nice things with this path is that you usually get some sort of analysis and explanation of the theory behind ways of dealing with complexity. One easy path to complication is, as has been pointed out above, understanding pipelining to achieve substantially higher data rates for a given design. This will introduce you to timing closure concepts, latency, valid data scope, and other issues quickly, but with specific issues to resolve. First you need to understand the AC switching specifications for your particular device so as to make the project feasible. For real FPGA design situations what takes place beyond the IO pins is critical; but this is no longer FPGA development but digital design. Ideally, one would start with understanding digital design before trying to do FPGA development; but the is no right or wrong path to enlightenment. If you aren't competent at doing high level simulation and writing useful behavioral and RTL testbenches the you aren't ready for the other advanced topics. Well, for now that's my 2 cent contribution. Bon Voyage!
  5. 1 point

    Advanced topics

    For CDC, consider these articles on 1) basic CDCs, 2) formally verifying asynchronous designs, and 3) Asynchronous FIFOs. For speed optimizations, you'll need to learn about pipelining. Here's an article on pipeline control. Dan
  6. 1 point

    Advanced topics

    one recommendation, but check out whether it works for you: Keshab K. Parhi "VLSI Digital Signal Processing Systems: Design and Implementation" It's a very old (pre-FPGA) book, but it'll be as relevant in 20 years since the theory does not change. You can find a condensed version in the lecture slides. Pick what appears interesting: https://www.win.tue.nl/~wsinmak/Education/2IN35/Parhi/ ------- Reading through the Xilinx documentation might be a good idea. There are those people who read manuals and those who don't. Usually it's easy to tell the difference... I'd skim quickly over parts that don't seem relevant at the moment (which may be 99 %, definitely too much material to read cover-to-cover) and spend time with those parts that seem interesting or immediately relevant. ------------ For a practical example regarding timing, speed optimization, critical path, you can try this simple project: implement a pseudorandom sequence (e.g. 9 or 24 bits) and compare against a same-size number that is an input to the block (not hardcoded, e.g. set by switches). This is a simple AD-converter and you can test with a LED that it works. Then try to run at as high clock speed as you can manage e.g. 300 or 400 MHz. Understand all the warnings, fix those that are relevant (some are not but you should understand why), especially the ones related to inputs ("switches") and outputs ("LED").
  7. 1 point

    PMODs - Spec 1.2.0

    Hi @andresb, I apologize for the delay. The best way to determine if they are complaint with specification 1.2.0 is by looking at their respect Resource Center (such as the Pmod AD1). On the right-hand side under Electrical, you will see the Specification version that the Pmod is currently compliant with. The Pmod Interface Specification 1.2.0 is available directly here: https://reference.digilentinc.com/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf. Let me know if you have any questions about this. Thanks, JColvin
  8. 1 point

    iic setup failure

    Its sounds to me like a memory issue as well. It looks to me like you are accessing the correct memory location. This isn't a problem with the cache. I think I've had issues with the Smart Connect IP before. Try recreating the block design without the Smart Connect IP. Try running connection automation and unchecking the object (MIG?) that wants to add a SmartConnect IP. -Tommy
  9. 1 point
    Hi @vinodcxlv You have functions to read data from binary and text file, see the examples and Help tab. The Script tool supports JSON if you want to use it, but it does not apply settings from such data.
  10. 1 point

    Vitis HW Platform in Arty7-20

    Hi @Arty7_Lover Unfortunately the Arty Z7 does not yet officially support Vitis. That said, you can still use the Arty Z7 with Vivado 2019.2 and Vitis. The workflow for creating a basic embedded application has not changed much from previous version of Vivado with Xilinx SDK, described here. In order to create a application project, you must have a hardware specification (.xsa file) that targets the board. This hardware specification is exported from a Vivado project (File > Export > Export Hardware). I have attached both a project and specification for the Arty Z7-20 to this post. The project only uses the GPIOs and Zynq preset from our board files. Once you have a specification, you can launch Vitis. In the new application project dialog in the image you posted, if you click on the + button at the top left, you can choose a custom specification for your project. This can be any XSA file that supports the Arty Z7-20, whether you are using mine, or exported your own. If you keep clicking next through the dialog, you are able to choose an application template. This works the same as it did in Xilinx SDK. I have attached a zipped Vitis workspace with a hardware platform and a slightly modified Hello World application. The Arty can then be programmed from Vitis through the Xilinx > Program FPGA dialog, provided that the XSA included a bitstream. The application can be run by right clicking on the system project or application project and clicking Run As > Launch on Hardware. I hope that this provided a decent starting point. Thanks, Arthur vitis_export_archive.ide.zip arty_z7_20_base.xsa Arty-Z7-20-Base.xpr.zip
  11. 1 point
    Hey All, We recently posted a new version of WaveForms Live which ads some new features. This blog post lists all the changes in the update.
  12. 1 point
    Hi @sgrobler, I think it's entirely possible to include a timestamp in a log header when starting a session from a connected host. I'll put this on my list of additions & fixes, put some thought into a proper solution and get to work on it. I'll personally message you once I've made the changes (and you'll probably see a blog post about them as well). Regards, AndrewHolzer
  13. 1 point
    Hi @Bryan_S, We don't have the necessary resources to investigate/correct the code of your project. However the source code I provided to you above, is readable and you can test it with your project. Just integrate the clk_gen_50MHz.vhd and UART_RX_CTRL.vhd files to your project. I think those files are all you need. Cheers, Ana-Maria
  14. 1 point
    Sometimes people mistakenly try to create a derived baud rate clock that closely matches the baud rate. UARTs should be able to accommodate a significant variation of baud rate error, perhaps 15% or so. So a better way to think of it, particularly on the receive side is creating lots of samples and keeping data transitions near the middle of a baud's worth of sample units. This means that clocking the UART entity at a high clock rate, providing a lot of samples per baud period, will be optimal. A 50 MHz clock for 115200 baud is fine but I've been using a 100 MHz clock for 921600 baud that's reliable. Don't think or hope... simulate, simulate.. and simulate some more. The first thing that I'd do if made custodian for someone else's code would be to simulate everything until I understood it. Reading source text often not sufficient and commentary is rarely accurate. There are a number of UART based projects in the Digilent Project Vault, some with testbench HDL tha might be helpful.
  15. 1 point
    You are welcome, we are happy that the flash is programmed. Unfortunately this project seems to be marked as having internal use. And maybe this is the reason you get so many problems, as the documentation is not detailed enough.
  16. 1 point
    Hello, Since you mentioned that you successfully built the mcs file you can choose an alternate way to program the flash. Instead of using the SDK (the recommended way in the mentioned readme), let's use Vivado. Please open Vivado, do not open a project. In the the welcome screen please open Tasks/Hardware manager. Then Open Target / Autoconnect, you should see your FPGA in the Hardware tree. Right click on FPGA, select "Add Configuration Memory device ...". Select s25fl128sxxxxxx0-spi-x1_x2_x4. Then right click on the flash device you just added in the Hardware tree, select "Program Configuration Memory Device ..." and select your mcs file to be programmed. Please note that the board used for this caption uses a different FPGA. On the other hand, if you want to address the errors you mentioned in your previous post, most probably you lack the (HDL) top wrapper. Please right click on system.bd, select "Create HDL wrapper ..." and then rebuild. Good luck.
  17. 1 point
    Hi @sgrobler, I am able to successfully connect to my phones WiFi hotspot on firmware 1.3.0. I get the same message pop-up as you regarding the firmware update required, but I click the "OK" option and then select the Instrument Panel where-upon am I greeted with the same message, choose OK again, and then I am brought to the Instrument Panel where I am able to successfully run the OpenLogger. I do agree though that the pop-up message should not be occurring though. I have reached to @AndrewHolzer to help address this. Thank you for the feedback, JColvin
  18. 1 point

    Problems with PetaLinux for Zybo Z7-10

    1) https://github.com/Digilent/Petalinux-Zybo-Z7-10 2) Download the BSP and decompress it. BOOT.BIN and image.ub are in pre-built/linux/images
  19. 1 point
    I've seen similar issues in the forum, but no real solution. I have 5 CMOD A7 boards and only 2 of them behave properly. The other 3 do not accept a program and sometimes disconnect. I get the following errors; ERROR: [Labtools 27-3165] End of startup status: LOW ERROR: [Common 17-39] 'program_hw_devices' failed due to earlier errors. I have tried: - many different USB cables - Different ports on the PC - Powered USB hubs - Vivado Lab 2017.2 and 2018.1 - 2 different bitstream files The boards that work, always works. No matter the cable or USB ports. Anything else I should try?
  20. 1 point

    Can Arty Z7 handle 4k60p hdmi?

    Hi @greengun, No, the transceiver pins on the Arty A7 FPGA (a XC7A35TICSG324-1L FPGA) are no broken out. As per Xilinx UG475 (page 41), the HR I/O bank 16 is only partially bonded out, but as per the Arty A7 schematic, the HR I/O pins on bank 16 are not used. Thanks, JColvin
  21. 1 point
    Hi @Lesiastas As initialization when you application starts, before calling open set the following option to 0/Run: dwf.FDwfParamSet(DwfParamOnClose, c_int(0)) # 0 = run, 1 = stop, 2 = shutdown 2 - open always takes 'long' time (~300ms) since the device is powered down on close and reprogrammed on each opening 1 - device remains powered but the outputs are stopped on close, this takes a few ms on open/close * 0 - device continues the output after close (waveform, pattern generation, supplies), the open/close are fast * *The first open after power up will take 'long' time since the device needs to be programmed.
  22. 1 point

    Questions about waveform generator

    Hi @CyLab I'm not sure what sequence of functions are you using to configure the analog-out (Wavegen). Normally after calling any set functions the device gets configured 'automatically'. You can disable this option to configure the device only when calling FDwfAnalogOutConfigure, after all the settings are set. This option applies to all the instruments, analog/digital-out/in/io dwf.FDwfDeviceAutoConfigureSet(hdwf, c_int(0)) # 0 = the device will be configured only when calling FDwf###Configure dwf.FDwfAnalogOutNodeEnableSet(hdwf, channel, AnalogOutNodeCarrier, c_bool(True)) dwf.FDwfAnalogOutNodeFunctionSet(hdwf, channel, AnalogOutNodeCarrier, funcSine) dwf.FDwfAnalogOutNodeFrequencySet(hdwf, channel, AnalogOutNodeCarrier, c_double(1000)) dwf.FDwfAnalogOutNodeAmplitudeSet(hdwf, channel, AnalogOutNodeCarrier, c_double(1.41)) dwf.FDwfAnalogOutNodeOffsetSet(hdwf, channel, AnalogOutNodeCarrier, c_double(1.41)) .... dwf.FDwfAnalogOutConfigure(hdwf, channel, c_int(1)) # 0 stop, 1 start, 3 configure and continue running in case it is running
  23. 1 point
    Hello @bitslip, Yes, you are correct. Theoretically you can rescale the image at any size, even at 1000x1. I'm saying theoretically because I never tried it, not because I think it's not possible. The sensor doesn't have any kind of constraints that could stop you to do that. Or, at least I couldn't find any into the datasheet. The VDMA has to have a fix number of bytes for each individual transfer. So, if you are playing with the number of bytes, you have to reinitialize the function above for each transfer, as it was done in the DEMO.
  24. 1 point
    Hi @sgrobler, Thank you for posting about the issues you are having with WaveForms Live. I am currently doing some further work on the OpenLogger and WaveForms Live and will gladly fit investigating them into task list. I'll also take a look at the single character scaling issue you posted about. Keep an eye on this thread for an update. AndrewHolzer
  25. 1 point
    Hi @P. Fiery The latest WF beta version lets you access the instrument windows. https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ Scope.window.toggleFFT() // open or close ... or ... if('fft' in Scope.window){ // close if open Scope.window.fft.close() }else{ Scope.window.toggleFFT() }
  26. 1 point
    @bitslip To answer your questions. 1. Yes. You can can output any image size that is described into the sensor datasheet. This can be done on the fly if you reprogram the right registers. Part of this is already achieved by the demo project. The change resolution option from the user interface reprograms the sensor for each resolution. For more info you can dig into the fallowing function: pipeline_mode_change(vdma_driver, cam, vid, Resolution::R1280_720_60_PP, OV5640_cfg::mode_t::MODE_720P_1280_720_60fps); The OV5640_cfg namespace has 3 different modes for each individual resolution. Each mode is correspondent to a structure that stores all the registers values needed for that resolution. To be more specific, all the registers that are responsible for image windowing (0x3800 to 0x3807), are configured in these structures. Let's take for example the cfg_1080p_15fps_ structure. If you want to calculate the output X size, you would have 2287(0x3804, 0x3805 registers) - 336(0x3800, 0x3801) - 16(0x3810, 0x3811) which is equal with 1919. The registers 0x3808 and 0x3809 are configured for 1920, so the image is basically un-scaled. For image windowing you have to rewrite those registers. 2. Yes and No. It depends on how many resolution do you want to add. Unfortunately I cannot give you a number, because I'm not sure how versatile is the current design. For now it works for 3 different resolution, but is hard to tell how many you could add on. Each individual resolution may have a different pixel clock, or as I said before, a different set of image constants. For now, I would probably start to understand how to configure the above registers, and I would start playing with them. You also need to make sure, that the vdma transfer works as expected. As you may see, the pipeline_mode_change function reconfigure the vdma_driver object for each resolution.
  27. 1 point
    Hopefully. when Digilent spins the next CMOD they will provide a better arrangement for using the configuration circuitry with an external power supply. Even as a standalone module configured from flash 1 Vcc pin and one GND pin is less than ideal, and likely problematic if the FPGA is driving or receiving a number of single-ended signals.
  28. 1 point
    Hi @svet-am, This solution works just for the Digilent boards. Please contact Xilinx for support in order to fix your KCU1500 board. Best regards, Bianca
  29. 1 point

    Software to Get started

    @Robert R Hi. Welcome to the world of FPGAs. First you will need to install Vivado i order create a design that contains a MicroBlaze system. You will want the free WEB edition because you don't need a licence for the FPGA on your board. The SDK will be installed unless you choose not to but you will choose to install it because that's the application that allows you to develop you C applications for your design. Once the tools are installed you need to start using the Document Navigator to download tutorials, user guides and other relevant information. You'll have a hard time of it if you don't understand what an FPGA consists of and how to use Vivado tools.
  30. 1 point
    That's alright; I'm glad you were able to get it working!
  31. 1 point
    Hi @yildizberat, What version of Vivado are you using and what monitor resolution do you have? I used the 2018.2 release available here: https://github.com/Digilent/Zybo-Z7-10-Pmod-VGA/releases successfully. I did end up regenerating the bitstream to get it to work successfully though. Thanks, JColvin
  32. 1 point

    Pmod RS485 size

    Hi @Takashi "The Yaka mein", We have a 3D model of the Pmod RS485 available in it's Resource Center on the right hand side under Documentation. Let me know if you have any questions. Thanks, JColvin
  33. 1 point
    Thanks for reporting. There was a problem with the project. We updated the project and the instructions in the README. Just run the following commands: git clone https://github.com/Digilent/Petalinux-Arty-S7-50.git cd Petalinux-Arty-S7-50/Arty-S7-50/ git submodule update --init petalinux-config petalinux-build
  34. 1 point
    Hi @satvik, I believe you can get all of the functionality from the WebPACK version of Vivado (most of us here at Digilent use the WebPACK for most of the work we do). There may be some IPs that require an external license that is not included with WebPACK (or the Design or System edition) versions of Vivado, such as more complex Ethernet or USB IPs from Xilinx. But you would be able to implement a Pmod WiFi with the Cora board; we have an example using the Pmod WiFi with a different Digilent board here as well as a thread on it here and here. Thanks, JColvin
  35. 1 point
    Hi @Lesiastas In case you don't need prefill/pretrigger, in the 'Config' set the trigger position to zero.
  36. 1 point

    PmodKYPD and PmodOLED for Zynq

    Dear Ana-Maria, Thank you so much. I already found all three links you mentioned right before you reply to me. Yes, they really help me to how to start. The sample codes were long, but worked. I'm trying to write a main code. I really appreciate your great help. You're awesome!! Thanks again.
  37. 1 point
    Hello @justeen, I see that you used the Pmod IP's from the vivado-library. Each IP you added to your block design comes with a demo. In the vivado-library folder, corresponding to your Pmod IP, you will find the example sources. Here are the demo sources for Pmod Oled and here are the demo sources for Pmod KYPD. You can look into the example sources for both of the Pmods and adapt them to your project. At step 11. Create a New Application Project in SDK from the tutorial explains how to create a project in SDK when using Digilent Pmod IPs. Cheers, Ana-Maria
  38. 1 point
    Hi @satvik, I apologize for the delay. The reason the Cora Z7-07s is not present in Vivado 2015.4 and 2016.1 is because Xilinx had not added those parts to their software. From what I know, the XC7Z007S chip (the SoC present on the Cora board) was not added to the Vivado WebPACK version until 2016.3. Otherwise, if you are looking to follow Digilent made examples for the Cora Z7-07s, I would recommend using Vivado 2017.4 or 2018.2 as those are the versions of Vivado that we have made examples for the Cora Z7, which you can find in the Cora Z7's Resource Center. Thanks, JColvin
  39. 1 point

    dynamic phase configuration on arty s7

    @ekazemi What frequency rates are you trying to achieve? This method will get you user-controlled phase to within about 1ns or so, and it works nicely for sending something off-chip. But to your question, I have yet to try the dynamic interface of any clock management hard-cores. I've looked them over a couple of times, but ... not actually tried any. Dan
  40. 1 point
    @johnsan1 I'm not sure w/ regards to tera term, but there are some other options. Assuming you aren't running up against the baud rate as a speed limit, you could add a Xilinx AXI Timer/Counter IP to your block design, that could be used to fairly precisely time how long your code takes to execute. The time values captured from the counter, either raw or formatted however you want could then be printed over serial, along with your data. Adding in extra bytes to the serial transfers would slow the system down, but you could either increase the data density of the transfers by reducing the number of bytes (stripping out the leading "Pin V" substring for example), or try to increase the baud rate, or something else. -Arthur
  41. 1 point

    Using tera term for two pmods

    Hello, Sorry this is a bit late, but yeah this is basically what I did and it worked. Thank you so much!!
  42. 1 point

    Offline Installer

    I've been thinking that we've not been talking about the same things for a while now. In order to use your CMOD you need Vivado to create the configuration bitstreams. The last time I downloaded Vivado it was a file north of 40 GB. Yes, Gigabytes. Xilinx also supplies much smaller installers that require an internet connection in order to install Vivado on you PC. Digilent supplies tools for standalone configuration of the FPGA using bitstream that you create. Also, their tools can supplement Vivado to allow Vivado Hardware Manager to use the Digilent configuration facilities. Digilent also has software development tools and APIs for compiling your own software applications using various interfaces found on their FPGA boards. These files are all reasonably small. Trying to do FPGA development in a room or building without any internet access is going to be difficult without full support from the IT people maintaining your network and computing resources.
  43. 1 point
    Hi @Phil_D You can use the RangeSet function to select the gain and the RangeGet function to get the calibrated value, full swing. All the Set/Get function in the API behave like this. Normally it is not recommended to go with full swing input signal since clipping can occur. Like when the scale top is 5.561V and the input signal reaches 5.562V dwf.FDwfAnalogInChannelEnableSet(hdwf, c_int(-1), c_bool(True)) dwf.FDwfAnalogInChannelRangeSet(hdwf, c_int(-1), c_double(5.0)) dwf.FDwfAnalogInConfigure(hdwf, c_int(1), c_int(1)) range1 = c_double() range2 = c_double() offset1 = c_double() offset2 = c_double() dwf.FDwfAnalogInChannelRangeGet(hdwf, c_int(0), byref(range1)) dwf.FDwfAnalogInChannelRangeGet(hdwf, c_int(1), byref(range2)) dwf.FDwfAnalogInChannelOffsetGet(hdwf, c_int(0), byref(offset1)) dwf.FDwfAnalogInChannelOffsetGet(hdwf, c_int(1), byref(offset2)) print("Scope 1 Range: "+str(range1.value)+"V Offset: "+str(offset1.value)+"V") print("Scope 2 Range: "+str(range2.value)+"V Offset: "+str(offset2.value)+"V") # on my AD2 the actual ranges are the following: # Scope 1 Range: 5.560701917732086V Offset: -2.4933249474501373e-06V # Scope 2 Range: 5.558373268176409V Offset: 0.00021560932083742462V
  44. 1 point
    Hi @P. Fiery The 'replace all' can be undone easily with Ctrl+Z. The 'all files' would require undo in each file, so I have added confirmation for this. Thank you again for your feedback.
  45. 1 point
    Hi all, Quick update here. I've got binaries built for Mac and Linux (Ubuntu) and have updated the documentation to link to them. You may also download the Windows, Mac or Linux binaries by following the links I just gave you. If you encounter any issues whatsoever, submit in issue on the GitHub page and I'll set to fixing them straight away. Regards, AndrewHolzer
  46. 1 point

    Using tera term for two pmods

    Hi @johnsan1 As there is only one UART link between the PC and your board, you cannot use more than one instance of Tera Term. I am assuming you have a Vivado block design containing two Pmod AD2 IP cores. The provided SDK example code only configures and reads from one AD2. In order to view samples from both AD2's at the same time, you must edit the example code to configure and control both AD2s and print data from both out over the serial interface. A starting point would be to add a second device driver instance to the code by editing line 44 of the example code as follows: PmodAD2 myDevice_JA, myDevice_JD; Thanks, Arthur
  47. 1 point

    pipeline granularity

    >>thus i have a tendency to over-pipeline my design read the warnings. If a DSP48 has pipeline registers it cannot utilize, it will complain. Similar for BRAM - it needs to absorb some levels of registers to reach nominal performance. I'd check the timing report. At 100 MHz you are are maybe at 25..30 % of the nominal DSP performance of an Artix, but I wouldn't aim much higher without good reason (200 MHz may still be realistic but the task gets much harder). A typical number I'd expect could be four cycles for a multiplication in a loop (e.g. IIR). Try to predict resource usage - if FFs are abundant, I'd make that "4" an "8" to leave some margin for register rebalancing: An "optimal" design will become problematic in P&R when utilization goes up (but obviously, FF count is only a small fraction of BRAM bits so I wouldn't overdo it)
  48. 1 point
    Hi @AvnetRH, I haven't ever worked with this particular power supply so I do not know if this is true, but there is a possibility that the Xilinx Development boards may refer to development boards that Digilent sells (such as the Arty). After getting some more information from our sales team (since the part is not directly available on our website), it seems you will need to email our sales team, sales at digilentinc dot com, to be able to request that specific power supply. Thank you, JColvin
  49. 1 point

    Embedded Linux Question Disclaimer

    Hello! Welcome to the Digilent Forums! All of us here, both Digilent Staff and our incredible community members, are excited to be able to help you out with your project. That being said, we are not the ultimate experts on Embedded Linux. A couple of us have a decent amount of experience, but unfortunately we cannot guarantee that we can identify the issue and have the solution to your problem for your exact distro, drivers, board, and application. We will try to help out the best that we can, but it may take some additional time to provide feedback on any questions that you may have. Thanks, The Digilent Team
  50. 1 point
    OK, I'll try an wrap this up and go on to other things. You'll notice that my "help" has not been in the form of providing code examples, answering your questions directly or providing exactly what it is that you are looking for. Others have done that so you are being pretty well serviced in that regard. What I'd like to do is try and expand your perspective. Intelligence, educational degrees, and even to an extent experience are all nice things to have when trying achieve success in any endeavour. In my experience, attitude, having a structure to your thinking and problem solving efforts, being willing to continually challenge your assumptions and work product are far more important in determining what kind of experiences you'll have in life. This is true whether you are a student waiting to enter professional life or even a seasoned old hand just playing around with a new FPGA board. Believe me I understand the desire for immediate (OK immediate is a relative term ) gratification in seeing your project perform. You'll sustain your interest in FPGA or any other other endeavour far longer by forcing other goals into you thinking. My advice: - Your brain is telling you something when it complains that the tool ( in this case VHDL ) that you're using is confusing and flawed ( this is my interpretation of your comment ). The truth is that no tool is perfect for all tasks, or perfect for any for that matter ) but when multitudes of people use the same tool and achieve success the problem is not likely the tool. Your brain is telling you that perhaps you need to learn how to use your tools. So, I advise you to put off, if you can, getting your project to work until you are comfortable using your tool of choice. This will make your eyes roll... in VHDL integers aren't infinite... in fact the largest integer is a signed 32-bit value. Ouch! But the explicit advice here is to learn to listen to your brain and figure out what it is trying to tell you. That's the best advice I have to offer. - Do read and try to understand well written code, and try to figure out why it is well written code, from experienced people even if the goal of their task is not very interesting. In life the shortest distance between two points is rarely a straight line. Somewhere in the documentation for OCTAVE the authors mention a quote from a book of my youth "How to build a Telescope". I'm paraphrasing here but the quote goes like this: " It takes less time to build a 5" mirror and an 8" mirror than it does to build an 8" mirror". As you probably don't have the book I'll explain. The reference is to the skill involved in hand grinding and polishing a glass bank into a shape suitable for use as an optical mirror that could be used in building a telescope. If you read the book you'll realize that what's involved in ending up with a usable 8" mirror is far more challenging than for a 5" mirror.You'll waste far less time and glass honing your skills and training your brain, hands and eyes trying to achieve what you really want by preparing yourself with a succession of less demanding objectives. This advice works for just about any endeavour.