Leaderboard


Popular Content

Showing content with the highest reputation since 09/17/19 in all areas

  1. 3 points
    Ana-Maria Balas

    MTDS PMOD Connection issue

    Hello @WillTx, 1. There is an IP for Pmod MTDS with the drivers you need to make your Pmod MTDS working. It also contains 10 demos from which you can learn a lot. You can find it here : https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodMTDS_v1_0. You need to download the entire vivado-library (from here) then follow the tutorial for using Pmod IP cores in Vivado. 2. Your block design after adding the Pmod MTDS IP: 3. You can use the board flow to automatically connect to JB Pmod connector without a XDC constrain file (as it shows in the tutorial at step 3). You need to install the board files first. If you want to use the Cora-Z7-07S-Master.xdc constraint file, below are the lines corresponding to JB Pmod connector : 4. Please follow the REAME.txt found in drivers/PmodMTDS_v1_0/examples/ Cheers, Ana-Maria
  2. 2 points
    Hi @attila Thank you again for all the support you've provided me for the past weeks. I am now capable of receiving more than 409 characters using the Wrapper I created base from your example. It uses the Record acquisition mode and I set the buffer size to 3 million for now. I'll increase it when the need arises. I used 1 UART controller and branched out its Tx pin to 2 DIO pins of the AD2 (DIO #0 & 1). I transmitted 500 characters: (If Record mode is not the acquisition mode, the received result will be blank) For DIO # 0, it received: with a length of: For DIO #1, it received: with a length of: I could not have done it without your guidance, thank you again and more power to you and Digilent Best regards, Lesiastas
  3. 2 points
    Yes, that cable is suitable from connection perspective. Still, there are functionality issues that you must be concerned. Most of the Pmods communicate using protocols like SPI, I2C, etc. This is specified on the Pmod datasheet. This means that the pins corresponding on the maching connector (on the system board) must implement that specific functionality. Normally using a FPGA board will be easier to configure Pmod pins to the needed functionality. Still, as you use a microcontroller board, this might be more difficult or even impossible. Please check if the pins associated to the Pmod rows correspond with the associated function on the Pmod. Another possibility is to re-configure the pins if your microcontroller allows pins reconfiguration. Please check (in the board schematic) which microcontroller pins are connected to the Pmod connector, and then check (in the microcontroller datasheet) the functions for these pins. Good luck.
  4. 1 point
    D@n

    Verilog Simulator

    @xc6lx45, This is a valid question, and a common response I get when recommending Verilator. Let's examine a couple of points here. Verilog is a very large language, consisting of both synthesizable and non-synthesizable subsets. I've seen more than one student get these two subsets mixed up, using constructs like "always @* clk <= #4 !clk;" and struggling to figure out why their design either doesn't work or fails to synthesize. I've seen a lot of student/beginners try to use these non-synthesizable constructs to generate "programs" rather than "designs". Things like "if (reset) for(k=0; k<MEMSIZE; k=k+1) mem[k] = 0;", or "always @(*) sum = 0; @(posedge clk) if (A[0]) sum = B; @(posedge clk) if (A[1]) sum = sum + (B<<1)", etc. Since verilator doesn't support #delay's, nor does it support 'x values, in many ways it does a better job matching what the synthesizer and the hardware will do together, leaving less room for confusion. C++ Verilator based wrappers can be used just as easily as Verilog for bench testing components. That said, ... The Verilog simulation language is a fairly poor scripting language for finding bugs in a module when compared to formal methods. There's been more than once that I've been deceived into thinking my design works, only to find a couple cases (or twenty) once I get to hardware where it didn't work. Indeed, both Xilinx and Intel messed up their AXI demonstration designs--designs that passed simulation but not a formal verification check. As a result, many individuals have posted unsolved bugs on the forums, complained about design quality, etc. (Xilinx has been deleting posts that aren't flattering to their methodology. I'm not yet sure about Intel in this regard) Formal methods tend not to have this problem. Why waste a student's time teaching a broken design methodology? So, if you aren't using Verilog for your bench test, then what other simulation based testing do you need? Integration testing where all the modules come together to interact with the hardware in some (potentially) very complex ways. At this point, you need hardware emulation, and Verilator provides a much better environment for integrating C/C++ hardware emulators into your design. My favorite example of this is building a VGA. VGA's are classically debugged using a scope and a probe since the definition of "working" tends to be "what my monitor will accept." The problem with this is that you lose access to all of the internal signals when abandoning your simulation environment. On one project I was working on, this one for the Basys3 where there was a paucity of memory for a video framebuffer, I chose to use the flash and to place prior compressed frames onto the flash. I would then decompress these frames on the fly as they were being displayed. My struggle was then how to debug decompression failures, since I could only "see" them when the design ran from hardware. Verilator fixes this, by allowing you to integrate a display emulator with your design making it easier to find where in the VCD/trace output file the bug lies. Another example would be a flash simulation. Most of my designs include a 16MB flash emulation as part of their simulation. This allows me to debug flash interactions in a way that I doubt you could using iverilog. This allows me to simulate things like reading from flash, erasing and programming flash--even before I ever get to actual hardware, or perhaps after I've taken my design to hardware and then discovered a nasty bug. More than once is the time where I've found a bug after reading through all 16MB of flash memory, or in the middle of programming and something doesn't read back properly. I'm not sure how I would do debug this with iverilog. A third example would be SD-card simulation. I'm currently working with a Nexys Video design with an integrated SD card. It's not a challenge to create a 32GB FAT based image on my hard drive and then serve sectors from it to my running Verilator simulation, but I'm not sure how I would do this from iverilog. So far in this project, I've been able to demonstrate an ability to read a file from the SD card--FAT system and all, and my next step will be writing data files to it via the FATFS library. I find this to be an important simulation requirement, something provided by Verilator and quite valuable. Finally, I tend to interact with many of my designs over the serial port. I find it valuable to interact with the simulation in (roughly) the same way as with hardware, and so I use a program to forward the serial port over a TCP/IP link. I can do the same from Verilator (try that with iverilog), and so all of the programs that interact with my designs can do so in the same fashion regardless of whether the design is running in simulation or in hardware. Yes, there are downsides to using Verilator. It doesn't support non-synthesizable parts of the language. This is the price you pay for getting access to the fastest simulator on the market--even beating out the various commercial simulators out there. Verilator is an open source simulator, and so it doesn't have the encryption keys necessary to run encrypted designs--such as the Vivado's FFT or even the FIFO generator that's a core component of their S2MM, MM2S, and their interconnect ... and probably quite a few other components as well. This is one of the reasons why I've written alternative, open source designs to many of these common components. [FFT, S2MM, MM2S, AXI interconect, etc.] As to which components are "better", it's a mixed bag--but that's another longer story for another day. Verilator does not support sub-clock timing simulations, although it can support multi-clock simulations. At the same time, most students don't need to know the details of sub-clock timing in their first course. (I'm not referring to clock-domain crossing issues here, since those are rarely simulated properly anyway.) Still, I find Verilator to be quite a valuable choice and one I highly recommend learning early on in the learning process. This is the reason why my beginners Verilog tutorial centers around using both Verilator and SymbiYosys. Dan
  5. 1 point
    Hi @P. Fiery Thank you for the observations.
  6. 1 point
    xc6lx45

    Verilog Simulator

    As a 2nd opinion, I would not recommend Verilator to learn the language. It does work on Windows (MSYS) but I'd ask for a good reason why you need Verilator in the first place instead of a conventional simulator. Have a look at iverilog / gtkwave: http://iverilog.icarus.com/ It works fine from standard Windows (no need to create a virtual machine). You'd call it through the command line though (hint: create a .bat file with the simulation commands to keep them together with the project. Hint, the abovementioned MSYS environment is pretty good for this, e.g. use a makefile or shell script).
  7. 1 point
    D@n

    Verilog Simulator

    @Ahmed Alfadhel, Don't put spaces between the "-" and "Wall", or between the "-" and the "cc" and you'll do better, Dan
  8. 1 point
    D@n

    Verilog Simulator

    @Ahmed Alfadhel, I put instructions together for that some time ago. Let me know if they need to be updated any. Dan
  9. 1 point
    attila

    Scope, Script and StaticIO

    var usw = Scope1.Channel1.measure("NegWidth")*1e6 rgusw.push(round(usw*100)/100) sumusw += usw ccw++ } var avgusw = round(sumusw/ccw*100)/100
  10. 1 point
    Hi @milliars I'm not sure if I understand your question correctly. You could use a reference channel (uncheck Lock time under Ref 1 gear button) and a math channel, like this: To measure the phase between two input signals use custom global measurement: The Network Analyzer phase provides a better phase measurement:
  11. 1 point
    You'll definitely have to order CAN PHY devices unloess you find a board with a PHY already connected to the FPGA.
  12. 1 point
    Hi @P. Fiery In the last WF beta you can have multiple files with separate functionality or you can use as includes (File / New File): https://forum.digilentinc.com/topic/8908-waveforms-beta-download/
  13. 1 point
    zygot

    Verilog

    I haven't bought a textbook for quite a few years now so I don't have any suggestions. There are a lot of levels to learning an HDL. One is the language syntax and basic concepts of timing, concurrency and other aspects of simulating a model. Then there is the usage of languages like VHDL and Verilog for synthesis. Both are central aspects of designing logic in programmable devices. I can't emphasize enough how important learning basic digital design concepts is to developing competency in FPGA design regardless of your source preferences. I doubt that there is a good text that covers all of these facets. Unless there is a University nearby finding a place to browse though books to see if they might be worth the investment is a difficult proposition these days. I know that @D@nloves verilator. He's the only one concentrating on programmable logic design that I know of who uses it. Be aware that it is a cycle based simulator. These tend to be a lot faster than regular logic simulators and certainly have a place. Don't be afraid of the simulator tools widely used in industry where products are programmable logic based. The native Vivado simulator and ModelSim provided by Intel are preferred simulation tools for programmable logic. These are time based simulations that can simulate in units of picoseconds if that's warranted. They also use compiled libraries that understand the vendors device architecture. Best of all they can do post route timing simulations. Learn how to write good testbenches that work with the vendors simulators. Part of the design process is being able to conceptualize real world device behavior; the less idealistic the more complete your design process and logic will be.
  14. 1 point
    D@n

    Verilog

    @Ahmed Alfadhel, Perhaps the most complete tutorial out there is asic-world's tutorial. You might also find it the most vacuous, since although it tells you all the details of the language it doesn't really give you the practice or the tools to move forward from there. There's also a litexsoc (IIRC) by enjoy-digital that I've heard about, but never looked into An alternative might be my own tutorial. Admittedly, it's only a beginner's tutorial. It'll only get you from blinky to a serial port with an attached FIFO. That said, it does go over a lot of FPGA Verilog design practice and principles. It also integrates learning how to use a simulator, in this case Verilator, and a formal verification tool, such as SymbiYosys, into your design process so that you can start learning how to build designs that work the first time they meet hardware. I'm also in the process of working to prepare an intermediate tutorial. For now, if you are interested, you'd need to find most of the information that would be in such a tutorial on my blog. (It's not all there ... yet, although there are articles on how to create AXI peripherals ..) Feel free to check it out. Let me know what you think, Dan
  15. 1 point
    Hi @Zed_Guy, The ZedBoard XDC file is available on out GitHub here: https://github.com/Digilent/digilent-xdc/ I looked in your document and I saw that they changed the name of the ports in the XDC to match with their projects. You can either use in the project, the names used in the XDC or change in the XDC the names according to your project. By the fact that they are using "my_constraints.xdc" implies that they created a XDC file specific for the project in the guide, and probably used just what they needed. Normally, where you found the project and the guide, you should've been able to find the that XDC because it is not a generic Rev D XDC. The pins marked in the document with red, are linked to the first 4 pins in the JA pmod connector. You can find them in the official XDC. You have two choices. Contact Avnet and ask for that project specific XDC, or take the XDC from us and change it according to your project. Best regards, Bianca
  16. 1 point
    tgvho

    JTAG-SMT3-NC UART usage

    I'm concidering adding a JTAG-SMT3-NC to my next design so I can have access to both the UART and the JTAG interface. Hoever, it is not clear how to use the UART. I've read over the ADAPT2 API and the SMT3 documentation pages, but it's not very clear to me. So, What drivers are needed? Does the device enumerate itself as a serial device so that it can be used with standard OS serial device utilities (I'm guessing a virtual com port driver)? How does one set the baud rate? For example, if I want to use this as a data dump debugger at the megabuad rate, how would I go about enumerating the serial device?
  17. 1 point
    Hi @P. Fiery The Views can't be opened/closed from Script. The FFT.Window refers to data windowing. You could have 2 Scopes opened, one with and the other one without fft, and control them from Script as Scope1 and Scope2.
  18. 1 point
    Writing to confirm that there are indeed timing errors in the reference project that will take some time to fix. There is an XDC in dvi2rgb that is getting synthesized by mistake (lost property during an update) and the locked signal not being synchronous to PixelClk as the reset module is expecting.
  19. 1 point
    FYI, Attila is on vacation returning on Oct. 9th.
  20. 1 point
    Support confirmed that the platform does not currently support changing the default sorting, but I've added a feature request to them.
  21. 1 point
    Hi @jfranz-argo, @kharoonian, and @Franky32, I apologize for the delay. I have sent each of you a PM about this. Thanks, JColvin P.S. to other readers, be sure not have Digilent boards attached when you are reprogramming other FTDI devices. A long list of users will tell you it's an easy mistake to accidentally select the wrong device.
  22. 1 point
    Ana-Maria Balas

    MTDS PMOD Connection issue

    In my block design I didn't used the board flow, I made external the output pin of the IP , and then I used that name to constrain the JB Pmod pins in the Cora-Z7-07S-Master.xdc constraint file(as you can see in the picture below the bd) . You have two choices: 1. You can name the Pmod's IP output anyway you want, but then you'll have to constrain the Pmod pins in the xdc file as I did in my block design 2. You can use the board flow as suggested in the tutorial, and you don't use the xdc file. "jb" is the name of the Pmod connector, as it is supposed to be, you cannot change it. When you connect it from the board tab, it means that the output of the Pmod IP will be constrained automatically to the right pin connector( named "jb") of your board, and this way you don't have to constrain those pins manually. Those warnings won't affect your project, it means that the Pmod MTDS IP was packed with a different board when it was created. Just add the Zynq, add the Pmod MTDS using board flow, leave the "jb" as it is, ignore the warnings related to different board value of the Pmod MTDS IP, make sure you validated your design, create HDL Wrapper and generate bitstream. Then follow the rest of the steps from the tutorial. Cheers, Ana-Maria
  23. 1 point
    Hi all, Quick update here. I've got binaries built for Mac and Linux (Ubuntu) and have updated the documentation to link to them. You may also download the Windows, Mac or Linux binaries by following the links I just gave you. If you encounter any issues whatsoever, submit in issue on the GitHub page and I'll set to fixing them straight away. Regards, AndrewHolzer
  24. 1 point
    None of our products are intended for or tested for extreme temperatures. All parts are usually commercial and not industrial grade. Our products are intended for use in a laboratory setting and if you need environmental testing, you will have to conduct it. Regarding your classification, the 70 °C ambient temperature seems to be extreme.
  25. 1 point
    Re-read my previous post. Your initial question is why bad assumptions will get you bad advice. You assume that length matching traces implies something that it doesn't. Read ahead... @D@nhas offered a good hint to your question. This quote is from my earlier post to this thread. I hate repeating myself but I realize that finding answers already covered by such questions isn't easy on this forum. High speed LVDS used in ADC device interfaces are only supported by IO Banks with Vcco of 2.5V or lower. Digilent has a number of FPGA boards with FMC connectors whose signals are connected to Vadj. Vadj is user selectable on most FPGA boards with FMC connectors that I'm aware of. Even if you choose a board with an FMC connector with IO Banks powered by Vadj = 1.8V, 2.5V or some other voltage compatible with Series7 LVDS IOSTADNARDs that doesn't mean that any ADC mezzanine board with and ADC will work with it. There are restrictions for clocking options using Series7 SERDES options. I have investigated using the Nexys Video, Genesys2 and KC705 boards with various ADC EVMs involving multi-lane LVDS interfaces. I haven't found any EVMs that work with any of those FPGA boards due to clock pin assignments. Connector choice is very important. Opal Kelly has a few boards with their SYZYGY specification ports that are properly designed for mixed LVDS and single-ended interfaces. If you want to interface an LVDS device to your FPGA you need to read and understand the Series7 Select IO and Clocking reference manuals as a starting point. You need to examine the schematics for any potential FPGA board platform. Opal Kelly offers one 25 MHz dual ADC POD. I'm unaware of inexpensive ADC add-on boards for Xilinx otherwise. You can always design your own ADC FMC mezzanine card but be careful in assigning signals. If all your clocks and data are on the same IO Bank then you have a chance. LVDS interfaces where the data runs at a rate > 8x the clock rate have additional restrictions to observe and likely you need 2 clocks. I'm not happy to say this but if you want to do ADC or DAC conversion at rates of 100 MHZ or higher things the Intel HSMC world is where to look. If money is no object than there are military grade options in the Xilinx world but I doubt that you get much support. The most important advice is to be aware of the rules for high speed LVDS in your FPGA device and synthesize and route a preliminary design with pin assignments before making a purchase. If you know what your are doing it isn't hard to design an interface or layout a board that won't work. If you don't know what you are doing you don't have much chance of success. There are multi-channel ADCs in the 250 MHz range with parallel DDR interfaces which are a whole lot easier to work with. Much of what I've mentioned here were previously mentioned in a few threads in the Technical Based Off-Topic Discussion forum. You can search the Digilent Forums for posts relating to particular topics. Lastly, you just aren't going to find a cheap FPGA board that let's you implement a state of the art high speed interfaces.
  26. 1 point
    @ManserDimor, You'll need something that is voltage agile if you want to do LVDS. Most of the I/O on Digilent boards is fixed at 3.3V, so check your reference manual and your schematic to make sure that you can use the voltages available to you. Dan
  27. 1 point
    Hey Paolo, I'm glad you found my videos helpful! I've been working on other projects, but if you have any other ideas for videos that you would find helpful let me know. Kaitlyn
  28. 1 point
    @Takemasa Tamanuki If you intend to use the the CMDO A7 as a standalone component you need to carefully read the reference manual and schematic. This module is meant to be powered by the same USB connector that provides JTAG configuration and UART communications. It has a FLASH device capable of configuring the FPGA and a power input pin so it is entirely possible to use the module without USB connectivity. When I develop an interface using a standard like SPI I don't write HDL that supports all of the possible modes that might exist in every device. I design a minimal interface that supports a particular device. I'm sure that there is good IP for SPI masters out there but I've never used one so I have no suggestions. If you can do Verilog or VHDL development and understand how the SPI devices that you are working with operate it is a rather easy and straight forward effort. I advise against expecting that adding an FPGA board with generic "code" could be an easy and quick solution to any existing problem.
  29. 1 point
    @ManserDimor Here's a general rule of thumb. Differential traces, whether laid out as differential or not must be length matched as best as possible. High speed bussed signals are usually length matched but normally this isn't nearly as critical as differential signalling; and this is usually done with a maximum data rate in mind. Everything else is usually assigned to the auto-router. Hand tuning traces is expensive and time consuming and usually there are a limited number that can be optimised with high ball count FPGA footprints. Usually, the focus is on external memory like DDR. If you need IO pins that are length matched then choose a board that makes it clear how well this was done. If the board vendor doesn't mention length matching then it was unlikely to have been done. Most of Digilent's boards with "high-speed" "differential" PMODS mention length matching in the reference manual. Some vendors offer a trace routing report of lengths for certain connectors. If differential signal traces are routed as true differential pairs then using them as single-ended signals might be problematic from a cross-coupling standpoint, especially if you don't take this into account. The only 3.3V differential IOSTANDARD supported by Series7 devices is TMDS and this is best done when the termination is as close to the receiver as possible. All of this does not necessarily mean that you can't design around a board's shortcomings to achieve some level of performance using a logic that the board wasn't designed for. This is one reason why all (most???) Series7 devices offer input delay management and in some cases output delay management features. There are boards from a few vendors with length matched GPIO on connectors are usually designed for high-speed. 2.56x2.56 mm connectors aren't that. Not many board vendors are going to go to the expense of designing a high performance board that they intend to sell at a cheap price. Final comment. If you are going to connect an external board or device to your FPGA board connector then you must assume the digital logic designer role required to do so.
  30. 1 point
    JColvin

    UART echo code in vhdl

    Hi @Vishnuk, This sounds a bit like a class project, so while I won't be just providing the code, I can try to answer specific questions that you may have. In the mean time, I would recommend taking a look at this thread where the user worked through receiving signals from a UART input to modify the LEDs present on the Basys 3. A quick internet search also brought up a VHDL UART echo project, though it was designed for a different board and probably different UART settings than you want. Thanks, JColvin
  31. 1 point
    You can start with the following tutorials: http://www.ni.com/tutorial/14871/en/ https://reference.digilentinc.com/learn/programmable-logic/tutorials/program_fpgas_through_multisim/start
  32. 1 point
    Hi @cfatt7 Yes, you can use the FDwfAnalogOutConfigure(..., -1, ...) to start channels synchronized. You can also use the FDwfAnalogOutMasterSet to specify the master channel, then starting master channel will also start the slave channels. This is important in case you are using external triggering or cross-triggering with other instruments. Specifying a finite run length is useful to keep different frequencies phase aligned, using the minimum frequency or greatest common divisor. Like 1kHz might be generate as 0.9999999kHz and 2kHz as 2.000000001kHz, which could shift slowly over time. In this case use 1ms (1/1kHz) run time. FDwfAnalogOutRunSet(..., ..., 1.0/min_freq); FDwfAnalogOutRepeatSet(..., ..., 0); See the WF SDK/ samples/ py/ AnalogOut_Sync.py examples
  33. 1 point
    I got it. I decided not to use the master and slave technique, and just ran "FDwfAnalogOutConfigure" with the idxChannel as -1 to run all the enabled channels at once.
  34. 1 point
    PaulW

    I2C SCL line remains low on Cora Z7 board

    This has helped my problem: https://forums.xilinx.com/t5/UltraScale-Architecture/I2C-through-EMIO/td-p/984165 particularly: " As would be expected this turned out to be something very simple. For I2C not only is the SDA bi-directional but SCL is also, but I had not set up the return path for SCL. So the controller was always waiting to see the SCL line high before starting anything and that's why both SDA and SCL showed no activity even on the ILA. In the vhdl wrapper for the block design just the second line below was the fix: <SCL I/O pin name> <= I2C1_scl_out when (I2C1_scl_tristate = '0') else 'Z'; I2C1_scl_in <= <SCL I/O pin name>; -- <- This was the missing vhdl line that I needed to add in the wrapper vhdl file <SDA I/O pin name> <= I2C1_sda_out when (I2C1_sda_tristate = '0') else 'Z'; I2C1_sda_in <= <SDA I/O pin name>; Thanks for the help on this.
  35. 1 point
    Hi @Baig. SDR ADRV9361 board is not from Digilent. It is not clear which version of Qt you have on your board(target) and against which version you link your app. Please make sure it is the same. Also make sure qtmodules you use in your app are properly working on the board. You can run examples that are provided with QT to do that. If you want to debug, build/install Qt framework in debug mode, usually the lib files have 'd' at the and of name: libQtCored.so You can use `ldd` tool to inspect dependencies for your app on target to make sure something is not missing which seams to be the case. Also note that QWS was repalced in Qt > 5.0.0 with QPA.
  36. 1 point
    Hi @sgrobler, The OpenLogger doesn't have any sort of RTC or time keeping mechanism. Because of that, the data cannot be timestamped and that functionality cannot be added. AndrewHolzer
  37. 1 point
    Glenn

    USB Power

    Upon further reflection, I bet my switched cables do not have all the USB lines coming through. RPi only needs power via it's microUSB input.
  38. 1 point
    First of all the Project Vault is a place to post working projects, not ask questions; so this post belongs somewhere else. Doing things and knowing how they work are often two different challenges. Understanding how to create a tone and how to implement LTE are worlds apart. Wanting to understand the concepts for both are worthwhile goals. I'd advise starting with a good textbook. Janak Sodha's book Fundamentals of Communications Systems is a good introductory text with lots of accessible examples. Analog Devices has a number of good application notes texts available as well. Beware that there is a lot of math involved. Fortunately, one doesn't have to do brute force math to implement basic signal creation. To start, consider a vector. It has length and an angular orientation relative to some X-Y coordinate system. If you pin the tail to a fixed point and spin the head of the vector around at a constant rate you've created the basis for a tone. The basic building block of a tone generator is the phase accumulator. The phase accumulator is nothing more than an adder where you don't care about overflow. The time it takes between overflows represents the tonal frequency. Of course tones are sinusoidal so the actual tone requires using the accumulated phase as a pointer into a sine or cosine lookup table. And that's the 10 second introductory lecture on communications. Now if you suppose that creating a tone and creating the exact tone with the qualities that you want might be a bit more complicated then you assume correctly; but dealing with the details isn't a 10 second presentation. Now, you can do all sorts of interesting things with your rotating vector like modulate ( vary ) its magnitude for AM. Or, instead of changing the phase input to your phase accumulator at a constant rate you can modulate the input to do FM or PM. If you create a number of different tones and add them you can encode information that can be extracted by finding which tones make up the signal. There's quite a leap from there to modern communications in terms of what you need to understand but that's the fun. All of these can be implemented in FPGA logic with a lot of knowledge and a bit of insight. Communications is little more than creating and manipulating tones with some sophisticated conditioning involved. Conditioning is important because poorly designed or constrained communications interfere with other even well designed communication systems. That's why the experimenter needs to be careful building hardware that transmits signals. Drowning out an FM station that you are listening to while playing around with your hardware might be fun for you but will not be so much fun for your neighbours; particularly if they are dependent on a communications system like police and firemem or pilots. The pioneers of modern communications were mathematicians like Fourier, Laplace and Euler who understood the basic concepts long before other very smart people got around to playing with tonal generation for transmitting and receiving information. And all of it is possible because someone had some insight that made the very difficult practical to implement.
  39. 1 point
    Hi @sgrobler, I've build a 64-bit executable for Windows, which you can download from here. Save that into a location you're likely to remember. Refer to the repository README for instructions on how to use the executable. Regards, AndrewHolzer
  40. 1 point
    Hi @Lesiastas Sorry, but I'm not familiar with VB6, VBA. This was my biggest VB application so far Please search on the net for solutions, like: http://www.excely.com/excel-vba/bit-shifting-function.shtml probably a += b should be written as a = a + b
  41. 1 point
    Executables will be posted in the next few days. But if you'd like to build it on Windows you can do one of the following: Install git for windows Install cygwin If you have Win 10, you can install a Linux Subsystem within Windows Ubuntu Other distributions If you don't want to use git clone, you can download the source repository as a zip file.
  42. 1 point
    Hello, We apologize for taking so long to answer this issue. I have followed the steps you mentioned in the first post (of course, using zybo-z7-20 instead of zybo-z7-10) and I managed to get things done. Please be careful to the exported file location (I suggest to use the project default locations). I attach a screen caption with the Vivado block design and a caption with my teminal showing the great message. I am also attaching a zip with my project, in case you fail to get it running you can try to use mine. Please follow the steps from the readme file (run the proj/create_project.tcl script, ...). Good luck. ZyboHello.zip
  43. 1 point
    mmdsaifudn

    SREC SPI Bootloader is Very Slow

    @bhall Thanks a lot bhall for giving info.I got this elf bootloader working when I started from scratch.
  44. 1 point
    @JColvin I wasn't able to use the Add Design Tools or Devices function due to administrator controlled system, but I was able to reinstall from scratch and fixed the issue. Thanks @JColvin and @Bianca!
  45. 1 point
    Hi @sgrobler and @benl, I was informed today that a conversion process of converting a dlog file into csv is now tested and working for OpenLogger and OpenScope MZ and is documented here: https://reference.digilentinc.com/reference/software/waveforms-live/how-to-convert-dlog. If you have any questions on this, I will try to answer them, but may end up deferring to @AndrewHolzer for the technical side of things. Thanks, JColvin
  46. 1 point
    Hi @Lesiastas The rg0 will get its value after you step over the respective line, after the decode function is executed. Byte sampling: Module Module1 Function decodeUart(ByRef rgData() As Byte, ByVal cSamplePerBit As Integer, ByVal pin As Integer) As List(Of Byte) Dim pData As Boolean Dim fData As Boolean = False Dim cSamples = rgData.Length Dim rgUart As New List(Of Byte) For i As Integer = 0 To cSamples - 1 Dim s = rgData(i) pData = fData fData = 1 And (s >> pin) If pData <> 0 And fData = 0 Then Dim bValue As Integer = 0 For b = 0 To 7 Dim ii = Math.Round(i + (1.499 + b) * cSamplePerBit) ''''' If ii >= cSamples Then Exit For End If s = rgData(ii) fData = 1 And (s >> pin) If fData Then bValue += (1 << b) End If Next rgUart.Add(bValue) i += cSamplePerBit * 9.499 - 1 ''''' 1 start + 8 bits + 0.5 stop -1 because For will increment End If Next Return rgUart End Function Sub Main() Dim hdwf As Long If FDwfDeviceOpen(-1, hdwf) = False Then Dim szError As String FDwfGetLastErrorMsg(szError) System.Console.WriteLine("Device open failed" & vbCrLf & szError, vbExclamation + vbOKOnly) End End If Const hzUart = 9600 Const hzRate = hzUart * 1 ''''' Const cSamples = 1000 Dim hzDI As Double FDwfDigitalInInternalClockInfo(hdwf, hzDI) FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDetectorDigitalIn) FDwfDigitalInTriggerSet(hdwf, 0, 0, 0, &HFFFF) 'any falling edge 'FDwfDigitalInTriggerAutoTimeoutSet(hdwf, 10.0) FDwfDigitalInDividerSet(hdwf, hzDI / hzRate) FDwfDigitalInSampleFormatSet(hdwf, 8) FDwfDigitalInBufferSizeSet(hdwf, cSamples) FDwfDigitalInTriggerPositionSet(hdwf, cSamples - 10) FDwfDigitalInConfigure(hdwf, 1, 1) Dim sts As Byte While True If FDwfDigitalInStatus(hdwf, 1, sts) = 0 Then Return End If If sts = DwfStateDone Then Exit While End If End While FDwfDigitalInDividerGet(hdwf, hzRate) ' get the actual rate Const cSamplePerBit = hzRate / hzUart Dim rgData(cSamples) As Byte FDwfDigitalInStatusData(hdwf, rgData, 1 * rgData.Length) Call FDwfDeviceCloseAll() Dim rg0 = decodeUart(rgData, cSamplePerBit, 0) System.Console.Write("Hex 0: ") For i = 0 To rg0.Count - 1 System.Console.Write(" 0x" + Conversion.Hex(rg0(i))) Next System.Console.WriteLine() System.Console.WriteLine("Text 0: " + System.Text.Encoding.ASCII.GetString(rg0.ToArray)) End Sub End Module
  47. 1 point
    Hi @miner_tom, Looking at your screen shots, it looks like the board is showing as COM8 in the ports section and both converter a an b are showing in the Universal serial bus controller section. Please download Adept 2 here. Does the Adept 2 recognize the Zybo-Z7-20? I attached an example of this using a Cora Z7. Does Vivado's Hardware Manager recognize the Zybo-Z7-20? Is the mode jumper set to JTAG? best regards, Jon
  48. 1 point
    Hi @NotMyCupOfTea, We have an old ZedBoard programming tutorial. This was not checked for a while so might contain errors. Also, it's made for older versions of Vivado SDK. Things might be a bit different with the current versions. It goes through the steps @xc6lx45 mentioned above. I hope it helps. https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-programming-guide/start?s[]=qspi Bianca
  49. 1 point
    attila

    Math on FFT traces

    Hi @lab!fyi In the Network Analyzer extended option lets you use Wavegen channels at up to 20MHz and with external up to 50MHz. In the Spectrum Analyzer you can select frequency range up to 10MHz but with auto option lets you set Stop frequency up to 50MHz. Selecting the dB unit will let you specify custom reference, for dBm I think it should be 0.316V
  50. 1 point
    attila

    WaveForms beta download

    3.11.27 digilent.waveforms_beta_v3.11.27_64bit.exe digilent.waveforms_beta_v3.11.27.dmg digilent.waveforms_beta_3.11.27_amd64.deb digilent.waveforms_beta_3.11.27.x86_64.rpm Fixes and Help update 3.11.26 digilent.waveforms_beta_v3.11.26_64bit.exe digilent.waveforms_beta_v3.11.26.dmg digilent.waveforms_beta_3.11.26_amd64.deb digilent.waveforms_beta_3.11.26.x86_64.rpm Added: - Script: - multiple files for individual scripts or optional include Fixed: - Logic Analyzer: - keep order in Bus signals 3.11.25 digilent.waveforms_beta_v3.11.25_64bit.exe digilent.waveforms_beta_3.11.25_amd64.deb digilent.waveforms_beta_3.11.25.x86_64.rpm Fixed: - Protocol I2C Read with Script 3.11.24 digilent.waveforms_beta_v3.11.24_64bit.exe digilent.waveforms_beta_v3.11.24.dmg digilent.waveforms_beta_3.11.24_amd64.deb digilent.waveforms_beta_3.11.24.x86_64.rpm Added: - Wavegen: - period setting next to frequency Changed: - Protocol: - AVR programmer speed, functions, script access Fixed: - Network Analyzer: - phase averaging 3.11.22 digilent.waveforms_beta_v3.11.22_64bit.exe digilent.waveforms_beta_v3.11.22.dmg (not certified) digilent.waveforms_beta_3.11.22_amd64.deb digilent.waveforms_beta_3.11.22.x86_64.rpm Added: - Logic Analyzer: - SPI interpreter with MOSI/MOSI - HDMI CEC interpreter, trigger on: start, source, destination - Portocol: - AVR programmed: Flash, EEPROM, Fuse, Lock, Calibration - Scope/Logic remembers as default option: Show Attenuation, Acquire Noise, Multiple Scale - Pattern Generator negative delay option Changed: - Pattern Generator: - clock duty round up 3.11.21 digilent.waveforms_beta_v3.11.21_64bit.exe Fixed: - Patterns preview 3.11.20 digilent.waveforms_beta_v3.11.20_64bit.exe Added: - shared workspace list when running multiple applications Fixed: - Digital Discovery trigger position - Patterns preview for pulse - other minor fixes 3.11.19 digilent.waveforms_beta_v3.11.19_64bit.exe Added: - Patterns Delay option for signal/bus Fixed: - Digital Discovery system frequency adjustment 3.11.18 digilent.waveforms_beta_v3.11.18_64bit.exe Fixed: - Supplies for EExplorer and Analog Discovery 1 - Logic Analyzer Inputs for Digital Discovery 3.11.17 digilent.waveforms_beta_v3.11.17_64bit.exe Added: - Spectrum Units: V/vHz, dBm, dBm/vHz, dBm/vMHz - Digital Discovery: - system frequency (Pattern Generator and Logic Analyzer) fine adjustment from Supplies window 3.11.16 digilent.waveforms_beta_v3.11.16_64bit.exe Added: - Spectrum: - Units: dBm, dBmHz, dBmMHz Fixed: - Wavegen: Sync option 3.11.15 digilent.waveforms_beta_v3.11.15_64bit.exe Added: - SDK: - VB/C# ushort and uinteger modes for FDwfDigitalInStatusData/2/Noise/2 - replacing BOOL and BYTE types - manual update - Logic Analyzer: - 100 MHz limit option for Digital Discovery Fixed: - Spectrum: Persistence view axis labels for log scales - SDK: VB/C# wrappers FDwfAnalogInStatusData16 3.11.14 digilent.waveforms_beta_v3.11.14_64bit.exe digilent.waveforms_beta_3.11.14_amd64.deb digilent.waveforms_beta_3.11.14.x86_64.rpm Added: - Script access to Logic Analyzer measurements - System Monitor in Supplies window for AD1, AD2, DD Fixed: - SDK DwfParamOnClose continue running after re-open 3.11.13 digilent.waveforms_beta_v3.11.13_64bit.exe Added: - Network/Impedance Analyzer usage with constant frequency, start=stop - quick measure, cursors, horizontal axis as percentage 3.11.12 digilent.waveforms_beta_v3.11.12_64bit.exe digilent.waveforms_beta_3.11.12_amd64.deb digilent.waveforms_beta_3.11.12.x86_64.rpm Added: - Import data from file option for Spectrum, Network and Impedance Analyzer - trace toolbar width setting for Impedance Analyzer - AnalogOutIn_PlayRecord.py example playing mono and recording to stereo WAV file - FDwfAnalogImpedanceStatusInput phase normalization Fixed: - Analog Discovery 2 USB power monitor false 1A readings - wrong default reference for dBV in Spectrum Analyzer 3.11.11 digilent.waveforms_beta_v3.11.11_64bit.exe Added: - Logic Analyzer Bus interpreter: - either Clock edge option - sampling delay relative to edge - Events view lists sample for each edge when Clock signal is selected 3.11.10 digilent.waveforms_beta_v3.11.10_64bit.exe Added: - Scope scale for XYZ and Spectrogram 3D views - Export EPS image format - support for multiple transfers in Protocol/I2C/Sensor loop function 3.11.9 digilent.waveforms_beta_v3.11.9_64bit.exe Added: - Scope Spectrogram 3D surface view, for 64bit Windows 3.11.8 digilent.waveforms_beta_v3.11.8_64bit.exe digilent.waveforms_beta_v3.11.8.dmg digilent.waveforms_beta_3.11.8_amd64.deb digilent.waveforms_beta_3.11.8.x86_64.rpm Added: - horizontal cursors for Scope/FFT, Spectrum and Impedance Analyzer - cursor delta as decade for logarithmic scales - Scope: - simple Math channel operations: RMS, ATan - LockIn amplifier as Math channel - XYZ 3D graph, for 64bit Windows Fixed: - Scope/Audio/Tempo option 3.11.7 digilent.waveforms_beta_v3.11.7_64bit.exe digilent.waveforms_beta_v3.11.7.dmg digilent.waveforms_beta_3.11.7_amd64.deb digilent.waveforms_beta_3.11.7.x86_64.rpm minor fixes and improvements 3.11.6 digilent.waveforms_beta_v3.11.6_64bit.exe digilent.waveforms_beta_v3.11.6.dmg digilent.waveforms_beta_3.11.6_amd64.deb digilent.waveforms_beta_3.11.6.x86_64.rpm Added: - Protocol - UART Spy - Max Lines option: log limit to prevent application slowdown - Line Wrap option - tooltips for UI controls listing Script access path - application and script Font options - dark theme support for Script 3.11.5 digilent.waveforms_beta_v3.11.5_64bit.exe Added: - Script open/save text file - application argument: -script myscript.txt/js Fixed: - warnings at low record rates 3.11.4 digilent.waveforms_beta_v3.11.4_64bit.exe Added: - Scope: - set/reset zero offset in each channel option - precision option for measurements Fixed: - Script: access to traces and channels from Instrument.Export - unit conversions V to Ṽ, A to à - I2S 32 bit data 3.11.3 digilent.waveforms_beta_v3.11.3_64bit.exe digilent.waveforms_beta_3.11.3_amd64.deb digilent.waveforms_beta_3.11.3.x86_64.rpm Fixes 3.11.2 digilent.waveforms_beta_v3.11.2_64bit.exe digilent.waveforms_beta_3.11.2_amd64.deb digilent.waveforms_beta_3.11.2.x86_64.rpm Added: - Spectrum, Network and Impedance Analyzer store time data when this view is open Fixed: - runscript argument - loading of docked views geometry 3.11.1 digilent.waveforms_beta_v3.11.1_64bit.exe digilent.waveforms_beta_3.11.1_amd64.deb digilent.waveforms_beta_3.11.1.x86_64.rpm Added: - Scope: out of range warning in measurements - Protocol/UART: - support up to 32bit/word - TX/RX format: text, binary, decimal, hex - Wheel Direction option - Logic Analyzer: option to swap previous/next events - Spectrum Analyzer: allowing higher number of BINs for CZT 3.10.7 digilent.waveforms_beta_v3.10.7_64bit.exe Added: - Spectrum: logarithmic magnitude scale for voltage units - Protocol: datetime stamp for SPI/I2C Spy Fixes 3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom math channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Network Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.