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  1. 6 points
    attila

    WaveForms beta download

    3.11.11 digilent.waveforms_beta_v3.11.11_64bit.exe Added: - Logic Analyzer Bus interpreter: - either Clock edge option - sampling delay relative to edge - Events view lists sample for each edge when Clock signal is selected 3.11.10 digilent.waveforms_beta_v3.11.10_64bit.exe Added: - Scope scale for XYZ and Spectrogram 3D views - Export EPS image format - support for multiple transfers in Protocol/I2C/Sensor loop function 3.11.9 digilent.waveforms_beta_v3.11.9_64bit.exe Added: - Scope Spectrogram 3D surface view, for 64bit Windows 3.11.8 digilent.waveforms_beta_v3.11.8_64bit.exe digilent.waveforms_beta_v3.11.8.dmg digilent.waveforms_beta_3.11.8_amd64.deb digilent.waveforms_beta_3.11.8.x86_64.rpm Added: - horizontal cursors for Scope/FFT, Spectrum and Impedance Analyzer - cursor delta as decade for logarithmic scales - Scope: - simple Math channel operations: RMS, ATan - LockIn amplifier as Math channel - XYZ 3D graph, for 64bit Windows Fixed: - Scope/Audio/Tempo option 3.11.7 digilent.waveforms_beta_v3.11.7_64bit.exe digilent.waveforms_beta_v3.11.7.dmg digilent.waveforms_beta_3.11.7_amd64.deb digilent.waveforms_beta_3.11.7.x86_64.rpm minor fixes and improvements 3.11.6 digilent.waveforms_beta_v3.11.6_64bit.exe digilent.waveforms_beta_v3.11.6.dmg digilent.waveforms_beta_3.11.6_amd64.deb digilent.waveforms_beta_3.11.6.x86_64.rpm Added: - Protocol - UART Spy - Max Lines option: log limit to prevent application slowdown - Line Wrap option - tooltips for UI controls listing Script access path - application and script Font options - dark theme support for Script 3.11.5 digilent.waveforms_beta_v3.11.5_64bit.exe Added: - Script open/save text file - application argument: -script myscript.txt/js Fixed: - warnings at low record rates 3.11.4 digilent.waveforms_beta_v3.11.4_64bit.exe Added: - Scope: - set/reset zero offset in each channel option - precision option for measurements Fixed: - Script: access to traces and channels from Instrument.Export - unit conversions V to Ṽ, A to à - I2S 32 bit data 3.11.3 digilent.waveforms_beta_v3.11.3_64bit.exe digilent.waveforms_beta_3.11.3_amd64.deb digilent.waveforms_beta_3.11.3.x86_64.rpm Fixes 3.11.2 digilent.waveforms_beta_v3.11.2_64bit.exe digilent.waveforms_beta_3.11.2_amd64.deb digilent.waveforms_beta_3.11.2.x86_64.rpm Added: - Spectrum, Network and Impedance Analyzer store time data when this view is open Fixed: - runscript argument - loading of docked views geometry 3.11.1 digilent.waveforms_beta_v3.11.1_64bit.exe digilent.waveforms_beta_3.11.1_amd64.deb digilent.waveforms_beta_3.11.1.x86_64.rpm Added: - Scope: out of range warning in measurements - Protocol/UART: - support up to 32bit/word - TX/RX format: text, binary, decimal, hex - Wheel Direction option - Logic Analyzer: option to swap previous/next events - Spectrum Analyzer: allowing higher number of BINs for CZT 3.10.7 digilent.waveforms_beta_v3.10.7_64bit.exe Added: - Spectrum: logarithmic magnitude scale for voltage units - Protocol: datetime stamp for SPI/I2C Spy Fixes 3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom mathematic channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Netowrk Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.
  2. 5 points
    Sanyi

    Waveforms woks on Linux

    Hi All,I have an Analog Discovery, and I used to use it in VitualBox Xp. This was the only software I had to run on Windows. I decided to get rid ofWindows, so I had to make the Waveforms ready for Linux. It is a quite easy task to do: 1. Install 32bit wine. 2. export WINEARCH=win32 3. winetricks --gui dlls select msxml3 and dotnet35 4. Install Waveforms. Now the Waveforms must run in demo mode. 5. Install digilent.adept.runtime_2.15.3-i686 and digilent.waveforms_2.7.5-i386 6. cp dwf.dll.so dwf.def /usr/local/lib64/wine (in my case) you mustcheck your wine inst. dirs 7. cp dwf.dll.fake /usr/local/lib64/wine/fakedlls/ Enjoy your Linux Waveforms! Sanyi files.tar.gz
  3. 5 points
    hamster

    Welcome!

    My name is Mike, and I've developed a bit of an obsession with FPGAs. You might be able to find some project ideas or inspiration on my WIki at http://hamsterworks.co.nz/mediawiki/index.php/FPGA_Projects I'm always happy to talk FPGAs, so feel free to drop me an email sometime
  4. 4 points
    attila

    Analog Discovery troubleshooting

    During device opening internal chips are enabled and configured. This results in consumption increases, specially when the 100 MHz clock (PLL) is started. The needed current increases from 100mA to 500mA. In case the USB can't provide enough current the voltage drops below the minimal required for the device to operate and communication fails. In case you get “Device configuration failed (PLL 1)" or "Communication with the device failed.” error message: The device needs at least 2W/400mA from USB cable. To satisfy this: - Try to use different USB cable and computer plug. - Use the USB plug on the back of the PC, not the one on the front panel. - Use short cable, do not use long cable or cable extender. - Use powered USB-hub, avoid un-powered hub. - Use USB-Y cable to load power from two plugs. Device not detected by WaveForms: Open Windows Device Manager then connect the device and wait up to one minute for a device to appear: - USB Serial Converter, with warning - Connect the device directly to the computer's USB plug without using external hub. - Restart the computer. - Reinstall WaveForms, including the Adept Runtime section. - USB Serial Converter, without warning - Restart the computer. - Reinstall WaveForms, including the Adept Runtime section. - Other application might have erased the USB controller EEPROM (FT_Prog, programming cable drivers...) Use the "My device is not listed" button in WaveForms application Device Manager to reprogram the EEPROM. - Unknown Device Check the Hardware IDs under device Properties, Details tab - USBVID_0403&PID_6014 The USB driver is not installed. - Restart the computer. - Reinstall WaveForms, including the Adept Runtime section. - USBVID_0000&PID_0000 Device not identified or malfunction. See "Nothing shows up". - Nothing shows up: - Connect the device directly to the computer's USB plug without using external hub. - Try to use different USB cable and computer plug. The device or its plug might be damaged.
  5. 4 points
    circuitsense

    FreeRTOS on Zybo

    Hello Everyone, This is just for reference. FreeRTOS running on the Zybo. I could not find any FreeRTOS based post on this forum so i thought this might help anyone trying to attempt the same... http://bit.ly/freertos-on-zybo
  6. 4 points
    hamster

    HDMI input for Nexys Video.

    I've finally got my HDMI input project to a point where I have something to show. This little picture makes me really happy: This project does the following actions: Advertise HDMI support over EDID/DCCReceive the TMDS signalsDe-serialize them into 10-bit symbolsAlign the symbols using bitslipsTune the input delays for best receptionConvert the TMDS symbols into data valuesExtract CTL, Aux Data Periods (ADPs) and Video Data Periods (VDPs)Extract Video Infoframes from the ADP dataExtract Audio Samples from the ADP data.Extract Raw Pixels from the VDPsPerform 422 to 444 conversion, if required by video formatPerform YCbCr to RGB conversion, if required by video formatConvert Studio Level RGB to Full Range RGB, if required by video formatConvert Audio smaples to a relative db levelOverlay Audio level meters over the video streamConvert the video stream and sync signals back to TMDS symbolsSerialize them through a 10:1 serialisersTransmit the TMDS.I think that this is an awesome base for any video experimentation. I've even got to the trouble of making a GitHub repo for it: https://github.com/hamsternz/Artix-7-HDMI-processing Please feel free to fork and extend.
  7. 4 points
    Iw@n

    Petalinux on Genesys 2!

    Hi All, On http://www.iwans.net/xilinx/ I placed a comprehensive manual on how to run Petalinux on a Digilent Genesys 2 board. Board files made in Vivado 2016.2 are included, but at the moment only the USB UART, on-board GPIO (LED's and buttons) and 1 GBit Ethernet are supported. Iwan
  8. 4 points
    Bianca

    I want to blink LED

    Hello hilarikas, I just checked again your files and saw some things that I missed last time I looked. I saw that you tried to assign your clock signal and one led. Unfortunately you confused the XDC file with the UCF file. Both UCF and XDC are contraints files. UCF is used with ISE and XDC is used with Vivado. The main difference between them is the syntax. What you tried to do was writing in the XDC the with the syntax from UCF. It won't work. XDC syntax for the clock: ## Clock Signal #set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n #set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p UCF syntax for the clock: ## Clock signal #NET "clk" LOC = "E3" | IOSTANDARD = "LVCMOS33"; (taken from Nexys4 UCF) What you tried to do: ##NET "refclk" LOC = "AD11"; Then, you cannot use the Genesys2 clock like this. It's a differential clock and you'll have to use a primitive to instantiate it. As you can see you have a sysclk_n and a sysclk_p. You'll have to use IBUFG primitive. you can find more information in Xilinx documentation. This primitive will allow you to use the clock. The primitive looks like this: IBUFDS_inst : IBUFGDS generic map ( DIFF_TERM => FALSE, -- Differential Termination IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "DEFAULT") port map ( O => O, -- Buffer output I => I, -- Diff_p buffer input (connect directly to top-level port) IB => IB -- Diff_n buffer input (connect directly to top-level port) ); Where, O is a clock signal you will declare as standard_logic. (Not Port, but Signal) in your case you wanted refclk and I and IB are the two parts of the differential clock. it would look like this: IBUFDS_inst : IBUFGDS generic map ( DIFF_TERM => FALSE, -- Differential Termination IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "DEFAULT") port map ( O => refclk, -- Buffer output I => sysclk_p, -- Diff_p buffer input (connect directly to top-level port) IB => sysclk_n -- Diff_n buffer input (connect directly to top-level port) ); After this when your code and your XDC are ready synthesize your project. Don't generate bitstream just synthesize then open the synthesized design. You'll have to assign that clock to the design, in order to know that is a clock signal. Attached to this post is a word document with a tutorial on how to assign the clock. At the end of this reload your XDC file. You'll have an option on the top where you have the page open and if all works well you'll see that it will add an extra line on the bottom of your XDC. Mine looks like this: create_clock -period 5.000 -name sysclk_p -waveform {0.000 2.500} [get_ports sysclk_p] After you finished, generate your bitstream and put it on the board. Attached here you'll also find an example of a working code that counts on the leds and the correct uncommented XDC file. Best regads, Bianca Asign Clock.docx LED.vhd Genesys2_H.xdc
  9. 4 points
    cristian.ignat

    Add board to ISE

    Hi, You can add your own board following the steps: 1. Go to ..\Xilinx\14.7\ISE_DS\EDK\board\Xilinx\boards 2. Create a folder board 3. In your folder board create "data" folder 4. Create a .xbd file 5. Open this file and edit with the necessary parameters For example, I add a Nexys4 board. The path for the Digilent_Nexys4.xbd file, in my case is: C:\Xilinx\14.7\ISE_DS\EDK\board\Xilinx\boards\Digilent_Nexys4\data The file content is: ATTRIBUTE VENDOR = Digilent ATTRIBUTE NAME = Nexys4 ATTRIBUTE REVISION = B ATTRIBUTE SPEC_URL = www.digilentinc.com ATTRIBUTE CONTACT_INFO_URL = http://www.digilentinc.com/Support/Support.cfm ATTRIBUTE DESC = Digilent Nexys4 Evaluation Platform ATTRIBUTE LONG_DESC = '-' BEGIN FPGA ATTRIBUTE INSTANCE = fpga_0 ATTRIBUTE FAMILY = artix7 ATTRIBUTE DEVICE = xc7a100t ATTRIBUTE PACKAGE = csg324 ATTRIBUTE SPEED_GRADE = -1 ATTRIBUTE JTAG_POSITION = 1 END Please see the result: Best regards, Cristian
  10. 4 points
    Hi Arvy, Here is some code I wrote tonight. It includes the XADC instance, set to measure channel 6 in unipolar mode. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; Library UNISIM; use UNISIM.vcomponents.all; entity xadc_test is Port ( clk100 : in STD_LOGIC; led : out STD_LOGIC_VECTOR (15 downto 0); JXADC : in STD_LOGIC_VECTOR (7 downto 0)); end xadc_test; architecture Behavioral of xadc_test is signal reading : std_logic_vector(15 downto 0) := (others => '0'); signal muxaddr : std_logic_vector( 4 downto 0) := (others => '0'); signal channel : std_logic_vector( 4 downto 0) := (others => '0'); signal vauxn : std_logic_vector(15 downto 0) := (others => '0'); signal vauxp : std_logic_vector(15 downto 0) := (others => '0'); begin led <= reading; ----------------------------------- -- Pass through the analogue inputs ----------------------------------- vauxp(6) <= jxadc(0); vauxn(6) <= jxadc(4); vauxp(14) <= jxadc(1); vauxn(14) <= jxadc(5); vauxp(7) <= jxadc(2); vauxn(7) <= jxadc(6); vauxp(15) <= jxadc(3); vauxn(15) <= jxadc(7); XADC_inst : XADC generic map ( -- INIT_40 - INIT_42: XADC configuration registers INIT_40 => X"9000", -- averaging of 16 selected for external channels INIT_41 => X"2ef0", -- Continuous Seq Mode, Disable unused ALMs, Enable calibration INIT_42 => X"0800", -- ACLK = DCLK/8 = 100MHz / 8 = 12.5 MHz -- INIT_48 - INIT_4F: Sequence Registers INIT_48 => X"4701", -- CHSEL1 - enable Temp VCCINT, VCCAUX, VCCBRAM, and calibration INIT_49 => X"000CC", -- CHSEL2 - enable aux analog channels 6,7,14,15 INIT_4A => X"0000", -- SEQAVG1 disabled all channels INIT_4B => X"0000", -- SEQAVG2 disabled all channels INIT_4C => X"0000", -- SEQINMODE0 - all channels unipolar INIT_4D => X"00CC", -- SEQINMODE1 - all channels unipolar INIT_4E => X"0000", -- SEQACQ0 - No extra settling time all channels INIT_4F => X"0000", -- SEQACQ1 - No extra settling time all channels -- INIT_50 - INIT_58, INIT5C: Alarm Limit Registers INIT_50 => X"b5ed", -- Temp upper alarm trigger 85°C INIT_51 => X"5999", -- Vccint upper alarm limit 1.05V INIT_52 => X"A147", -- Vccaux upper alarm limit 1.89V INIT_53 => X"dddd", -- OT upper alarm limit 125°C - see Thermal Management INIT_54 => X"a93a", -- Temp lower alarm reset 60°C INIT_55 => X"5111", -- Vccint lower alarm limit 0.95V INIT_56 => X"91Eb", -- Vccaux lower alarm limit 1.71V INIT_57 => X"ae4e", -- OT lower alarm reset 70°C - see Thermal Management INIT_58 => X"5999", -- VCCBRAM upper alarm limit 1.05V INIT_5C => X"5111", -- VCCBRAM lower alarm limit 0.95V -- Simulation attributes: Set for proper simulation behavior SIM_DEVICE => "7SERIES", -- Select target device (values) SIM_MONITOR_FILE => "design.txt" -- Analog simulation data file name ) port map ( -- ALARMS: 8-bit (each) output: ALM, OT ALM => open, -- 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram OT => open, -- 1-bit output: Over-Temperature alarm -- STATUS: 1-bit (each) output: XADC status ports BUSY => open, -- 1-bit output: ADC busy output CHANNEL => channel, -- 5-bit output: Channel selection outputs EOC => open, -- 1-bit output: End of Conversion EOS => open, -- 1-bit output: End of Sequence JTAGBUSY => open, -- 1-bit output: JTAG DRP transaction in progress output JTAGLOCKED => open, -- 1-bit output: JTAG requested DRP port lock JTAGMODIFIED => open, -- 1-bit output: JTAG Write to the DRP has occurred MUXADDR => muxaddr, -- 5-bit output: External MUX channel decode -- Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0] VAUXN => vauxn, -- 16-bit input: N-side auxiliary analog input VAUXP => vauxp, -- 16-bit input: P-side auxiliary analog input -- CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs CONVST => '0', -- 1-bit input: Convert start input CONVSTCLK => '0', -- 1-bit input: Convert start input RESET => '0', -- 1-bit input: Active-high reset -- Dedicated Analog Input Pair: 1-bit (each) input: VP/VN VN => '0', -- 1-bit input: N-side analog input VP => '0', -- 1-bit input: P-side analog input -- Dynamic Reconfiguration Port (DRP) -- hard set to read channel 6 (XADC4/XADC0) DO => reading, DRDY => open, DADDR => "0010110", -- The address for reading AUX channel 6 DCLK => clk100, DEN => '1', DI => (others => '0'), DWE => '0' ); end Behavioral; And here is the XDC file for the Basys3: set_property PACKAGE_PIN W5 [get_ports clk100] set_property IOSTANDARD LVCMOS33 [get_ports clk100] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk100] ## LEDs set_property PACKAGE_PIN U16 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] set_property PACKAGE_PIN E19 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] set_property PACKAGE_PIN U19 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] set_property PACKAGE_PIN V19 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] set_property PACKAGE_PIN W18 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] set_property PACKAGE_PIN U15 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] set_property PACKAGE_PIN U14 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] set_property PACKAGE_PIN V14 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] set_property PACKAGE_PIN V13 [get_ports {led[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] set_property PACKAGE_PIN V3 [get_ports {led[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] set_property PACKAGE_PIN W3 [get_ports {led[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] set_property PACKAGE_PIN U3 [get_ports {led[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] set_property PACKAGE_PIN P3 [get_ports {led[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] set_property PACKAGE_PIN N3 [get_ports {led[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] set_property PACKAGE_PIN P1 [get_ports {led[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] set_property PACKAGE_PIN L1 [get_ports {led[15]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] ##Pmod Header JXADC ##Sch name = XA1_P set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] ##Sch name = XA2_P set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] ##Sch name = XA3_P set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] ##Sch name = XA4_P set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] ##Sch name = XA1_N set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] ##Sch name = XA2_N set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] ##Sch name = XA3_N set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] ##Sch name = XA4_N set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] When downloaded to your board, the value displayed in binary on the the LEDs should reflect the voltage on Pin 0 if the PXADC. I tested just by pushing some header pins into the PMOD and touching the pin - not exactly a complete test, but enough to show that it does something. NOTE: THE FULL SCALE VOLTAGE FOR THE XADC IS 1V, so some crafty planning might be required to interface to it.
  11. 4 points
    shockmonky

    Zybo ZYNQ Beginners help

    I had the same problem and switching the "reset Processor" to "Reset entire system" worked like a charm! Love you guys at Digilent!
  12. 4 points
    mwingerson

    Help With A Zybo Video Design

    Hey guy, I got it working with a little help from Sam. To simplify the whole thing, I trimmed out all of the zynq associated blocks since this is project isn't using the PS and removed the extra XDCs. The DDC channels on the dvi2rgb core need to assigned correctly and it is a bit of a pain. Delete all connectionsright-click DDC Select "make external" open the design wrapper and there should be two signals names "ddc_scl_io" and "ddc_sda_io"modify the Zybo master XDC to reflect those names in the HDMI group. Sam helped me fix the timing errors associated with timing. The fix was to comment out comment out this the create_clock line in "dvi2rgb.xdc". The new file should look like this: The issue is that the "create_clock" command is forcing the TMDS_Clk_p to be a frequency that cannot be supported by FPGA on the Zybo causing the timing error. Removing it allows the solution in the TMDS clock generate work. Finally, change the clocking wizard block to be in the PLL instead of the MMCM. The dvi2rgb core uses an MMCM and the clocking wizard wants to use a MMCM but there is only one MMCM in that section of the FPGA so tell the clocking wizard to use a PLL. I uploaded working directory to my github: here Hope this helps! Marshall
  13. 4 points
    attila

    Waveforms For Linux

    We are working on a new cross platform WaveForms software. The beta version of this, supporting Windows, OS X and Linux, will be published soon.
  14. 3 points
    logansam

    Welcome!

    Questions will not be answered here, start a new thread in the Technical Forum Welcome to the Diglent Forum! Our goal is to not only create a place where you can get support for our products, but also a community to share your projects. We are just getting started with our forum, so if there is anything you would like to see or if you would like to make any suggestions, please head over to the suggestions forum and let us know. My name is Sam, I am a web developer at Digilent.
  15. 3 points
    hearos

    FTDI chip not recognized anymore

    I have not had any activity listed when trying the "dmesg" so I went to buy a new cable, and that actually was it. Thank you for the hint!
  16. 3 points
    xc6lx45

    FTDI chip not recognized anymore

    I think it's Linux... Try the "dmesg" command immediately after plugging or unplugging. It should show some related events. The obvious, try with a different computer and a different cable. Especially cables fail often.
  17. 3 points
    Hi, reading between the lines of your post, you're just "stepping up" one level in FPGA design. I don't do long answers but here's my pick on the "important stuff" - Before, take one step back from the timing report and fix asynchronous inputs and outputs (e.g. LEDs and switches). Throw in a bunch of extra registers, or even "false-path" them. The problem (assuming this "beginner mistake") is that the design tries to sample them at the high clock rate. Which creates a near-impossible problem. Don't move further before this is understood, fixed and verified. - speaking of "verified": Read the detailed timing analysis and understand it. It'll take a few working hours to make sense of it but this is where a large part of "serious" design work happens. - Once the obvious problems are fixed, I need to understand what is the so-called "critical path" in the design and improve it. For a feedforward-style design (no feedback loops) this can be systematically done by inserting delay registers. The output is generated e.g. one clock cycle later but the design is able to run at a higher clock so overall performance improves. - Don't worry about floorplanning yet (if ever) - this comes in when the "automatic" intelligence of the tools fails. But, they are very good. - Do not optimize on a P&R result that fails timing catastrophically (as in your example - there are almost 2000 paths that fail). It can lead into a "rabbit's hole" where you optimize non-critical paths (which is usually a bad idea for long-term maintenance) - You may adjust your coding style based on the observations, e.g. throw in extra registers where they will "probably" make sense (even if those paths don't show up in the timing analysis, the extra registers allow the tools to essentially disregard them in optimization to focus on what is important) - There are a few tricks like forcing redundant registers to remain separate. Example, I have a dozen identical blocks that run on a common, fast 32-bit system clock and are critical to timing. Step 1, I sample the clock into a 32-bit register at each block's input to relax timing, and step 2) I declare these register as DONT_TOUCH because the tools would otherwise notice they are logically equivalent and try to use one shared instance. This as an example. - For BRAMs and DSP blocks, check the documentation where extra registers are needed (that get absorbed into the BRAM or DSP using a dedicated hardware register). This is the only way to reach the device's specified memory or DSP performance. - Read the warnings. Many relate to timing, e.g. when the design forces a BRAM or DSP to bypass a hardware register. - Finally, 260 MHz on Artix is already much harder than 130 MHz (very generally speaking). Usually feasible but you need to pay attention to what you're doing and design for it (e.g. a Microblaze with the wrong settings will most likely not make it through timing). - You might also have a look at the options ("strategy") but don't expect any miracles on a bad design. Ooops, this almost qualifies as "long" answer ...
  18. 3 points
    zygot

    A UART Based Debugger Tool

    Here's a utility for debugging and testing your code in hardware and uses any IO pin to send an ASCII representation of any signal through a hardware UART interface. If you don't have a UART on you FPGA board there are TTL USB UART breakout boards and cables that allow any spare IO pin to become a UART interface. This code is functionally the same as one recently released by Hamster but developed independently for the Fast Data Interface project. I recommend comparing the different coding styles. I decided to release this as a separate project as there are likely more people interested in this one that the other. This project contains test bench code. UartDebuggerR3.zip
  19. 3 points
    Ciprian

    Digital Twin

    Hi @Kris Persyn, It depends on how you manage your resources, driving immersive visuals on a HDMI display can be done in multiple ways at different resolutions, some are PL taxing others are DDR taxing; you could generate entire frame buffers in PL or PS or you could find a optimal algorithm to change just the previous frame or you could allocate a high number of frame buffers and then run them in a loop. It also depends on how math lab synthesizes the IP you will need to add to your design. If you design your project properly and don't aim for a resolution higher more 720p( I'm being conservative, we managed to drive the HDMI at 1080p with processing filters without a problem) I think it should be enough for what you want to do, resource wise. My suggestion, download and install Vivado, download and install the board files, create and implement your project look at the resource consumption and then buy a board. - Ciprian
  20. 3 points
    In your constraint file, the ddc pins have lowercase "ddc_scl_io" and "ddc_sda_io". Your block design has the port in uppercase "DDC". The case must match. Try editing your constraint file to have "DDC_scl_io" and "DDC_sda_io".
  21. 3 points
    jpeyron

    pmod wifi

    Hi @harika, I believe the HTML web page error is related to the materials on the SD card. 1) Please attach a screen shot of the contents of the Sd card you are using. 2) Please follow the YouTube video here from about 6 minutes and 28 seconds on for how to set up the HTTP server project. Make sure to update the login an password for the router/modem you are using. thank you, Jon
  22. 3 points
    dietfig

    Adept SDK C# Library

    This is a little DLL I wrote using C++ Interop in Visual Studio to pull some of the functions from the Adept SDK into C#. I'm posting it here in the hopes this is useful to someone else. It's pretty rough as I am absolutely not a Windows developer and I make no guarantees as to how well it is written and/or works (it does do what I need it to do ). Only supports basic DEPP functions as that's all I needed, other functions shouldn't be too hard to add at this point. Released under the BSD license. https://bitbucket.org/orslmontana/digilent-adept-clr-dll/
  23. 3 points
    @thobie, the bare-metal purchase option for the Zybo was done to enable a lower price point for those who do not require the accessories. For the rest of our customers, adding the Accessory Kit is recommended during the purchase process. You are not the first and the last to complain about version compatibility. It is economically unfeasible for us to update all support projects, IP and support packages provided for free four times per year for each Vivado version. Instead we made a commitment to consider the last Vivado release in each year stable and do a once-a-year update cycle. In that regard, 2017.4 is the version we are upgrading projects to. There is a question whether OOB designs should be updated at all, or kept at the version which generated the binary image shipped with the board. The board presets are not versioned for Vivado (no version-specific releases in our git repo), because these should be forward-compatible with Vivado versions. The critical warning itself related to CK-to-DQS delays being negative appears starting with 2017.4. The negative values are due to CK trace being shorter than any of the four DQS traces. In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Zybo was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Zybos shipped to customers are functionally tested and pass the DDR3 calibration process. Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. Since these delays are board-dependent, we would need to re-design the board to make the delay positive. This is impossible with the current form-factor. Another option would be modifying the board preset file and forcing a zero value instead of the actual delay. The tools seem to be using zero anyway for calibration. This will have to be thoroughly verified first.
  24. 3 points
    Hello, I've posted the next part in my FPGA graphics series using the Arty + VGA Pmod or Basys 3. It shows you how to make use of double buffering to animate sprites using simple Verilog. https://timetoexplore.net/blog/arty-fpga-vga-verilog-03 Feedback very welcome, Will PS. I'll add the source to GitHub shortly.
  25. 3 points
    attila

    Using script with Spectrum on AD2

    Hi @tomtektest, @abzza With WaveForms Script THD and other measurement logging and plotting can be automated, like this: function doTHD(){ var rgTHD = [] var rgFreq = [] for(var idx = 1; idx <= 100; idx++){ Wavegen1.Channel1.Simple.Frequency.value = 1000*idx Wavegen1.run() // start AWG wait(0.01) // settle time for the external circuit, expressed in seconds Spectrum1.Frequency.Stop.value = 20*Wavegen1.Channel1.Simple.Frequency.value // adjust analyzer stop frequency Spectrum1.single() // start acquisition if(!Spectrum1.wait()){ // wait to finish return; } rgFreq.push(Spectrum1.Trace1.measureFreq("FF")) rgTHD.push(Spectrum1.Trace1.measure("THD")) } Wavegen1.stop() print(rgFreq, rgTHD) // print data for copy paste // draw in plot1, View / Add plot plot1.X.Units.text = "Hz" plot1.Y1.Units.text = "dBc" plot1.X.data = rgFreq plot1.Y1.data = rgTHD } doTHD();
  26. 3 points
    zygot

    Rants about FPGA tool chain(s)

    @D@n , Here's a secret; I'm whispering because this is just between you and me: At places where they do a lot of quality FPGA development work no one ever brings up a GUI for anything. All of the toolchain invocation is done using Perl and TCL/TKL. Shhhh. Don't tell anyone....
  27. 3 points
    A few reasons are... a - The introduction of logic hazards can cause glitches : https://en.wikipedia.org/wiki/Hazard_(logic) b - Routing of clocks is very complex - It is hard to ensure that the same clock edge appears all over the FPGA at almost exactly the same time. Sometimes this is achieved with 'slight of hand' (e.g. using a on-chip PLL to advance phase of the clock, so that by the time it reaches the edge of the chip is in back phase with the original signal). Low-skew paths also exist, but are restricted to small areas of the FPGA, and the clock has to be connected to the correct pin to be placed and routed correctly. c - FPGAs and their tools are designed to behave predictably under the "synchronous digital design" paradigm (something like https://hps.hs-regensburg.de/scm39115/homepage/education/courses/red/2_SynchronousDigitalCircuitDesignRules.pdf). If you work outside the paradigm you will be fighting against the tools and their assumptions. d - There is almost nothing that you are unable to code in an FPGA friendly way, but there are infinitely many ways to write FPGA-hostile code. If you want your FPGA to place nice with you, you have to play nice with it. So you can either add an RC filter to debounce you switch, or you can sample it using a reliable clock.
  28. 3 points
    Tempest2k8

    OpenScope Mechanical STL Files

    Printed out on the Form Labs at my local TechShop.
  29. 3 points
    jpeyron

    Cmod A7 35T GPIO demo Error

    Hi @coloradosensors, I just generated bitstream on this project in Vivado 2015.4. You need to right click on the clocking wizard and remove it. Then under project manager click on ip catalog and re-add the clocking wizard with default settings. This will fix your issues with using an older version of Vivado for this project. cheers, Jon
  30. 3 points
    D@n

    Lots of fun UART testing code

    Hello Digilent Community! I just finished putting the finishing touches on a UART demonstration project that you can find here. The project was originally intended to share a C++ class that could work with Verilator to prove that anyone's UART implementation was working. However, after I got into it, I realized the project had a lot of value that others might appreciate. As an example, consider this post by @martin16. Had he used any of the testing mechanisms listed below, he might have known which side of the RS232 port he was working with was at fault. The core contains a complete implementation of both a transmit and receive UART encoder/decoder. These can be easily taken from my project and placed within your own. (Subject, of course, to the limits of the GPL v3) The core also contains a (fairly) generic FIFO implementation. For those wondering how to implement a FIFO, you may find this valuable as well. For those who would rather interact with a serial port over a bus, such as the wishbone bus, there are two approaches within the project that can be used to hook it up to a wishbone bus. One can be used within a larger wishbone slave module, the second as a standalone module. Both are Wishbone B4 compliant, and both use the pipeline mode--allowing you to read/write multiple values on consecutive clocks from/to the controller. Of course, this only really makes sense when using the FIFO. Those might be valuable enough on their own, but you can probably find without too much additional work other implementations of the above. Therefore this project includes some even more valuable files: It includes a series of test programs/configurations that can be used to determine if the hardware on your board is working properly. If you are like me, you've struggled every time you've tried to get a serial port working on a new board. Should you connect your output to the TX or to the RX line? Do you have the UART set up properly, at the right baud rate? Can you handle more than just single values at once? How fast can you transmit/receive? To help you answer these questions, the project file contains the following test configurations: Hello World: You know, that old fashioned hello world program? I would recommend trying this program on your board after you can blink an LED at your favorite rate, or equivalently after you know that your clock works. This particular project is so simple that it depends upon only the clock input and the UART transmit output. Getting this program running on your board will demonstrate that you understand your clock, and that you can modify your I/O constraint file properly, and that you know how to connect a terminal program to your board in order to observe the results. Line Test: Once you've got a hello world program running, so that you know the output UART pin works, then it is time to test the input UART pin. This is the purpose of the line test testing program. It works by reading a line of data (either until a newline or 80--characters), and then dumping that line to the output. (Don't forget to turn off hardware flow control, and be aware of the differences between a new line and a carriage return!) SpeechFifo: Finally, there's a program that can be used to test the FIFO capabilities found within the wishbone UART peripheral. This program uses the FIFO capability to make certain the transmitter stays fully loaded for over a thousand characters of output bytes. (No, this isn't computer speech generation, but rather a computer dumping a Abraham Lincoln's Gettysburg Address across the UART port.) Each of these configurations has a corresponding Verilator simulation file associated with it, allowing you to simulate the functionality within them as part of Verilator. The project includes, like I mentioned above, a C++ class that can be used to determine if your own UART is transmitting correctly under a Verilator simuation. This class can also be used generate UART signaling in order to test if your RTL can receive it properly. (See the line test C++ harness discussed below for an example of this.) As complements to each of the testing configurations above, the project contains C++ files to drive each of those within a Verilator context. Some unique features include: The Line Test C++ test harness automatically generates a linetest.vcd file that can be used together with GTKwave to study how the core works. Further, it can be run in either an interactive or an automated mode. The Speech Test C++ test harness can be used in an automated mode, or with the -i switch in a more interactive mode. In this latter mode, the speech test program generates a speechtrace.vcd file that can be used with GTK wave to understand how the UART transmitter, FIFO, the wishbone bus decoder, or even the test harness itself. I hope you find these as valuable as I have. Please feel free to post any questions or comments you might have about this project below. Dan
  31. 3 points
    LariSan

    Birth of an OpenScope!

    We got a series of photos of the OpenScope going through the manufacturing line. Unfortunately, Kickstarter didn't allow me to load all of them onto the update.
  32. 3 points
    Hi! I've been playing with the low cost ESP8266 modules, that present a IP-over-WiFi as a serial device, and you use modem-like AT commands to control it. I've just put up a project that allows the FPGA to connect to my Wifi network, then send status message to a service that is listening on my Linux VM. It is all done using VHDL state machines (no software CPU), and could most probably be made a little more compact. Because the serial port is running at 9600 and the AT command based protocol overhead it is a pretty low bandwidth solution, but enough if you wanted to add some basic WiFi telemetry to a design. The ESP8266 module used was under $7 - http://www.seeedstudio.com/depot/WiFi-Serial-Transceiver-Module-w-ESP8266-p-1994.html You can find all the source on my Wiki at http://hamsterworks.co.nz/mediawiki/index.php/FPGA_ESP8266
  33. 3 points
    D@n

    Nexys 4 DDR

    @gnicholls, Wow, what a good and thorough question. You've hit the nail on the head, and you are asking something a lot of users are asking. So in answer, may I reply, Welcome to the wonderful world of FPGA design! DDR memory is hard. I mean, really hard. I tried for about two solid months to get a DDR3 memory up and running, and eventually moved on because it was taking too much time to do. You can still find the project here, though--and I still hope to return to it--eventually. Xilinx has written a variety of App notes describing how they've gone about creating their reference solution. For 7-series devices, you can find their note here--but it just doesn't tell you much. I've found the most useful information in their note from a couple generations back, found here for a Virtex-5. Bottom line: it's *really* hard--most people only use the reference solution, and then make the reference solution work for their design. I love the examples found at fpga4fun.com. They tend to work through many of the basic I/Os that FPGAs need to work with, and how to build controllers for each of them. Another useful website is Asic-World--it's just not one I've ever gotten into. Xilinx has tried to make your problem easier with their platform studio and now its Vivado replacement--allowing you to connect via point and click various different Xilinx components together to make one of many (fairly) pre-canned designs. Many of the Digilent based "tutorials" or "examples" are of this type. I personally find them wanting, for many reasons: They are "too easy"--offering you no insight for how they are accomplished internally. They are so much of a black box that you cannot examine what they did or how they did it in order to modify it, debug it, or even learn from it. It can be difficult to integrate your own work with their components. They are all focused on how to use someone else's components, but offer little in the way of teaching you how to build your own. In the end, they leave you stuck with Xilinx solutions. Any components you create/develop will only ever work with Xilinx. This leaves you forever wedded to the Xilinx platform, or forced to relearn all you have learned. Verilog (and <gasp> even VHDL) is a better language than that--capable of doing a lot more. And if that's not enough, your design that works with one version of Vivado may well break when the next one comes out because ... they changed something. (This is an ongoing problem, and a thorn in Digilent's side--suggestions are always welcome.) I have personally been trying to work to create somewhat of a solution to your problem, but I'll admit my own designs are perhaps far from the professor's materials that you are looking for. You can find many of my Verilog designs on github here. A recent design I've put together for both beginners and more experienced types alike can be found here. It contains examples of how to create a serial port, both transmitter and receiver, together with some top level designs that use such a port. As the task of figuring out which pin is which on any board is fairly common--even among experienced users, these offer examples you can work with to make sure you have your serial port working. My efforts have gone so far as to even build my own CPU, flash controller(s), SD-card controller, GPS controller, real-time clock, 7-segment controller, FFT, VGA controller, etc. I mean, why when you buy a board would you only learn to work with some of it, right? You can find a fairly complete design here, using a CMod-S6, that places a CPU onto the S6 with a minimal multi-tasking "operating system". I'm also working on a more complicated design for the Arty here--this one uses the Xilinx generated MIG DDR3 SDRAM, such as you have on your Nexys 4 DDR. This design is currently somewhat on hold, as I am trying to update the CPU within it to a more mainstream CPU that will even support the C-library. (Today's success: I managed to get newlib to compile for it! This is after updating the assembler, linker, GCC compiler backend, etc.) If you are a hard-core VHDL type, Xess.com has put together a fascinating library of VHDL routines to demo how to use their boards. To my knowledge though, the tutorial information within their libraries is ... a bit harder to follow than the simple point and click designs Xilinx peddles. One of the things I've noticed about many (most, all?) of the more complicated FPGA designs I've come across is that they all depend upon some form of internal bus by which things can be connected. Once you get past learning about how to build the simple peripherals fpga4fun wishes to teach you, you're next step is really to learn about that bus structure. Why? If for no other reason than memories seem to be best accessed via a bus, so anything using a DDR type of memory tends to send its requests over a bus. This can easily become a bottleneck to your design, but ... it sort of comes with the territory. You can build other memories and distribute them throughout your FPGA, but the amount of block RAM memory you will get within any FPGA tends to be ... never enough. Hence you are often stuck with the external memory chip(s). Xilinx uses the AXI bus protocol. You can find the specification for it here. I haven't found any good tutorials on how to use it, but there's a way you can get Vivado to generate a sample AXI-lite design that you can interface with. (I can google it if you are interested--I just don't have it at my fingertips.) I've personally used the Wishbone Bus protocol, version B4, pipelined mode. Many others use version B3. I find that I can transfer data 3x faster using B4. To get from the Wishbone Bus to a DDR memory, controlled via Xilinx's Memory Interface Generated AXI controller, I built a wishbone-AXI bridge. Others of these also exist. There's an open source package manger out there called fusesoc which was designed to facilitate composing solutions from many different FPGA components together. In particular, the OpenRISC team has put a lot of work into making sure their CPU's, peripherals, and board designs can be built using this package manager. (These tend to connect to each other via the wishbone B3 standard.) If you dig into this, you can probably find many, many examples of working peripherals for various boards--although that community does tend to focus more on the Altera boards than the Xilinx boards, and Verilog more than VHDL. So ... when I build a new design, how do I do it? For every board of Digilent's that I have bought, I start with the reference page, look up the schematic to see how the components are connected, and then google the part numbers on the schematic. Those will contain the instructions you need to access the various chips on your board. They are usually where things pick up next after you leave the canned tutorials and examples. I hope I haven't overwhelmed you, but really ... where you go next is up to you. What would you like to do? Dan P.S.: My favorite description of RTL design for those who know nothing about FPGA's is, "Infuriatingly complex in its simplicity." Everything you do will be simple--like the clock divider. But too many of these very "simple" components can become so complex that it very quickly gets under your skin.
  34. 3 points
    Although this isn't using a Digilent FPGA board, here is how to drive a low-cost stepper motor and to count the steps taken. It is using a 5V stepper motor, but if you have 12V motor & driver board it may also work for you. http://hamsterworks.co.nz/mediawiki/index.php/Stepper
  35. 3 points
    prince, I recently ran into the same issue. You can follow this tutorial to put your program in the flash. BKallaher
  36. 3 points
    Bianca

    Is there an arty drawing available?

    Hi Gra, Please see the document attached. Best regards, Bianca Arty Dimensions.pdf
  37. 3 points
    Hello, The 16 inch cable length limitation of USB 2.0 is for data transmission signal integrity. In case you need more than this you use up to 5 USB hubs. The Analog Discovery needs about 400mA (2W) to function, less than the 500mA USB 2.0 limitation at 5V. Most computers can provide more than 2A without any problem (like external HDDs need this to spin up), having the surge protection above this limit. However long and/or bad quality cables have high resistance and the voltage will drop too much on the device side, below the ~4V minimal requirement for the AD. http://goughlui.com/2014/10/01/usb-cable-resistance-why-your-phonetablet-might-be-charging-slow/ There can be huge differences between cables. The best cable I have is a thin unshielded 6 feet one, some others are thick and looking good but have way more resistance. It seems the plug contact resistance is a very important factor since these can oxidize easily. With a good cable I see 0.1V drop (4.9V), with other bad ones up to 0.8V (4.2V) when using with AD taking 2W. Try using different USB cables, check the device voltage in the WaveForms application status bar. You can also try the Analog Discovery 2 which can be powered from 5V auxiliary supply.
  38. 3 points
    You want to use TMDS_33 - for example: set_property -dict { PACKAGE_PIN Y1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; set_property -dict { PACKAGE_PIN W1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; set_property -dict { PACKAGE_PIN AB1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; set_property -dict { PACKAGE_PIN AA1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; set_property -dict { PACKAGE_PIN AB2 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; set_property -dict { PACKAGE_PIN AB3 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; (this is from an Artix 7 project for the Nexys Video, so you will have different pin locations - but you get the gist - it is TMDS_33)
  39. 3 points
    D@n

    Reprogram (reset) FPGA

    Actually, resetting/reprogramming the FPGA from within the internal logic of the FPGA isn't as hard as it sounds--once you figure out how to do it. Check out the project wbicapetwo at opencores. On there you'll see a core that can be used to access the internal ICAPE2 port within a series 7 FPGA. I use it on my Basys-3 board (w/ Artix 7 FPGA) to reset the board from internal logic. All it takes is to write a 15 (IPROG) to the command address, 0x04. The FPGA will then reload its configuration. Should you wish to load an alternate configuration, load the address of that alternate configuration on your flash into the WBSTAR register, found at address 0x010, and then issue the IPROG command. You can find further documentation from Xilinx. However, Xilinx's manual is sparse on the timing of this operation, and the core at opencores resolves that. D@n
  40. 3 points
    tom21091

    Reprogram (reset) FPGA

    Hi Alexis, Unfoortunately, the program_b pin is only tied to the PROG button, and not to the FPGA. You can drive it with a Pmod port very easily though. Just take a wire and stick it under one of the bottom two feet on the PROG button. Put the other end into a Pmod port. In your .XDC file for your project, add a pullup to the port. set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP TRUE} [get_ports { ja1 }]; Now you just pull ja1 low when you want to reprogram through QSPI. Make sure JP1 is on QSPI.
  41. 3 points
    I'm working on a design for receving HDMI video and decided to write up my method for tuning the IDELAY and ISERDES settings to sync with the incoming stream. If you are interested, you can find it at http://hamsterworks.co.nz/mediawiki/index.php/SERDES_symbol_locking
  42. 3 points
    mwingerson

    Help With A Zybo Video Design

    Hey Run, Where did you get the demo? I would like to see what you are working from. 1. I suspect you just need to change the clocking wizard that feed the dvi2rgb core to 75MHz instead of 200MHz but I cannot be sure without poking around a little. Although, I have only ever used one ucf/xdc file per design so I am wondering if you are having issues with that. I could see how using multiple files could work but I don't have any experience with it. As for your errors, "[Common 17-55] 'set_property' expects at least one object. " error is caused by a mismatch between the defined port in Vivado and the xdc. In this case, I would get rid of the "dvi2rgb.xdc" and the "dvi2rgb_ooc.xdc" files and rely on the zybo master xdc. Then I would change the zybo xdc to match the port names that are attached to the dvi2rgb core. 2. I'll ask around but I think you should have one universal XDC. 3. Make sure to change the XDC to reflect the port names you used. 4. Do you mean you tied them by outputting them to a pin and using a wire to put them to VDD or GND? That isn't a good idea. Those pins are being driven as outputs and driving them to VDD or GND could short them and damage the pins. On inputs that would be fine but I like to tie the signals to a switch or button. On outputs, leave them unconnected. Hope this helps. Marshall
  43. 3 points
    hamster

    My Favorite Digilent Product...

    Prompted by Amber's blog post, https://blog.digilentinc.com/index.php/my-favorite-digilent-product-the-uno32/ here's mine - and it is most probably not the one you might expect. It is Part# 240-004P - the 6Pin Header & Gender Changer. I push them into breadboards for making solid off-board connections, They let me clip on scope probes onto PMOD sockets for debug outputs, I can attach the flying leads from my Logic Analyser to any 0.1" female connector. They they are multi-platform, working with nearly all dev boards from all suppliers. They are truly awesome. And they even act as gender changes for PMOD cables. I wish I could get millions of these, in nice 40-way long strips. At the moment they are like hen's teeth, as a lot of them have found semi-permanent use on projects around the place.
  44. 3 points
    All, First post, so may I say hi and introduce myself I've long been into electronics and good old DIY dabbling, took a course in "Applied Computing and Electronics" at Bournemouth Uni in the UK which was a bit of everything from VHDL, circuit layout/design and 8051 programming to some C++, Java and C#. Since then I've gone from creative fun programmer to boring paper pusher manager in the hunt for something to label a career. Along came the little Uno32 and the Motor Shield for some of that home hobby messing about I've so missed - boy is it good to be doing it again! :-D So some more background - many years ago my dad and I effectively retrofitted a highly accurate drive system to a telescope mount for astro-photography, this had a DC servo motor drive unit at the heart and back then (12 years now) that little magic box cost well into the triple figures. Before the days of my training, the insides of that box were simply black magic. Fast forward to now and just for fun I wanted to see what a sub £50 bit of kit, a la the Uno32 and some rusty knowledge could do to imitate that once mysterious and extortionately priced system. Well, its not exactly stellar, but I'm quite chuffed with what I've done so far. Lots of googling, lots of libraries downloaded and fiddled with and some slightly oddball approaches to the motor control and I have something that, despite the rambling, may be of interest to others. Basic Description: Uses the ChipKit Uno32, the Motor Shield, a 9V 3A supply for the shield and a Maxon 12V 3.8:1 gearmotor with 512CPT encoder (£25 off eBay). Just the one motor so far, though 2 should be simply a few extra lines in the sketch. Libraries that have been used include the SoftPWMServo, modified to run at 30KHz (20KHz still made some audible wine) and accept a range of 0-65535 (finer control, in theory). Checked the output on a scope at work and it looks pretty darn accurate for a software 30KHz PWM - I'm impressed :-) Not clear if I am allowed to post links here, but a google search will take you straight to the library. Another library was the Arduino PID Library, modified to match changes to SoftPWMServo accepting a range from 0-65535. A bit of code was stolen from one of the MPIDE examples to assist with serial data parsing so a few commands can be sent over the serial port to set either position or velocity. That came from the BasicSerialParser example in Communications. Motor Control: Control is somewhat odd, my own thinking but I completely expect by no means original! I drive the H Bridge completely backwards. By this I mean I keep the enable pin high, and send the PWM through the direction pin. This is probably considered completely mental, but it has a few interesting benefits (IMHO). Before PID, I was seeing how slow the motor would turn before stalling using just open loop PWM. This is of interest (to me) because having a large dynamic range is useful for telescopes - sloooow tracking but speedy slewing to an object. Driving the H Bridge in this alternate way definitely allowed me to drive it slower by about 3 fold compared to driving the H Bridge normally. Similarly, holding torque is improved since in 0 position the motor is not actually off, but oscillating constantly. The motor does obviously get hot though since it is constantly being driven at max duty cycle just in different directions all the time! No magic smoke released, so it seems the H Bridge copes with it OK - I'll let you know if it changes! Having said all that, the motor wasn't exactly great on torque (its only 22mm as it is and under driven at 9V for a 12V motor). The "steady state" PWM value for the motor is 32767 (effectively 50/50 duty cycle in forward/reverse resulting in 0 angular velocity), 0 sets max reverse speed and 65535 sets max forward speed. Now with PID thrown in the mix that forward/reverse control of the oddball H Bridge driving makes things really easy. Oh, PID is just brilliant by the way. Hopefully the sketch attached shows how simple it is to throw a PID algorithm in there, and it ends up allowing for some really cool control. Position (not worked out how to allow for going negative yet) is between 0 and _alot_. It is just a case of setting a "setpoint" of encoder pulses as the desired position, throwing in the current encoder pulses when you sample and letting it the PID do its thing. Its crazy, holding torque at any position is stupid - the thing feels alive and fights with you. The more you try and turn it, the more you are deviating it from the setpoint and so the more the PID injects as an offset to fight with you, really is quite cool. I've seen loads on how to do velocity online and people seemed to find it difficult, so I've probably done this completely wrong as all I do is keep count of the last encoder pulse sample value and sample time and then when you next sample you can work out how many pulses you are doing in a specified time frame. You use this and the desired value for the PID and it then ensures the speed is kept. The encoder counter is using an interrupt timer and set within the sketch. Pretty straight forward logic but I think it might be slightly floored, or I am missing counts or something as I can't quite yet get the thing to 0 at the same point repeatably. At fully chat its doing about 170KHz encoder pulses though so not bad going. The default PID values I'm using (20,400,0.2) are interesting but work well. The velocity goes down to about 20RPM smoothly, 10RPM it does but not happily - 4000RPM is the max it will do at 9V and it appears the encoder counting is keeping up (I had a poor(er) implementation before and when it started missing counts behavior went haywire). Pretty good dynamic range I think. Dialing in a position is great - snaps to it with no hesitation although need to work out why the lack of really precise repeatability. Next things to do are to try and work out how to do a position+velocity move which is proving a head scratcher. Then I think its time to tidy it up and put it into something a bit more manageable and start thinking about wrapping it with some stuff to make it useful for actual telescope mount control. Anyway, I must say apologies for such a rambling first post. It kind of befits my enthusiasm for this little thing, so nice to be back in the thick of a bit of hardware with wires hanging out of it and led's flashing away and the like. If anyone is genuinely interested in progress with this let me know and I'll keep this updated. PS: The sketch probably won't build! It requires the libraries mentioned above, but I did modify them a bit so some of the variables will have type changes. I could package the whole lot up as a zip but I honestly don't know where I'd stand with GPL licenses and the like so any problems shout and I can explain what I did. Hopefully there are some useful scraps in there for others to use if nothing else :-) ... UPDATE: I am not permitted to upload pde files, which is fine (not grumbling - just noticed the error when about to hit submit). I'll still post this so if anyone is interested for the sketch or the encoder counting code or whatnot let me know I guess I am allowed to post code snippets of my own in posts? Thanks all! Chris
  45. 3 points
    hamster

    Nexys3 Best Practice for Unused Pins

    Hi! By default the tools configure all unused I/O pins are configured with a weak pull-down on them (I'm away from my laptop at the moment so can't verify what I am saying, but I am a little bit sure that it is pull-down) So you can either: * change the "Generate Bitstream" properties to change this default behaviour (IIRC the other options are either pull up, pull down or floating). * Define the anode pins and force them to turn the display off * Ignore it, and consider it a feature. Mike
  46. 3 points
    Serge.V

    Welcome!

    Hi all, My name is Serge, I work for MIPS (now Imagination Technologies) doing simulators for verification. Microcontrollers are my hobby, and I have several pet projects, like: RetroBSD, LiteBSD, QEMU for pic32, pic32sim, pic32prog and ejtagproxy. I use Max32, WF32 and WiFire boards, and some pmods. Thank you.
  47. 3 points
    Syntax_Error

    Welcome!

    Hi, all. My name is Matt and I am a hobbyist and also an electronics technician by trade. I own a Digilent Analog Discovery w/BNC adapter board, and a Nexys2-1200 w/parallel LCD, also from Digilent. I use TINA and Waveforms, and have the Analog Parts kit and Mastech DMM in your product line. I have worked through most of Real Analog, and all of Real Digital, and have both Digital Design books by Haskell, and the FPGA book listed on your website. I have used your products and worked through so many of your materials and recommended books because as I have tried each one, I have found it to be a top notch quality resource. My personal favorite *BY FAR* is Real Analog. I do not know the instructor's name, but kudos to that man for clarity of instruction. I have learned much from him. Give him a raise! I list all this out to give you a bit of background on me before I say this: Please continue making educational materials. Your Analog Discovery product is awesome, but it was Real Analog that elevated me as a technician and budding engineering student and made me want MORE. Real Digital was good, too. There are tons of "entry-level" educational materials on the internet, but they all share a common lack of depth and mathematical rigor. Real Analog was a massive breath of fresh air. As someone who has a casual understanding of calculus, and no idea what a differential equation was when I started Real Analog, I was impressed at the depth of material and simultaneously the ease of learning that the program provided. It made me Google and Youtube things like "Complex Impedance" and "Phasor Diagram" and "Solving Differential Equations", something I had never done before. For the marketing folks here, I would emphasize the value in having educational materials using your products, akin to the Real Analog-Analog Discovery dichotomy. Make a program teaching microcontrollers (with rigor!) using your ChipKit products. Make a digital course using Basys or Nexys products (or either/both!). That's why I got Haskell's books with my Nexys2, and also why I bought Pong P. Chu's book instead of another FPGA book. I had a lab in my hand that the *book used*. If you build it, they will come; and buy the accessories, to boot. P.S. Thanks for everything your company has done. You're awesome, and I recommend you to every amateur, student, hobbyist, ham radio operator, and some professionals that I know.
  48. 3 points
    I just got this up and running: http://youtu.be/dIAJrQxToCc It's a custom TFT LCD controller board using only two PMODs. The board controlling it is an FPGA devboard that communicates with the host computer using the FTDI's FT2232H in synchronous FIFO mode so that I can transfer data between the host and board at a rate of about 25MB/s using a simple protocol. I wrote a scripting tool that glues together wishbone cores to create an FPGA image using a simple configuration file. Editing configuration files are great but I thought it would be so much better if I could modify the FPGA image by using a GUI so I worked on an application that does that. Here is a screen shot of how I visually created the LCD controller. One of the big limitations of using USB 2.0 is the relatively large overhead to initiate a transaction, It's much faster if you send a large chunk of data. So instead of writing directly to the LCD controller I write to the SDRAM and then configure the LCD controller to read directly from the memory. This way I can write a new frame down to memory while the LCD controller is reading data out using a double buffer scheme (host writes to back, controller reads from front, then flip). The protocol to communicate with the FPGA is a really simple protocol abstracted away in Python to simply 'read' and 'write'. It was pretty cool to communicate with the FPGA using a python module but I thought it would be so much better if I could interface with an FPGA using a GUI. So I added a visual interface to communicate with it (That's what I was using in the video). If you're interested in the board here's the link: http://wiki.cospandesign.com/index.php?title=Dionysus the code to control the LCD is here: https://github.com/CospanDesign/nysa-verilog/tree/master/verilog/wishbone/slave/wb_nh_lcd The code is designed to be as generic as possible, so if you want to adapt it to your project it really just needs a wishbone bus but you can bypass Wishbone by just using the nh_lcd.v
  49. 3 points
    Cristian.Fatu

    Pmod Tmp3 Pin Distances

    Find attached a drawing with the dimensions. PmodTMP3_mech.pdf
  50. 3 points
    Hello! So here is my entry for Digilent's Halloween contest. This is my first time programming in MPIDE and doing something of this nature with microcontrollers, so I put a lot of hours into researching and getting it to work the way that I had planned (with quite a few setbacks along the way). A PIR sensor activates a servo attached to the doll's head, a digital voice recording module with a creepy audio clip, and some LEDs for the eyes. It's running on the chipKIT Max32. I will follow up with a link to an instrucable when I have time to hammer that out. I had a lot of fun doing this and learned quite a bit. Below are some different youtube vids displaying the doll! http://youtu.be/hjpHrV_7POU Here's a video of the completed doll. http://youtu.be/AHtMbCk0-c4 Gotta love slowmo http://youtu.be/1MZ9VPrGxOY Testing phase to make sure all of the parts are working as intended.