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Showing content with the highest reputation since 07/20/19 in all areas

  1. 2 points
    There is no code to draw any shape as you observed since it was/is a work in progress. Thus it was excluded by default from `rootfs`. However it was mentioned by mistake in the first link you mentioned. https://reference.digilentinc.com/reference/software/petalinux/start The issue has been corrected.
  2. 1 point

    DMC60c Default Settings

    Default Device ID is 0, Current limit is disabled, continuous current limit 40A, peak current limit is 60A, current duration is 500ms. There is no voltage limit? All parameters and their defaults can be found in the DMC60C CAN Protocol Guide.
  3. 1 point

    Vivado sysnthesis fail..Pcam

    A new monitor solved the problem. Resolution problem. Thanks for your help! i now can practice on the Zybo!
  4. 1 point
    Hi @Andras A. Comparing two different tools might not be the best option, it could give different results. B. At the moment the Impedance Analyzer interface takes control over the Supplies and DIO lines to control the IA Adapter. On the Adapter the negative supply and some DIO lines are unused. In the next software version I will add option to be able to control these. Having these you could use a small signal relay with ~5V control, similar to the ones on IA adapter but non-latching, to switch between the measured and control DUTs. https://reference.digilentinc.com/_media/reference/instrumentation/analog_discovery_impedance_analyzer_sch.pdf Edit: You could use the current software for plan B. First, in the Impedance interface using the Adapter option select the needed resistor value, then select "W1-C1-DUT...". This will release the Supplies and DIO lines to be used from other interfaces, and the latching relays on the Adapter will remain unchanged. Then you can use the Static IO or Negative supply for other purposes, to control the external relay...
  5. 1 point
    Tim S.

    Pmod OLEDrgb with Zybo Z7

    Just to make sure my explanation is thorough. The above has a typo. It should read: Linux has a case-sensitive file system whereas Windows has a case-insensitive file system.
  6. 1 point

    DMC60c CAN Bus

    Hi opethmc, The current and voltage information is reported by the DMC60C every 100ms (by default) in the STSANALOG (0x020614C0) frame. This info can be found on page 28-30 of the CAN protocol guide. Fault status can be found in byte 4 (fs2) in the STSGENERAL(0x02061400) frame that is sent every 10ms (by default). You can find the fault counts by reading parameters 51 through 57. This can be done by sending PARAMREQ (0x02061800) frames containing the parameter you want to read, then scanning for a PARAMRESP(0x02061840) packet. This info can be found on page 12-28. Hope this helps! Tommy
  7. 1 point

    GPS Pmod

    Hi @cepwin, I'm glad you we able to get to the bottom of the issue. Thank you for sharing what happened. cheers, Jon
  8. 1 point

    GPS Pmod

    That you Dan! I did a little googling over lunch and realized there's a very simple/stupid reason I'm not getting a signal....I don't have the GPS module....I see Digilent sells one a long with some other sensors/etc. that work with the Arty s7. Those could be fun to play with. I did create a full Microblaze with memory and UART and that appears to be good. I just have to fix the code to use the UART library for that rather than the simple Microblaze that my class example used. What I realized is Vivado will generate the necessary headers based on your design, I also want to thank Jon again for his help as well. I have learned so much working this issue.
  9. 1 point
    Hi @m72 In this high resolution capture it looks like SDA is rising while SCL is still high. To overcome such situations lower the sample Rate, to 100MHz or lower. This way it will likely capture SDA and SCL change at the same time, which should be interpreted correctly. Note that the setup time for Stop condition is no respected:
  10. 1 point
    https://www.digikey.com/product-detail/en/on-semiconductor/FDV301N/FDV301NCT-ND/458954 It's Q9 on the last page of the schematic. This is for Rev. C.
  11. 1 point

    GPS Pmod

    @cepwin, There's a real easy way to debug whether or not you are getting a fix or not. Remove the FPGA design, and replace it with a pass through from the GPS UART transmit pin to the FT2232 UART RX transmit pin. You can then use your favorite terminal program, mine is minicom some like teraterm, to examine the NEMA stream produced by the GPS device. It's typically 9600 Baud, 8 data bits, no parity and one stop bit. It's also pseudo-human readable--line upon line of CSVs--you should then be able to tell if you are getting lock or not. I see no reason why you wouldn't be getting lock from your upstairs bedroom. Also, for your security, you probably don't want to paste the NEMA stream coming out of the device here for discussion--since it may well reveal the coordinates of your bedroom. Dan
  12. 1 point
    This little project might give you some ideas - it controls the speed of the dev board's fan based on the XADC reading. It also uses no IP blocks so everything is exposed. http://hamsterworks.co.nz/mediawiki/index.php/XADC_Fan_PWM
  13. 1 point

    Custom IP

    @PoojaN, You're not the first person who has asked this. If you just want to blink an LED, then I'd recommend a different approach that avoids all the pain with AXI in the first place. (You don't need AXI ...) If you want to start interacting with AXI cores, then you'll need to learn AXI. Sadly, this isn't as simple as it sounds. Xilinx picked the AXI bus to connect all their components with. This may have something to do with their ARM integration, since if I understand correctly AXI is an ARM creation AXI is not a simple bus to work with. Unlike Wishbone, it has five channels associated with it each of which can stall. These are the read address channel, the write address channel, the write data channel, the read response channel and the write response channel. One bus failure, and your device will lock up. In my experience, using an ARM+FPGA chip, lockups could only be fixed by cycling the power leaving you ever wondering what had caused the problem. Part of the problem is that the AXI standard has no way of recovering following a dropped response other than a total system reset. As I've implemented Wishbone, you can just adjust one wire (the cycle line--but that's another story) and start over. You can even use a timeout to clear the bus if a peripheral has not responded within an expected period of time. Not so with AXI. AXI is so difficult to work with that not even Xilinx could get it right. (See the links above) When I first discovered these bugs, I wondered that no one had found them before. For example, two writes in a row would lose a response and lock up the bus if ever there was the slightest amount of backpressure on the return channel. (Something Wishbone doesn't have to deal with, since there's no way to stall a Wishbone acknowledgement) It would seem as though very few individuals ever simulated their cores with backpressure (i.e. either BREADY or RREADY signals low), and so they never noticed these bugs. Similarly, some configurations of the interconnect might trigger the bugs while others wouldn't. Imagine adjusting the glue that holds your design together only to find your design starts failing. What would you blame? The interconnect, right? When in fact it was their demonstration core logic at fault that everyone was copying. I've now fielded several questions in the last several months alone on Xilinx's forums from users who've struggled with these bugs. If you do searches, you'll discover that folks have been struggling with these sorts of problems ever since Xilinx started using AXI. In one recent post, a software engineer posted that his FPGA engineer had left, leaving them with a "working" design. He then adjusted the software within the design and the whole design now froze any time he tried to write to their special IP core twice in succession. I'm hoping Xilinx will fix these bugs (soon). I haven't checked their latest release since reporting them, but I do expect them to fix the bugs in the near future. It's not just Xilinx either. I'm currently verifying the (ASIC) soft core of a major (unnamed) vendor. Much to my surprise, despite a team of highly paid professional engineers working to produce this amazingly complex core , and despite the fact that they created a simplified subset of the AXI interface standard to work with ... they still didn't get the AXI interface right. Realizing how difficult this was, I tried to simplify the task by creating a couple of cores. One showing how to build a bug-free AXI-lite slave (link above), another showing how to build a bug-free AXI slave (link above again). I also shared an AXI bridge implementation that, if you place your core downstream of it, you'd be guaranteed to meet the AXI protocol--even if it slowed you down a touch. I also shared the code for verifying that an AXI-lite component works--you are free to try it out yourself to know if your core still works after changing it. If you like using Wishbone, I've posted an AXI-lite to Wishbone bridge, or even a Wishbone to AXI bridge in case you want to access your DRAM memory. I also think you'll find that all of these cores, save perhaps the bus fault isolator core, will have better performance than Xilinx's logic ever had. Whether or not you use these options (or give up on AXI as I've tried to do) ... well, that's up to you. Forget what the sales brochures tell you, we aren't playing with legos here. There's more required to hook things together then just plugging them into each other--especially if you want something that works reliably when you are done. Just want something simple? Learn Verilog or VHDL. At least then you'll be the one responsible for your own bugs. Dan
  14. 1 point

    Zybo Z7 Pcam 5C Demo - Warnings

    Hi @Azzor, Welcome to the Digilent forums. I downloaded the zip file for Vivado 2017.4 from the release page here. I opened Vivado 2017.4 cd'd to the correct folder and opened the project. I then generated a bitstream without issue. I have attached a screen shot of this. Are you using a different version of Vivado? Best regards, Jon
  15. 1 point
    Impedance Analyzer v1.3.0.43 available for Download Currently, it only works with AD1 (cf. EEVblog AD2 not working with this great S/W). Would be great to get some advace from Digilent ,-) Best Ulli
  16. 1 point
    Bare metal is a stand alone program that runs on the PS without an operating system and is developed and deployed though Xilinx SDK. With Linux, you run Linux on the board and write a regular Linux application using the Linux toolchain. I suggest you read up a bit on both and see which you prefer.
  17. 1 point
    The error is because the magnitude as to be one bit longer than the inputs, (as the magnitude of (0xFFFFFF, 0xFFFFFF) is 0x16A09E4, which will overflow if you put it into a 25-bit signed value. It will however fit nicely into a 25-bit unsigned value, and as it is a magnitude it will be positive. So maybe snip off the top bit in the assignment, but remember it is unsigned!
  18. 1 point
    Using a tool for what it is meant to do is easy. Using a tool for something where it isn't suited, that is where the learning begins! (I now goes back to doing dental surgery with a steamroller, or maybe digging a tunnel with a teaspoon).
  19. 1 point

    GPS Pmod

    Hi @cepwin, Have you added the Vivado library to your Vivado 2019.1 installation? You can do this from inside Vivado by Choosing settings in the Project Manager in the upper left, expand the IP selection in Project Settings and choose Repository. You can then add in the path to the Vivado-Library from Digilent (which you can download from our GitHub here). This should let you generate the bitstream. Otherwise, you don't need to open up Vivado at all. If you have a fresh project you can open Xilinx SDK 2019.1, choose the workspace folder when it prompts you as the sdk folder source (as an example, mine is C:\Users\jcolvin\Documents\VivadoPrj\Arty-S7-PmodGPS_Vivado_2019_1\Arty-S7-PmodGPS_Vivado_2019_1.sdk) and wait for SDK to finish loading the workspace. When it is completed, you should see the hardware platform_0, the PmodGPS application folder, and the PmodGPS_bsp. You can then click the Xilinx tab at the top of the GUI, and choose to program the FPGA with the bitstream it finds. You will then want to connect to your board with your serial terminal of choice (I used TeraTerm) otherwise you won't see anything printing out. I then right-click on the PmodGPS application folder and choose Run As->Launch on Hardware (System Debugger). I then see the data printing out on the serial terminal. Is this what you did for your project? Thanks, JColvin
  20. 1 point
    Oh, a quick hack of a CORDIC magnitude library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity magnitude is Port ( clk : in std_logic; x_in : in std_logic_vector; y_in : in std_logic_vector; x_out : out std_logic_vector := (others => '0'); y_out : out std_logic_vector := (others => '0'); magnitude_out : out std_logic_vector := (others => '0') -- Accurate to 5 bits or so ); end magnitude; architecture Behavioral of magnitude is type a_x is array(0 to 5) of signed(x_in'high+1 downto 0); type a_y is array(0 to 5) of signed(y_in'high+1 downto 0); type a_x_delay is array(0 to 5) of std_logic_vector(x_in'high downto 0); type a_y_delay is array(0 to 5) of std_logic_vector(y_in'high downto 0); signal x : a_x := (others => (others => '0')); signal y : a_y := (others => (others => '0')); signal x_delay : a_x_delay := (others => (others => '0')); signal y_delay : a_y_delay := (others => (others => '0')); begin magnitude_out <= std_logic_vector(y(5)); x_out <= x_delay(x_delay'high); y_out <= y_delay(y_delay'high); process(clk) begin if rising_edge(clk) then if x(4) >= 0 then -- x(5) is not needed y(5) <= y(4) + x(4)(x(4)'high downto 4); else -- x(5) is not needed y(5) <= y(4) - x(4)(x(4)'high downto 4); end if; if x(3) >= 0 then x(4) <= x(3) - y(3)(y(3)'high downto 3); y(4) <= y(3) + x(3)(x(3)'high downto 3); else x(4) <= x(3) + y(3)(y(3)'high downto 3); y(4) <= y(3) - x(3)(x(3)'high downto 3); end if; if x(2) >= 0 then x(3) <= x(2) - y(2)(y(2)'high downto 2); y(3) <= y(2) + x(2)(x(2)'high downto 2); else x(3) <= x(2) + y(2)(y(2)'high downto 2); y(3) <= y(2) - x(2)(x(2)'high downto 2); end if; if x(1) >= 0 then x(2) <= x(1) - y(1)(y(1)'high downto 1); y(2) <= y(1) + x(1)(x(1)'high downto 1); else x(2) <= x(1) + y(1)(y(1)'high downto 1); y(2) <= y(1) - x(1)(x(1)'high downto 1); end if; if x(0) >= 0 then x(1) <= x(0) - y(0)(y(0)'high downto 0); y(1) <= y(0) + x(0)(x(0)'high downto 0); else x(1) <= x(0) + y(0)(y(0)'high downto 0); y(1) <= y(0) - x(0)(x(0)'high downto 0); end if; if y_in(y_in'high) = '1' then x(0) <= signed(x_in(x_in'high) & x_in); y(0) <= signed(to_signed(0,y_in'length+1)-signed(y_in)); else x(0) <= signed(x_in(x_in'high) & x_in); y(0) <= signed(y_in(y_in'high) & y_in); end if; -- Delay to output the inputs, so they are aligned with the magnitudes x_delay(1 to 5) <= x_delay(0 to 4); y_delay(1 to 5) <= y_delay(0 to 4); x_delay(0) <= x_in; y_delay(0) <= y_in; end if; end process; end Behavioral; Chaining the two together, and it seems to work. Top trace is the input, second trace is the delayed input, Third is the delayed output of the Hilbert filter, and the last is the scaled magnitude of the complex x+iy signal. NOTE: I know for sure that these are buggy, as they have range overflows), but they should give the idea of how @Ahmed Alfadhel could be implement it. magnitude.vhd hilbert_transformer.vhd tb_hilbert_transformer.vhd
  21. 1 point
    Szia @Andras The wide/narrow trace toolbar can be toggled with this button and Import is added for the analyzers. https://forum.digilentinc.com/topic/8908-waveforms-beta-download/
  22. 1 point


    I'd recommend you spend a working week "researching" the electrical-engineering aspects. The ADC may look just as an afterthought to DSP but it will require significant engineering resources (plan for several / many man-months). Long is the list of bright-eyed students / researchers / engineers / managers who have learned the hard way that there is a bit more to the problem than finding two boards with the same connector... Hint, check how much latency you can tolerate and research "digitizer" cards for PC (or PXI platform). If you don't need a closed-loop real-time system, don't design for a closed-loop realtime system.
  23. 1 point

    Zybo Z7020 SDK Programming Issue

    Yes, it's a 7020. I was able to get things working by power cycling the device. I was under the impression that changing jumper positions for boot device (JTAG vs. SPI) was enough to do between flashing the FPGA. I found that power cycling the device with the jumper in the JTAG position, and then flashing the device fixed this issue.
  24. 1 point

    Project Archive in Vivado

    Hi @Antonio Fasano, Here is the xilinx recommended approach for sharing and archiving SDK that should be helpful for eliminating multiple hw platforms as well as having to use the same folder name. best regards, Jon
  25. 1 point

    Correct Battery for PmodGPS

    Hi @stefantimm, We have added a CR1220 to the Pmod GPS. I will pass on your reference manual suggestion to our content team. Here is a forum thread that discusses the height of the battery as well. best regards, Jon
  26. 1 point
    Szia @Andras For this you don't necessarily need a script. In the interface you can set constant frequency (Start = Stop), specify a long Settle time and press Single. Like the following will run for 50 minutes, 100 samples at about 2/min rate, 30s + a few milliseconds due software processing.
  27. 1 point

    Enevlope Detection using FPGA board

    @hamster, Not bad, not bad at all ... just some feedback for you though: The "official" Hilbert transform tap generation suffers from the same Gibbs phenomena that keeps folks from using the "ideal lowpass filter" (i.e. sin x/x) You could "window" the filter to get better performance, or you could try using Parks-McClellan to get better taps. There are tricks to designing filters with quantized taps as well ... however the ones I know are ad-hoc and probably about the same as what you did above There's symmetry in the filter. For half as many multiplies you can take sample differences, and then apply the multiplies to those sample differences. Other than that, pretty cool! Did you find anything useful to test it on? Dan
  28. 1 point
    Hi @Lesiastas The FDwfDigitalUart,Spi,I2c functions like WF app Protocol perform most of the protocol decoding in the device, storing only the needed samples, without time marks. In order to have the signals in time see the DigitalIn_Trigger.py or DigitalIn_Record.py and decode the data like it is in the LogicAnalyze custom example:
  29. 1 point
    You can find newer version in the description of the video: https://www.youtube.com/watch?v=4d3hc-9zBaI
  30. 1 point

    Petalinux kernel panic error

    Follow our instructions here especially the section Configure SD rootfs.
  31. 1 point
    @sungsik, So let me shoot in the dark and ramble and see if it helps clarify your question. There are many ways you can design things on a Zynq. You can create state machines like you did before on the Spartan 6, making logic just like before that will work without a CPU. Indeed, you can still control I/Os like before if you want. The AXI GPIO core may be nice, but it is certainly not required. You can create AXI slave cores. Anything you create with a slave interface can be connected to the ARM in the Zynq and can interact with the ARM. This is typically very useful for controlling peripherals from the PS. You would write software commands to interact with your device, and off you go. This might be the easy way to interact with the AXI GPIO, but it is by no means the only way. There's also a discussion to be had about where the O/S / Application division will be within your software and how to write a proper device tree entry for IP cores that will be controlled from Linux. You can also create AXI master cores in PL. Your AXI masters can then be used to drive AXI slaves. So, for example, if you wanted to control the AXI GPIO as a state machine on board, all you would need to do is to connect an AXI master to it to do so. This would apply to any DDRx SDRAM as well. Yes, it is possible to connect an AXI master to multiple slaves, this requires an interconnect however. Which method you choose is up to you, the designer, and the specific and particular needs of your project. For example, logic is limited but fast, whereas software tends to be abundant but not nearly as fast. Further, most CPU software will produce (fairly) unpredictable timing, where as timing can be tightly controlled from the PL. Hopefully these ramblings will at least suggest where the conversation might go next. Dan
  32. 1 point
    yes, for an application with basic requirements, like receiver gain control this will probably work just fine (it's equivalent to an analog envelope detector). Now it needs a fairly high bandwidth margin between the modulation and the carrier, and that may make it problematic in more sophisticated DSP applications (say "polar" signal processing when I try to reconstruct the signal from the envelope) where the tolerable noise level is orders of magnitude lower.
  33. 1 point
    Oh, for what it's worth I've been toying with the Hilbert Transform. Here is a example of it; #include <math.h> #include <stdio.h> #define SAMPLES 1000 #define HALF_WIDTH 11 /* e.g. 11 filters from -11 to 11 */ float x[SAMPLES]; int main(int argc, char *argv[]) { int i; /* Build some test data */ for(i = 0; i < SAMPLES; i++) { x[i] = cos(2*M_PI*i/10.3); } /* Now apply the Hilbert Transform and see what we get */ /* It should be close to sin(2*M_PI*i/10.3) */ for(i = HALF_WIDTH; i < SAMPLES-HALF_WIDTH-1; i++) { double h = 0; int j; /* Apply the kernel */ for(j = 1; j <= HALF_WIDTH; j+=2) h += (x[i-j]-x[i+j]) * 2.0/(j*M_PI); /* Print result */ printf("%8.5f, %8.5f\n", x[i], h); } }
  34. 1 point
    Hi @Lesiastas You could change in the declaration of FDwfDigitalUartRx the argument to be <MarshalAs(UnmanagedType.LPStr)> ByVal szError As StringBuilder as it is for FDwfGetLastErrorMsg´╗┐.
  35. 1 point
  36. 1 point
    Hi @Lesiastas You're welcome and thank you.
  37. 1 point
    Oh having a look at the full signal chain, it looks like you just need to apply a low-pass filter on the absolute value of the signal. It might be just as simple as: if sample < 0 then filter := filter - filter/64 - sample; else filter := filter - filter/64 + sample; end if; With the value of "64" change depending on your sample rates and desired cutoff frequency. Or if your needs get very complex you might need to use a FIR low pass filter. Run some sample data through it in Matlab or Excel (or heavens forbid, some C code) and see what happens.
  38. 1 point
    Hi @Ahmed Alfadhel I had the C code handy because I have been working on an atan2(y,x) implementation for FPGAs, and had been testing ideas. I left it in C because I don't really know your requirements, but I wanted to give you a working algorithm, complete with proof that it does work, and so you can tinker with it, see how it works, and make use of it. Oh, and I must admit that it was also because I am also lazy ­čśÇ But seriously: - I don't know if you use VHDL or Verilog, or some HLS tool - I don't know if your inputs are 4 bits or 40 bits long, - I don''t know if you need the answer to be within 10% or 0.0001% - I don't know if it has to run at 40Mhz or 400Mhz - I don't know if you have 1000s of cycles to process each sample, or just one. - I don't even know if you need the algorithm at all! But it has been written to be trivially converted to any HDL as it only uses bit shifts and addition/subtraction. But maybe more importantly you can then use it during any subsequent debugging to verify that you correctly implemented it. For an example of how trivial it is to convert to HDL: if(x > 0) { x += -ty/8; y += tx/8;} else { x += ty/8; y += -tx/8;} could be implemented as IF x(x'high) = '0' THEN x := x - resize(y(y'high downto 3), y'length); y := y + resize(x(x'high downto 3), x'length); ELSE x := x + resize(y(y'high downto 3), y'length); y := y - resize(x(x'high downto 3), x'length); END IF My suggestion is that should you choose to use it, compile the C program, making the main() function a sort of test bench, and then work out exactly what you need to implement in your HDL., You will then spend very little time writing, debugging and improving the HDL because you will have a very clear idea of what you are implementing.
  39. 1 point

    GPS Pmod

    Hi @cepwin, Welcome to the Digilent Forums! To better assist you I would like a little more information about your project. From the linker script I can see that you are using Vivado 2019.1 and Microblaze and not ZYNQ. 1. What FPGA development board are you using? a. If a Digilent FPGA are you using the Digilent board files? 2. Please attach a screen shot of your block design. Here is a verified Pmod GPS Microblaze project using Vivado 2019.1 and the Arty-A7-35T(Artix-7). I have also attached screens shots of the Block design, SDK, the block automation for microblaze and the tera term serial output. best regards, Jon
  40. 1 point
    Hi @Lesiastas For reception you only need the lines with RX. See the other UART options, like FDwfDigitalUartRateSet, in the Python examples or the manual.
  41. 1 point
    Hi @pgmaser, I would look at the Spartan 3 Resource Center then which has the Xilinx made user guide (including details on the SRAM and flash). I don't believe you have control over the Done LED. Otherwise, I would recommend that you check that the FPGA configuration mode is set up correctly (as described in the Xilinx User Guide). Otherwise, there are also a number of projects for the Spartan 3 listed in it's Resource Center as well. What is the purpose of the second link you provided? It seems to have no relevance to FPGAs. Thanks, JColvin
  42. 1 point

    Getting Input Phase Programmatically

    Hi @jamesbraza I constantly see the prefix `rg` in your programs. What is the meaning of `rg` prefix in all array namings? This are so called Hungarian notations originating from physics, to help identifying variable kinds like: rg Array, sz String, i Index, c Count Why does the gain term = V_C1 / V_C#? I would think it's the inverse... gain = output / input = V_C2 / V_C1 This is how the function returns it. You can convert it using 1.0/gain Does the formula you listed, M = gain2 - 1.0, come from a simplification of M = (V_C1 - V_C2) / (V_C2 - 0)? Yes. Also, please see the attached image. It's of input phase. Note sometimes the points are flipped about 360┬░. My final question is, do you know why this might be happening? The phase should be normalized to +/-PI. The next software version will correct this, but you can correct it in you script/application like this: if phase2.value > math.pi : phase2.value -= 2.0*math.pi if phase2.value < -math.pi : phase2.value += 2.0*math.pi Thank you for the observation.
  43. 1 point
    Hi @Lesiastas You can convert between VB String and byte arrays like this: https://docs.microsoft.com/en-us/dotnet/visual-basic/programming-guide/language-features/strings/how-to-convert-strings-into-an-array-of-bytes https://docs.microsoft.com/en-us/dotnet/visual-basic/programming-guide/language-features/strings/how-to-convert-an-array-of-bytes-into-a-string You could also change the argument declaration in the wrapper to: <MarshalAs(UnmanagedType.LPStr)> ByVal szRx As StringBuilder
  44. 1 point
    Hi @pikeaero In the Logic Analyzer you could use in the Add/Custom interpreter, see the UART example. In case you want to send and receive UART data you could use the Protocol tool or access it from Script.
  45. 1 point
    Hi @pikeaero, Welcome to the Digilent forums! best regards, Jon
  46. 1 point
    I did a quick experiment with different liquids. All of them are in a small ceramic container. The blues (Ref1, Ref2 and Ref5) are tap water. The red (Ref3) is salted water. The green (Ref4) is carbon-filtered tap water. I just put both the + and - wires of the Impedance Analyzer into the container and I made sure they are not directly connected. Here are the results: Cool stuff!
  47. 1 point
    Hi @pgmaser, You can find the details for the what FPGA pin is associated for the Spartan 3E-1600 in it's user guide that Xilinx created (available on the right hand side of it's Resource Center under Documentation, conveniently linked here for you. LED0, as per page 18 under Discrete LEDs, is linked to D4. This is verified on page 4 of the schematic as well. I presume you were looking at the Spartan 3E starter kit user guide which is using a 500 variant of the Spartan 3 rather than a 1600 variant of the Spartan 3, hence the difference in FPGA pins. An example UCF file for the entire Spartan 3E 1600 is available at the end of the previously mentioned user guide starting on page 163. I am not certain what you mean by "writing to the LCD in 4-bit mode and then turning off the memory chip in the process". Are you referring to the memory chip present on the LCD screen? Based on the Memory Map section on page 44 of the user guide, I don't think you would be able to write to the display while having the memory turned off, though you can just keep the LCD screen turned off with the display off command, fill in whatever you like to the display memory, and then turn the display back on. As for a timing diagram, you would have to find the datasheet of the Sitronix ST7066U graphics controller or one of the functional equivalents that are also listed on page 44 of the user guide. The CPLD (as per page 127 of the user guide) coordinates behavior between the different FPGA configuration memories such as the two PROMs, so if you are using the flash memory, I imagine it is needed for production runs. I don't believe we have the JED code available for it, nor do I think it is readily possible to extra the configuration and display the HDL on ISE, though I am not very familiar with that end of things. Thank you, JColvin
  48. 1 point
    Hi @freakuency, On Arty Z7 reference page you can see a step model for the board on Additional Resources section: https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start If the step file doesn't help you, You have here some dimensions for the Arty Z7. Regards, Bianca Arty_Z7_Drawing.pdf
  49. 1 point

    VGA example for Digilent Nexys A7?

    Hi @kwilber, I really like this VGA demo originally made by a previous co-worked for the zybo. It does a few different tasks like a move box in the lower left of the screen. The horizontal/vertical black and white(largest change in color) lines also helped determine resolutions usable by the Pmod VGA without having issues. thank you, Jon
  50. 1 point

    JTAG-HS3 connection with API (DmgrOpen)

    @Assane, As I recall, there's an action required by the udev subsystem when you insert a USB Xilinx into your system. Without the udev action, it will show under lsusb (which I think is what you meant earlier, not libusb, right?), but nothing will recognize it. Getting the udev action to take place when you plug in your device requires installing the Xilinx device drivers as root. Basically, Xilinx and Digilent want to install two separate files into /etc/udev/rules.d/. Just to see if these files have been installed, can you "ls" this directory for me? You are looking for files "52-xilinx-digilent-usb.rules" and "52-xilinx-pcusb.rules". Thanks, Dan