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Showing content with the highest reputation since 08/20/20 in Posts

  1. 1 point
    Hi @painterguy1995, I believe (it's been awhile) that the needed drivers either come with the Arduino IDE or are part of the Digilent Core for the Arduino IDE (installation instructions available on our Wiki here: https://reference.digilentinc.com/learn/software/tutorials/digilent-core-install/start). *Edit: I checked and the necessary drivers are included with the Digilent Core. The instructions say to use Arduino 1.6.9, but I have used the same core up through 1.8.12 without any issues or needing to install drivers; Windows . My understanding is that MPIDE has been depreciated and is no longer used. Let me know if you have any questions. Thanks, JColvin
  2. 1 point
    @[email protected], I just got an email from a well known high end FPGA board vendor claiming 200 Gbps Digital IO. Yes this is far fetched but I had to know why a respected vendor would make such a claim. The answer turns out to be OCuLink. No, I was unaware that this is a thing but a google search returns plenty of hits. Some variants of the RfSoC have multiple lanes of transceivers that run at 25 Gbps. Connect 8 of these transceivers to an interface and you have 200 Gbps of something. Calling that something digital IO is beyond misleading. PCIe transceivers aren't like Select IO pins. My PCs have spare 4 lane Gen 3 (8 Gbps) slots. What do you think my chances of using one for GPIO are? BTW, finding OCuLink hits for things that you can connect to your 200 Gbps FPGA board interface is a different proposition. Beware of marketing claims. They can take a kernel of truth and turn it into a fantastical claim... unless you understand the context. The FPGA vendor claims that it can use this interface to connect two boards with a very high speed interface. Now that's believable but practical sustained data rates would likely be no where near 25 GB/s. [edit] It's curious that these beasts have such limited PL logic clocking support given the capability of the PS hard logic and the transceivers.
  3. 1 point
    Hi @Frank.Muenzner 2. I'm working on implementing such recording for the VIs Hope to give you a version with this in a few days.
  4. 1 point
    @xc6lx45, Spoiler Alert! This is one of those ZYNQ beasts with onboard ADC and DAC converters. The issue is essentially a lack of documentation and transparency on the part of Xilinx on how their devices work. My earlier posts to this thread shows that I didn't get it at first either.
  5. 1 point
    A sneaky way out of it is to use n (e.g. n=8 ) generators in parallel, with a phase offset of 1/n sample. This is literally a "polyphase" approach. For high-end fast DA / AD converters you won't be able to operate at the converter's clock rate on an FPGA so it needs to be split on multiple, parallel lanes anyway.
  6. 1 point
    zygot

    SERDES doesn't work as expected

    That's not how TMDS termination works. Read the material that I've suggested. Do not try and connect custom hardware or wires to your board unless you understand supported IOSTANDARD specifications and terminations for your device and bank Vccio. TMDS_33 termination resistors are external. The FPGA IO PULL_UP and PULL_DOWN are not suitable. Again, you need to do your homework before starting any experimentation. You are not likely to find what you are looking for using Xilinx IP. and the board design flow. You will have better fortunes if you learn Verilog or VHDL. The Digilent staff are keen on the board design approach perhaps you will be lucky and one of them will have some suggestions. But really, the appropriate thing to do here is write your own HDL to experiment with IOSERDES.
  7. 1 point
    If this is your first FPGA project you jumped into the deep end of the pool. The UltraScale devices are a lot more complicated than the normal devices used in products normally discussed in the Digilent Forum and the key information tends to be a lot more difficult to tease out. The first thing that you want to do is try to at least build the demo projects that come with your development kit. You might not be able to run them due to odd requirements. This is what I ran into with the ZCU106 TRD. But, with a bit modification of the tcl I did manage to build the demo.
  8. 1 point
    Hi, it sounds very unlikely. Now it does happen that boards fail (which is very rarely related to the FPGA itself, but more often unreliable USB cables, connectors, failing voltage regulators, PCB microcracks and, did I mention, unreliable USB cables) but usually, the problem is somewhere else. The FPGA GPIO circuitry is very robust. Unless there is an external power source involved outside the bank voltage range, I doubt you'd manage to damage it even if you tried. I guess we all know those panic moments, like "oh no I've bricked / toasted the board" and then you have a coffee, reboot the PC and everything is well again.
  9. 1 point
    Hi @S.Kamath, Yes, you can use our guide here, https://reference.digilentinc.com/learn/programmable-logic/tutorials/2020.1/getting-started-with-ipi, for using the Zynq processor to control an LED on a Zynq based board such as the Cora Z7-07S. Let me know if you have any questions. Thanks, JColvin
  10. 1 point
    Shun

    Using script with Wavegen Modulation on AD2

    Awesome, thanks Attila! It's exactly what I wanted to do!
  11. 1 point
    attila

    Using script with Wavegen Modulation on AD2

    Hi @Shun
  12. 1 point
    Kier

    SPI Decode In Logic Analyzer Is Incomplete

    Hi @attila Thank you very much for the quick, proactive support. The beta fixed the problem! Kier.
  13. 1 point
    Shalom

    BNC Adapter Schematic

    That makes a lot of sense about the scope lines... thanks for the explanation! It'd be great to put the Wavegen lines into the suggestion box for future revs of the BNC Adapter This is my first semester having my students use the AD2 (with adapter and probes) at the university and it would just be a nice option for them. Thanks again 👍
  14. 1 point
    attila

    BNC Adapter Schematic

    Hi @Shalom Routing the Scope lines on the BNC adapter also to the wire end would highly increase the capacitance, making it incompatible with 10x probe, and it would provide single ended channels. The Wavegen outputs have zero impedance, so these could be routed without major implications, but for similarity these are also only available on the BNC connectors.
  15. 1 point
    attila

    BNC Adapter Schematic

    Hi @Shalom On the BNC adapter the Scope and Wavegen outputs are only available on the BNC connectors. You can see the NC labels on the PCB and the traces. You can find the schematic at: https://reference.digilentinc.com/reference/instrumentation/bnc-adapter-board/start
  16. 1 point
    Hi @painterguy1995, As per the reference manual, https://reference.digilentinc.com/reference/microprocessor/uc32/reference-manual#power_supply, the 3.3V regulator is limited to 500 mA and the 5V regulator is limited to 1A. Each individual digital I/O pin is limited to 18 mA. I'm not certain which 3V pin you are referring to. The one the arrow points to is labeled as "3V3", which is 3.3V. I'm not certain what you mean by "Arduino" bootloader, but it does come loaded with a bootloader so that it can be configured through the Arduino IDE, yes. Let me know if you have any other questions. Thanks, JColvin
  17. 1 point
    Hi @Shalom, In case you want to match the output you'll use the 50Ohm jumper position in order to have adaptation. In this case your amplitude will be divided by 2. In the case you want to use the Gavegen just as a voltage source and don't want to reduce the amplitude, you can leave it to 0V. Regards, Bianca
  18. 1 point
    attila

    SDK and measurements

    Hi @Zebel http://www.radioradar.net/en/measurements_technics/oscilloscope_measurement_fundamentals.html
  19. 1 point
    tcmichals

    AXI Interrup Controller setup

    >Does the Interrupt interface on the microblaze and the AXI Interrupt Controller have to be connected in both NORMAL and FAST mode? The microblaze supports vectored interrupt table when FAST mode is enabled. This allows the ISR to jump to a function. For example, if your familiar with ARM Cortex-M, FAST mode in the microblaze is the same idea. In a general processor there is only one interrupt for general interrupts, i.e. serial, etc. So the software has to decode the interrupt and then jump to the handle, this is NORMAL mode. I would recommend adding a AXI UART (connect to concat to ISR) and AXI TIMER connect the interrupt concat) in vivado. Then use vitis to create a platform and example app. The platform will provide the drivers, etc. Typically the drivers have an init function, like the gpio, that will connect to the interrupt etc and you provide a callback. vitis has all the driver support for most AXI devices. I would recommend using FAST, which is the default for the fastest ISR speed. https://www.xilinx.com/html_docs/xilinx2020_1/vitis_doc/ugx1574145792115.html https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841745/Baremetal+Drivers+and+Libraries
  20. 1 point
    Hi @painterguy1995, That is correct; the ADC that is present on the PIC32MX chip is not equipped to handle voltages above 3.3V. The digital I/O have both clamp diodes and current limiting resistors which allows them to handle 5V inputs. Let me know if you have any questions about this. Thanks, JColvin
  21. 1 point
    JColvin

    unable to connect to hw_server

    Great! I'm very glad to hear that you were able to figure out what was causing the issue.
  22. 1 point
  23. 1 point
    JColvin

    Arty A7 basic IO problem

    Hello, This is also detailed a little bit more in our Getting Started with Vivado IP Integrator and Vitis guide in this section here. Thanks, JColvin
  24. 1 point
    Thank you! The trigger is the key point to detach the plug!
  25. 1 point
    JuanCar

    Triggering the mains failure

    dear @attila, I followed your recommendations and now is working perfectly. I can measure the mains with my home made 1000V isolated probe. You can see the result. Thanks a lot...
  26. 1 point
    zygot

    HDMI input for Nexys Video.

    True. It's also true that people who know the answers to anyone's questions don't have to help when given reasons not to. In this case @[email protected] did offer help. The anyone in this case just didn't realize it. BTW, Dan's an old fashioned man from at least the 1900's era , though it's possible that you chose a time period that he didn't find offensive. Your general response certainly was. I realize that in some cultures a well aimed insult is good fun... until someone decides to take it seriously. I'd suggest that you'd get more sympathy and better answers by not throwing insults in response to replies to your questions. [edit] As far as writing with all CAPS is concerned I don't have a side to defend. I don't engage in social media platforms so I don't infer yelling when faced with a particular writing style. I do realize that some people do infer yelling or being angry with capitalized sentences as the default situation. If an entire post is all caps then I really have no basis for making an inference about intent; it could just be the result of hitting the wrong key on a keyboard. If a few sentences of a post are in all caps this could just be an attempt at trying to highlight a thought as important ( well perhaps more important than other parts of the post ). I can certainly see a context in which there's less doubt about trying to convey anger or yelling. Usually, it's best to just ignore inference and try to deal with substance as inference is error prone. The world is just a better place to live in when we try to understand someone else's personal universe rather than insist that everyone accommodate ours
  27. 1 point
    Tim S.

    FPGA Colors Palette Tester

    Today I authored a brief post to introduce a simple FPGA design that I shared on GitHub. The design inputs a 24-bit color palette value from a keypad; and then that color value is mixed on a discrete RGB LED as well as text on a small display. https://timothystotts.github.io/2020/08/31/colors-palette-tester-on-arty-a7.html Regards, Tim S.
  28. 1 point
    tcmichals

    Arty A7 basic IO problem

    The GPIO API uses channels, #1 for push buttons and #2 for LEDS. For example: static XGpio gPIOBoardLEDAndPushbuttonss; ... int rc = XGpio_Initialize(&gPIOBoardLEDAndPushbuttonss,0); notice the API has 3 parameters, the GPIO handle, which channel 1 for Push buttons set data direction XGpio_SetDataDirection(&gPIOBoardLEDAndPushbuttonss, 1, 1); XGpio_SetDataDirection(&gPIOBoardLEDAndPushbuttonss, 2, 0); set output for LEDs XGpio_DiscreteWrite(&gPIOBoardLEDAndPushbuttonss, 2, 0x7);
  29. 1 point
    Hi, maybe I'm missing something here but even a plain 640x480x60 VGA signal has a pixel clock of 25.175 MHz, against the XADC maximum sample rate (2 channels!) of 1 MHz?
  30. 1 point
    Hi @amenah89, I presume you are using the Nexys A7 board, https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start? This board does not have a dedicated video input so it will be difficult at best to receive and process video on it. The VGA port has a resistor ladder for each of the colors so while you could technically provide a video feed from an external source, you would be limited to 3 bit color, which I doubt you want. There are a couple of potential alternatives with regards to providing a video feed to the Nexys A7. You could wire individual signals from a VGA source to the XADC connector (taking care to adjust the HSYNC and VSYNC voltage signals do not exceed the 1V limit on the XADC connector) and then use some fancy logic from the XADC to properly receive and interpret the signals. You could also have a pre-recorded video on an SD card that you then read off of, but at that point you may as well take the pre-recorded video and use dedicated software on an external PC to process and otherwise edit the video. Thanks, JColvin
  31. 1 point
    Hi, P=V^2/R that is V = sqrt(P*R). For 5 Watts and (assuming!) 50 ohms the voltage at your dummy load will be 16 V RMS or, multiply with sqrt(2), +/- 22.3 V peak. Consider using a 1 : 10 probe, check against the 22.3 V with some margin. This calculation assumes a largely sine-shaped waveform which seems a safe bet if you're FCC compliant with regard to harmonics. If you want to use a 50 ohms input you may consider a series resistor. For example, 1 kOhm into 50 ohms is (approximately) 1:20 voltage division. A 1/4 W rating would be at the limit (16^2 / 1000 is around 1/4). Probing your load with this will cause a minimal variation in load impedance (mismatch) - this is where a power splitter would come in for "serious" RF engineering - but most likely this can be swept under the rug. Or use 10k. it's funny how time flies - nowadays, buy a premium mobile phone and chances are good there's a modulated DC-DC converter inside with a bandwidth of many times said "RF" frequency...
  32. 1 point
    ssm

    Using the SDK with AD2 on Ubuntu

    thank you attila
  33. 1 point
    ssm

    generating and reading a custom signal

    the mistake was here: FDwfAnalogInTriggerSourceSet(hdwf, trigsrcDetectorAnalogIn); not sure why I used trigsrcDetectorAnalogIn instead of trigsrcAnalogOut1 FDwfAnalogInTriggerSourceSet(hdwf, trigsrcAnalogOut1) working perfectly now. thanks a million for the great help ssm
  34. 1 point
    Hi @mjk.kirschner Thank you for the observation. It will be fixed for the next software release. - To overcome this you can add two SPI interpreters, one for MOSI and one for MISO. - You could also change the Format for MISO from Script, by running: Logic.Channels.SPIMISO.Format.text = "Decimal" As mentioned in the installer the driver is only required for older macOS versions. Such warning/info is given by the WF application when no device is detected:
  35. 1 point
    The reference to Barbara Dennerlein is beyond my cloistered lifestyle ; but I get your point. Sometimes a question suggests that a different problem than the one being asked is at the crux of the difficulty. It's a sense, analogous to the web crawler's spidey sense, that gets tingled every so often. It's a result of many years of experience. Sometimes the source of the question simply hasn't thought trough the problem. Sometimes it represents a naive understanding of the problem. You can't really solve a problem unless you understand it. Occasionally, you can have a naive understanding of the problem and still come up with an acceptable solution, but usually doing the work to more fully understand the problem eliminates those solutions from consideration. I'm not suggesting that there's nothing to discuss here; just that a bit of digging is in order to better describe exactly what needs to be done and discuss possible solutions. It's unfortunate but more knowledge often impedes progress. Less knowledge produces quick results but not generally correct ones.
  36. 1 point
    OT: I think Barbara Dennerlein once discovered such a place playing Hammond organ on a generator-powered festival... almost in tune...
  37. 1 point
    Brent

    Programming FPGA Boards from a Mac

    Follow Up and Summary - Programming FPGA Boards from a Mac Thanks to those who responded to my request for methods for programming FPGA boards on a Mac. Since then I have found a mechanism that is working very well. It is called Open OCD (search the web). This is an open source solution that we have tested on a number of Digilent boards (Nexys4, Basys3, Arty). It works for both a Mac as well as Linux (useful since we could never get Adept 2 installed in a way to work on Ubuntu 16.04). I have created a web page that describes how to use it at: https://github.com/byu-cpe/BYU-Computing-Tutorials/wiki/Program-7-Series-FPGA-from-a-Mac-or-Linux-Without-Xilinx Feedback appreciated.
  38. 1 point
    ssm

    generating and reading a custom signal

    thank you attila for the great help, ssm
  39. 1 point
    Hi @attila, that did the trick. Got great data, I'm a fan!
  40. 1 point
    Hi @satvik, I apologize for the delay. It looks like the output on the Console is getting limited to only printing out 8 characters between the 0:25000/ and the .BIN. I'm not certain where this limitation coming from though. Thanks, JColvin
  41. 1 point
    This worked! Thanks @attila
  42. 1 point
    Hi @Phil_D # 2nd configuration for Analog Discovery with 16k analog-in buffer if(!FDwfDeviceConfigOpen(-1, 1, &hdwf)){...
  43. 1 point
    Hi @satvik, My guess is that you haven't set up your serial terminal correctly. I recommend you use teraterm and I'll show you how to set it up correctly using screenshots. First, make sure you select Serial and from the drop down list select the COM Port associated to your Zedboard. Next, go to Setup and choose Serial port... Set Speed to 115200 and then press New setting. Then go to Setup again and select General... In the General setup make sure to change the Language to English. Now go to Setup->Terminal... and for the New-line setting make sure you have selected CR+LF for both Receive and Transmit and then press OK. You should now go to Setup->Font->Font... and select Courier as the primary font (apparently you have to do this so you don't get japanese kanji characters when you type "\" aka backslash or other such keys). Upon startup, the ESP32 is configured to echo serial commands sent to it. The AT command "ATE0" can be used to prevent the demo from printing each character received from the host PC's serial terminal twice. So just type ATE0 and then press Enter but don't worry if it comes out as AATTEE00. Now you should be able to get it working yourself but if you have any other questions we'll be happy to help.
  44. 1 point
    JColvin

    When/Where can I buy an AD2?

    Hi @[email protected], We are working on filling back orders for the Analog Discovery 2, though new orders will have some amount of lead time associated with them. The latest information on this can be found on Digilent's website here: https://store.digilentinc.com/analog-discovery-shortage/. Thank you, JColvin
  45. 1 point
    Hi! Since I've been doing a lot of stuff with SDR for the past 2 years, I was wondering, if it is possible to use the AD2 with any SDR software. The Waveforms SDK only allows to record float values to a file, if I understood correctly, so I would have to save them and convert them before usage. It would be nice though, to make a FIFO pipe to some other software like gnuradio, gqrx or SDR#. Thanks to the 14 bit ADC/DAC it would be a very useful SDR device. Does anybody of you have an idea, of how to implement this? Since we can use the AD2 to play audio, the easiest way would be to create a virtual sound card, piping the whole spectrum (Waveforms does it in spectrum view, but without demodulation possibilities), because those can be used in any SDR software. Thanks in advance!
  46. 1 point
    Hi @Pazzo In case the data processing or saving in your loop function takes too much time it could lead to buffer overflow (samples lost/corrupt). You could try opening the device with 2nd configuration to have more device buffer. # 2nd configuration for Analog Disocovery with 16k analog-in buffer #dwf.FDwfDeviceConfigOpen(c_int(-1), c_int(1), byref(hdwf))
  47. 1 point
    @Clarissa, Yes, it means you can adjust the frequency standard of those pins used on the FMC connector, as well as the power used by the switches, the buttons, and the XADC PMod (not all of the PMods) FPGA's handle their I/O voltages by bank. Hence, when you adjust the I/O voltage of a bank, you adjust the I/O voltages of all of the signals on that bank. This is the reason why you can't just specify a voltage for an I/O pin and expect it to suddenly have that voltage (a common misperception). The voltage needs to first be set in the voltage rail for the whole I/O bank. Hence, for most Digilent boards, this I/O voltage is fixed. This is also true for most of the Nexys Video board, although only one bank's voltage may be adjusted. If you look across the top of page 10 of the Nexys Video schematic, the Digilent Nexys Video engineer has been kind enough to write above the various I/O banks the voltage standard being used for each bank. The third I/O bank on that page, labeled as "Bank 15", is the adjustable voltage bank. If you look further, on page 15, you can see how the SET_VADJx and VADJ_EN lines are connected. If you'd like, you can even look up the various specifications for the chips that are then used to control that output voltage. As for the difference between LVCMOS and LVTTL, I would caution you against ascribing the only difference as being to the I/O voltages. According to Xilinx's SelectIO Resources user guide, starting at page 51, LVTTL is available at 3.3V, whereas LVCMOS is available in 1.2, 1.5, 1.8, 2.5, and 3.3 Volts (p54). In other words, the difference goes beyond voltage since both LVTTL and LVCMOS can handle 3.3V. Dan
  48. 1 point
    hamster

    HDMI input for Nexys Video.

    And with a night of hacking, I've got a Sobel-like edge detector working too.
  49. 1 point
    hamster

    HDMI input for Nexys Video.

    Oh, just added a video of it in action...
  50. 1 point
    Tim Ansell

    HDMI input for Nexys Video.

    This is so awesome! Thank you for creating this. I'll try and verify this on my own Nexys Video when it arrives. Tim 'mithro' Ansell