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Showing content with the highest reputation since 03/24/19 in all areas

  1. 2 points
    JColvin

    Read from MicroSD in HDL, Write on PC

    Hi @dcc, I'm not certain how you are verifying that the HDL is writing to and then reading back from the SD card in a normal formatting style, but in general FAT32 is a widely used format for SD cards that has existing material for it. I am uncertain why you are using a special tool to write to the SD card though; from what I can tell the tool is Windows compatible, so why not just use the Notepad program which comes with Windows and save a .txt file with the data you are interested in reading to the SD card or just using Windows Explorer (the file manager) to move the file of interest onto the SD card? If you do have a header in your file, you will need to take account for that, though I do not know what you mean by "random file" in this case. Thanks, JColvin
  2. 2 points
    SeanS

    Genesys 2 DDR Constraints

    Hi JColvin, I am definitely not using ISE. I think JPeyron had it correctly. I didn't have my board.Repopaths variable set and so the project wasn't finding the board files. Once I set this variable as suggested, the pin mapping and IO types were auto populated as expected. Kudos, Sean
  3. 2 points
    @jpeyron @D@n I fixed the bug in my SPI Flash controller design. Now I can read from Flash memory.
  4. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  5. 1 point
    Hi @Ciprian, After some time, I managed to solve this issue. In fact, It was a problem in the hardware and device tree configuration. I discovered it when probing with another example project named Zybo-hdmi-out (https://github.com/Digilent/Zybo-hdmi-out). However, as this project is for a previous version of Vivado, I tested with Vivado 2017.4. Surprisingly, it worked fine but with another pixel-format in the device tree. The Zybo-base-linux project which I used, has a pixel format in DRM device tree configuration set to "rgb888", however, for the Zybo-hdmi-out, it displayed correctly with pixel-format "xrgb8888". If I use other pixel formats, no output is displayed in both cases. Going deep into the configuration of both projects, I discovered that there are some differences in the VDMA and Subset converter settings, which changed to the configuration in Zybo-hdmi-out, solves the problem of colors and rendering, considering also a pixel format in the devicetree equal to "xrgb8888". I attached the images of both configurations. In addition to this, I managed to update the design for the Vivado version I use (2018.2) with no more differences that a change in the AXI memory interconnect replaced by the AXI Smart connect in the newer version, which is added automatically when using Vivado autoconnect tool for the VDMA block. Hope this information could help others which run in the same issue. Thanks for your help. Luighi Vitón
  6. 1 point
    if you can bring it up once in Vivado HW manager (maybe with the help of an external +5 V supply), you might be able to erase the flash. If not, you may be able to prevent loading the bitstream from flash e.g. by pulling INIT_B low (R32 is on the bottom of the board, its label slightly below the CE mark). See https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf "INIT_B can externally be held Low during power-up to stall the power-on configuration sequence at the end of the initialization process. When a High is detected at the INIT_B input after the initialization process, the FPGA proceeds with the remainder of the configuration sequence dictated by the M[2:0] pin settings.""
  7. 1 point
    @askhunter Tip if you want to notify someone that you are responding to a post type @and the first few letters of their username. A selection of usernames will appear in a popup window to choose from. If you just type @ and the whole name you won't get the desired result. I confess that I'm not an expert on using the features of this site but I did figure out this one. As to understanding all of the Xilinx documentation what yo are doing is correct. Speed-read though a document to get a general sense of what's being presented and don't worry about the things that you don't grasp. Just being familiar with what information is where will help with a specific question later. The DSP48E is a very complicated piece of hardware. You only understand how complicated by trying to instantiate it as a UNISIM component to implement a particular algorithm. I've done this and it take time. You understand by doing; one step at a time. In your case I'm assuming that you are starting with someone else's code and trying to modify it. This approach takes a difficult task and turns it into an extremely difficult task. [edit] Vivado uses the multipliers in a seamless way when you specify a multiply in your HDL code. It takes care of a lot of little details, such as that the multipliers are signed 18-bit. There are a LOT of options with the DSP48E blocks. Once you start making decisions for Vivado, by say, using the use_dsp attribute in your code you are taking on responsibility for more of those details... so you had better understand how the DSP48E blocks work. Trust me, even after you have figured out all of the necessary behaviors of the DSP48E blocks it doesn't get easier as you will have to contend with routing issues that might dramatically reduce your data rates. This is a general rule for using FPGA device resources. You can use the IP wizards to help construct a component that's useful for your needs or do it yourself in HDL code and assume the responsibility for getting all of the details and constraints right.
  8. 1 point
    @askhunter I suggest that you read UG479 to see what the DSP48E blocks do. Then read UG901 to see what the use_dsp attributes do. Reading the recipe doesn't always help improve the cooking but it never hurts. A long time ago having signed multipliers in hardware was a big deal for FPGA developers. For the past decade or so these have become integrated into more complicated and useful 'DSP' blocks. The DSP nomenclature is a holdover from the days, long before IEEE floating point hardware was available, when having a fast multiplier in hardware meant that you could do some fun stuff in a micro-controller that you couldn't do with software routines. These days the lines are blurry. Most FPGA devices have some really fast hardware features, block ram and DSP blocks ( depending on how they are used ) being the most useful for grinding out mathematical algorithms. By the way, the DSP blocks can be useful for more than multiply-add operations.
  9. 1 point
    D@n

    Read from MicroSD in HDL, Write on PC

    @dcc, This is really the backwards way to get something like this going. You should be proving your design in simulation before jumping into a design on hardware. Let me offer you an alternative. Here is a Verilog driver for talking to an SD card using SPI. If you have already chosen to use the AXI bus, you can find an AXI-lite to WB bridge here that will allow you to talk to this core. Even if you already have a driver you like, this documentation for this one describes how to set up the SD card to where you can talk to it, and provides examples of how to read and write sectors. Even better, there's a piece of C++ code which can be used as a simulator with Verilator. (Not sure if this would work with MicroBlaze or not.) You can then use Linux tools, such as mkfatfs and such, to create a file with a FAT format that you can use as a "simulated" SD card. When the simulation isn't running, you can mount the card on your system and check out/modify the files, and so know that things will work (based upon your experience with simulation) once you finally switch to hardware. Indeed, if you are willing to accept the risks, you could even interact with your SD card from the simulation environment itself. If you want an example of a set up that would control the SD card interface from a ZipCPU, you can check out the ZBasic repository which has such a simulation integrated into it. Indeed, there's even an sdtest.c program that can be used for that purpose. As for reading and comprehending the FAT filesystem, there's a FATFS repository that is supposedly good for use with embedded software. I haven't tried it, so I can't comment upon it that much. Alternatively, if you can control how the file system is laid out, you should be able to place a file of (nearly) arbitrary length a couple of sectors into the FS, and force the file to be use contiguous sectors. If you do that, then you've dealt with the most complicated parts about reading from the SD card. Just my two cents, and some thoughts and ideas along the way. Dan
  10. 1 point
    JColvin

    OpenLogger ADC resolution + exporting

    Hi @sgrobler, Our design engineer who designed the OpenLogger did an end-to-end analysis to determine the end number of bits of the OpenLogger. This is what they ended up doing in a summarized fashion: <start> They sampled 3 AAA battery inputs to the SD card at 250 kS/s and set the OpenLogger sample rate to 125 kS/s and then took 4096 samples; they then took the raw data stored on the SD card and converted it to a CSV file and exported the data for processing. Their Agilent scope read the battery pack at 4.61538 V and as they later found from FFT results the OpenLogger read 4.616605445 V, leading to a 0.001226445 V or ~1.2mV difference, which is presuming the Agilent is perfect (which it is not), but it was nice to see that the values worked out so closely. They calculated the RMS value of the full 4096 samples in both the time domain and using Parseval's theorem in the frequency domain as well, both of which came up with the same RMS value of 4616.606689 mV, which is very close to the DC battery voltage of 4616 mV. Because RMS is the same as DC voltage, this gives the previously mentioned DC value of 4.616605445 V. They can then remove the DC component from the total RMS value to find the remaining energy (the total noise, including analog, sampling, and quantization noise) of the OpenLogger from end-to-end. With the input range of +/- 10V input, this produces an RMS noise of 1.5mV. At the ADC input, there is a 3V reference and the analog input front end attenuates the input by a factor of 0.1392, so the 1.5mV noise on the OpenLogger is 0.2088mV at the ADC. With the 16 bits (65536 LSBs) over 3V, 0.0002088V translates to ~4.56 LSBs of noise. The ENOB is a power of 2, so log(4.56)/log(2) results in 2.189 bits, giving us a final ENOB of 16 - 2.189 = ~13.8 bits. Note though that this ENOB of 13.8 bits is based on system noise and not dynamic range, so for non-DC inputs (which will likely be measured at some point) the end number of bits is not easily determined. The datasheet for the ADC used in the OpenLogger (link) shows that the ADC itself gives an ENOB of about 14.5 bits at DC voltage (so the 13.8 bits is within that range), but at high frequencies, this of course rolls off to lower ENOB at higher frequency inputs. Thus, they cannot fully predict what the compound ENOB would be over the dynamic range, but they suspect it all mixes together and is 1 or 1.5 bits lower than the ADC ENOB response. </end> Let me know if you have questions or would like to see the non-abbreviated version of his analysis. Thanks, JColvin
  11. 1 point
    jpeyron

    Pmod IA AD5933 measurement speed

    Hi @M.Mahdi.T, Welcome to the Digilent Forums! We typically do not test the max throughput metric when validating our products. Looking at the AD5933 datasheet here the Pmod IA would be limited to 1 MSPS due to the on board ADC. The main bottleneck for throughput to a host board will be the I2C communication which runs at 400 KHz. Here is a good forum thread for using the Pmod IA with the Raspberry PI with code and hints for use , setup and calibration. Here is the resource center for the Pmod IA which has the Raspberry PI code as well. best regards, Jon
  12. 1 point
    bogdan.deac

    OpenCV and Pcam5-c

    Hi @Esti.A, If you clone the repo you obtain the "source code" for the platform and you have to generate the platform by yourself. This is a time consuming and complicated task and is not recommended if you do not understand SDSoC very well. I advise you to download the last SDSoC platform release from here. You will obtain a zip file that contains the SDSoC platform already build. After that, you can follow these steps to create your first project.
  13. 1 point
    kwilber

    New Xilinx Zynq MPSoC ebook available

    For those interested, Xilinx has just made a new Zynq MPSoC ebook available here.
  14. 1 point
    FPGAMaster

    CMOD A7 Schematic missing stuff

    Thank you Jon... I got the PM and will follow up as you suggested.
  15. 1 point
    Hi, I think a UART is the least effort. Parsing ASCII hex data in a state machine is easy and intuitive to debug, at the price of 50 % throughput. If you like, you can have a look at my busbridge3 project here, goes up to 30 MBit/second. The example RTL includes very simple bus logic with a few registers, so it's fairly easy to connect an own design. Note, it's not meant for AXI, microblaze or the like as it occupies the USB end of the JTAG port. In theory, it should work on any Artix & FTDI board as it doesn't any LOC-constrained pins.
  16. 1 point
    LOL yeppers! https://store.digilentinc.com/labview-physical-computing-kit-for-beaglebone-black-limited-time/ I've been struggling to dredge up my Unix experience from 30 years ago and apply it to this board as well as a RPi 3B+ in an effort to get them to run LabView. In the process, I had flashed the BBB's eMMC with the most current software only to find it broke LINX. I then back-rev'd the software to 8.6 2016-11-06 which seems to work so far. But, I'd like to know what it originally shipped with in order to fill out the revision continuum. -Scott
  17. 1 point
    xc6lx45

    Vivado free for Artix-7?

    Just as a reality check: To e.g. make a LED blink, the required CMOD A7-specific content is about five lines of constraints from CMODA7_Master.xdc. This may look more complicated than it actually is. And BTW, good choice, it's a great little board 🙂
  18. 1 point
    jpeyron

    Vivado free for Artix-7?

    Hi @TerryS, Thank you for posting how you got to the legacy content. I will pass this on to our content team. We will still have this content accessible since there are a wide array of people that use different versions of vivado. The legacy content is accurate for earlier versions of Vivado/SDK. best regards, Jon
  19. 1 point
    Hi @Phil_D Sure, it makes more sense to apply the window only on the real data section. const NAVG = 10 const NPAD = 2 Spectrum.Trace5.Window.text = "Rectangular" // disable windowing Spectrum.run() var win = [] var sum = [] for(var acq = 1; acq <= NAVG && Spectrum.wait(); acq++){ var hz = Spectrum.Channel1.dataRate // WF v3.11.2 { // padding in Trace 5 var rg = Spectrum.Channel1.data // channel 1 time domain data var c = rg.length if(acq==1){ // create window var w = 0 for(var i = 0; i < c; i++) { var v = pow(sin(PI*i/(c-1)), 2.0) // Hann w += v win.push(v) } w /= c*NPAD for(var i = 0; i < c; i++) { // normalize win[i] /= w } } for(var i = 0; i < c; i++) rg[i] = win[i]*rg[i] // apply window for(var i = 0; i < c*(NPAD-1); i++) rg.push(0) // padding Spectrum.Trace5.setSamples(rg, hz) } { // averaging in Trace 6 var rg = Spectrum.Trace5.magnitude if(acq==1){ sum = rg; Spectrum.Trace6.Clone(Spectrum.Trace5) }else{ rg.forEach(function(v,i){ sum[i] += v;}) // sum sum.forEach(function(v,i){ rg[i] = v/acq;}) // average Spectrum.Trace6.setMagnitude(rg, 0, hz/2) } } } Spectrum.stop() Here you can see that CZT produces the same result as the padding: The noise floor difference is due to different captures. The FFT works on power of two + 1 BINs, with CZT you can specify arbitrary number of BINs, setting fine resolution:
  20. 1 point
    jpeyron

    OpenCV and Pcam5-c

    Hi @Esti.A, I would suggest using the version of Vivado/SDK/Petalinux that the project was made in and for. If you are typing to update an existing project to an newer version there are alot of potential issues that could occur. We do not have a tutorial on how to do this. I would suggest looking through the xilinx petalinux documentation like the petalinux wiki. Here is a forum thread that might be helpful as well. best regards, Jon
  21. 1 point
    jpeyron

    Cora Z7 Basic IO example problem

    Hi @Lost_In_Space, Welcome to the Digilent Forums! Please download Adept 2. 1) Can Adept 2 recognize the Cora Z7? Please attach screen shots of the Adept 2 text when the Cora Z7 is connected. 2) Are you using Linux? Windows? 3) Is the Mode Jumper JP2 set to JTAG? 4) How are you powering the Cora Z7? USB or external power source? best regards, Jon
  22. 1 point
    jpeyron

    VGA on Zybo

    Hi @Mukul, Glad to hear that your project is working. Thank you for sharing what you did. best regards, Jon
  23. 1 point
    Hi jon! I have resolved that issue using a case statement to assign the bits instead of using the - operator.Hence I have deleted the post also immediately.where you still able to see it?
  24. 1 point
    Hi @Phil_D I just notice that the -runscript is only working when the instruments are in docking window mode. My bad, runscript is only looking for docked Script window. It will be fixed in the next software version.
  25. 1 point
    Hi @Phil_D There is no zero padding option but it can be done with Script like this: var rg = Spectrum.Channel1.data // channel 1 time domain data var c = rg.length var t = rg[c-1] // last sample for(var i = 0; i < c; i++) rg.push(t) // 2x padding var rghz = Spectrum.Trace1.frequency var hz = 2.0*rghz[rghz.length-1] //var hz = 2.0*Spectrum.Frequency.Stop.value // scope sample rate Spectrum.Trace5.setSamples(rg, hz) Some other suggestions to improve the resolution: 1. For lower frequencies, with 1MHz sampling you can use the Scope to perform a longer recording. This will highly improve the resolution in the FFT view. 2. With AD you can select the second device configuration to have 16k Scope buffer. 3. You can select a higher bandwidth window, like rectangular or cosine. 4. In the latest beta version with CZT algorithm you can select higher number of bins, higher resolution. https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ Here: - T1 is CZT BlackmanHarris 10x BINs, 244Hz resolution - T2 is FFT BlackmanHarris 4k BINs 2.4kHz resolution - T3 is FFT Cosine 4k BINs 2.4kHz resolution
  26. 1 point
    jpeyron

    VGA on Zybo

    Hi @Mukul, Here is a VHDL VGA project that has pixel clock frequencies for multiple resolutions. Here and here are non-digilent VGA tutorials. Here is a listing for different pixel frequencies and resolutions. best regards, Jon
  27. 1 point
    jpeyron

    Hello world program for zynq linux

    Hi @Ram, I moved your thread to a section where more experience embedded linux engineers look. best regards, Jon
  28. 1 point
    jpeyron

    ZYBO HDMI IN project

    Hi @birca123, I got the same errors when I loaded the applications. Looking at the last line says that the "BSP Project P/HDMI_IN_bsp has been successfully migrated" is a good thing. I was able to program the FPGA, run the application and the project to worked. I have updated the above linked HDMI project with my sdk portion done as well. I have also attached my SDK log so you can compare it to what you have. best regards, Jon SDK_LOG_HDMI_IN.txt
  29. 1 point
    Hello Jon! Thank you for giving hope in coding with what ever I am comfortable with.
  30. 1 point
    jpeyron

    ZYBO HDMI IN project

    Hi @birca123, I would suggest to start with a fresh sdk portion of the project. To do this close SDK and delete the hdmi-in.sdk folder in the \Zybo-hdmi-in\proj folder. Then in vivado click file->export -> export hardware including the bitstream. Then launch SDK from Vivado by clicking in file and selecting launch SDK. Once in SDK and the HW platform is loaded click in file and import HDMI_IN and HDMI_IN_bsp from Zybo-hdmi-in\sdk. Once you have the HDMI_IN and HDMI_IN_bsp into your SDK project then program the FPGA Next open a serial terminal emulator like tera term and connect to the Zybo's com port. Set the baud rate to 115200 everything else should be left at default settings. Now connect the Zybo to the HDMI and VGA device. then in SDK right click on HDMI_IN and select run as->launch on hardware(system debugger). Do you see the serial terminal menu? Is there an image on the VGA device?
  31. 1 point
    Thanks again @Ionel, That solved it. I was now able to build the petalinux project.
  32. 1 point
    thanks for the response. Greatly appreciated. I figured out what I had done wrong....I didn't select the Board properly. I had filtered/searched for the Basys3 board and when that was the only one on the screen I "thought" that was all I needed to do to select it. I pressed next......and that caused my problem. I finally realized I had to click in one of the fields for the selected/filtered board, which turns the whole line blue...and THAT selected the proper board. I figured it out by looking at the Project Part # (within the project) and realized it was NOT the Basys3 board. Stupid mistake. Thanks again for responding...and so quickly!
  33. 1 point
    JColvin

    Read out .log file from OpenLogger

    Hi @Peggy, I spoke with some of the firmware folks for WFL and OpenLogger and learned that they haven't yet implemented the parsing of the header into the Digilent agent yet. I did receive a picture that showed the structure of the header file, which I have attached below. Thanks, JColvin
  34. 1 point
    I see, thanks jpeyron
  35. 1 point
    JColvin

    Pmod ISNS20 SPI Arduino

    Hi @tfcb, I am taking a look into this; I connected a level shifter of my own (Digilent's Pmod LVLSHFT rather than the Sparkfun one you linked to) to connect an Arduino Uno and Pmod ISNS20, but I too am getting strange values (no initial offset for example), so I'm debugging some more. Thanks, JColvin
  36. 1 point
    jpeyron

    OpenCV and Pcam5-c

    Hi @Esti.A, We have a reVISION project here for the Zybo-Z7-20 that uses SDSoC and the OpenCV that should be useful for your project. best regards, Jon
  37. 1 point
    Hi, >> We are forced to work in assembly with picoblaze. you might have a look at the ZPU softcore CPU with GCC. The CPU is just a few hundred lines of code but most of its functionality is in software in the crt.o library in RAM. I understand it's quite well tested and has been used in commercial products. Not surprisingly, using an FPGA to implement a processor that then kinda emulates itself in software (aka RISC :) ) is maybe not the most efficient use of silicon - I'm sure it has many strong points but speed is not among them... Unfortunately, the broken-ness of Xilinx' DATA2MEM utility (to update the bitstream with a new .elf file) spoils the fun, at least when I tried in ISE14.7 (segfaults). When it works, the compile/build cycle takes only a second or two. Long-term, porting the processor to a new platform would be straightforward, or even fully transparent if using inferred, device-independent memory. This would also work for a bootloader that is hardcoded into default content in inferred RAM. I might consider this myself as a barebone "hackable" CPU platform strictly for educational purposes.
  38. 1 point
    Heya Jon, Now it seems resolved. And I can move to other questions to Digilent (you can see that Xilinx thread you 've referred too) Thanks for your help on this.
  39. 1 point
    bogdan.deac

    Inter core communication

    As far as I know the NN training phase takes long time and needs many resources. For this reason it is not recommended to train NN on FPGAs. On the other hand, FPGA is strong in inference. I advise you to use GPU and a learning framework, like Caffe, for the training phase. Fortunately, Xilinx released recently a new development kit for NN named Deep Neural Network Development Kit (DNNDK). Here you have the user guide and the DNNDK extension for SDSoC. Have a look on the Xilinx documentation and forum posts to get familiar with all concepts. Let us know if you have any questions.
  40. 1 point
    jpeyron

    IP used in Zybo-Z7 MIPI Pcam 5C demo

    Hi @Esti.A, Can you be more specific? The Vivado library branch here has the updated MIPI_D_PHY_RX and MIPI_CSI_2_RX. These IP Cores were updated by the creator of these IP cores and should work are described in this forum thread here. Here is a forum thread that discusses some of the difference between Digilent's MIPI_D_PHY_RX and MIPI_CSI_2_RX IP Cores and those that are available for purchase. best regards, Jon
  41. 1 point
    Hi @Luighi Vitón, I'm not sure it's a HDMI issue, have you tried to use X11 over SSH do you get the same result? -Ciprian
  42. 1 point
    gummadi Teja

    FFT / iFFT / RS - Basys3

    thank u sir i complete my code for fft using cordic algorithm..
  43. 1 point
    Hi @askhunter, The top.vhd is already added to the project. If you are wanting this file to be underneath the design_1 then you should right click on the design_1 and select add sources. Then add the vhdl files you would like to add to the design. It might be easier to start with a fresh project. best regards, Jon
  44. 1 point
    jpeyron

    Arty A7 vs Nexys A7

    Hi @Phil, The Arty-A7-100T comes with with a built in USB JTAG/UART (J10) programming circuit.You will not need an additional JTAG programmer like the JTAG-HS2 to configure the Arty-A7-100T. Here is the Arty A7 resource center. Under Additional Resources there is a tutorial called getting started with microblaze servers that goes through making an ethernet echo server with the Ethernet lite IP Core (no cost). best regards, Jon
  45. 1 point
    CVu

    Nexys 2 - transistor part number

    Transistor has been replaced, board is back up and running. Thanks!
  46. 1 point
    CVu

    Nexys 2 - transistor part number

    Thank you very much Jon. Much appreciated.
  47. 1 point
    jpeyron

    Nexys 2 - transistor part number

    Hi @CVu, Welcome to the Digilent Forums! Q1 information is below: NTS2101P Single P-Channel Power Mosfet 1.4A, 8VSOT-323 (SC-70) best regards, Jon
  48. 1 point
    zygot

    NexysDDR4 example projects

    OS file permissions are a two-edged sword. It can prevent users from changing stuff that shouldn't be changed but it can prevent users from doing their work unintendedly This is a user issue. You will have to learn how to change file permissions as a computer user to the extent that your privileges allow. Depending on the OS and how security is set up this can be a pain, especially when transferring files form one OS or computer to another one. If you have an IT department they should be able to help resolve issues. If you are the IT department then you need to learn how to set up and use your OS safely and securely.
  49. 1 point
    Hi @Nithin Yes. See the AnalogIO_DigitalDiscovery.py how to adjust the IO voltage, enable VIO output, set pull-up/downs, slew rate, drives The DigitalIO functions can be used the same way controlling DIO[24:31] The DigitalOut functions are the same but you have 32k custom bit/line for DIO[24:31] The DigitalIn by default samples DIN[0:23]&DIO[24:31]. To sample DIO lines first DIO[24:39]&DIN[0:15] set FDwfDigitalInInputOrderSet(hdwf, true). This way if you sample 16 bits you will get DIO[24:39]. The base frequency is 800MHz (FDwfDigitalInInternalClockInfo), like use FDwfDigitalInDividerSet(hdwf, 8 ) for 100MHz
  50. 1 point
    jpeyron

    0V5640 5MP Camera FPGA Board

    Hi @DFL, We have the Pcam 5C here that uses the Omnivision OV5640 5 megapixel (MP) color image sensor. The Zybo Z7 (either the Z7-10 or Z7-20) works with the Pcam 5C through the MIPI CSI-2 interface. There is a demo using the Pcam 5C and the Zybo-Z7 here. We have the Pcam 5C IP Core here. thank you, Jon