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  1. 3 likes
    A few reasons are... a - The introduction of logic hazards can cause glitches : https://en.wikipedia.org/wiki/Hazard_(logic) b - Routing of clocks is very complex - It is hard to ensure that the same clock edge appears all over the FPGA at almost exactly the same time. Sometimes this is achieved with 'slight of hand' (e.g. using a on-chip PLL to advance phase of the clock, so that by the time it reaches the edge of the chip is in back phase with the original signal). Low-skew paths also exist, but are restricted to small areas of the FPGA, and the clock has to be connected to the correct pin to be placed and routed correctly. c - FPGAs and their tools are designed to behave predictably under the "synchronous digital design" paradigm (something like https://hps.hs-regensburg.de/scm39115/homepage/education/courses/red/2_SynchronousDigitalCircuitDesignRules.pdf). If you work outside the paradigm you will be fighting against the tools and their assumptions. d - There is almost nothing that you are unable to code in an FPGA friendly way, but there are infinitely many ways to write FPGA-hostile code. If you want your FPGA to place nice with you, you have to play nice with it. So you can either add an RC filter to debounce you switch, or you can sample it using a reliable clock.
  2. 2 likes
    Here's a utility for debugging and testing your code in hardware and uses any IO pin to send an ASCII representation of any signal through a hardware UART interface. If you don't have a UART on you FPGA board there are TTL USB UART breakout boards and cables that allow any spare IO pin to become a UART interface. This code is functionally the same as one recently released by Hamster but developed independently for the Fast Data Interface project. I recommend comparing the different coding styles. I decided to release this as a separate project as there are likely more people interested in this one that the other. This project contains test bench code. UartDebuggerR1.zip
  3. 2 likes
    @Hi @jpeyron, I think I've found something interesting. In a German online store you can buy a Pmod-Compatible CAN transceiver: https://shop.trenz-electronic.de/de/TEP0001-01-Pmod-kompatibler-CAN-FD-Transceiver-industrieller-Temp.-bereich Just bought it and will try it out. Best regards, Thomas
  4. 2 likes
    Dear @Tickstart I might be too late to bring this but hope not. 1. It is typical to use switch - case construct for designing finite state machines. Xilinx even included synthesizable language templates. When you are in the VHDL design window you can see it the Vivado help (click light bulb icon), see the snapshot of it. Using flip-flop seems to be the hardest way to me, however, it is a matter of choice. 2. There is a Digilent project called Active Power Meter reference design with an example of SPI using FSM posted here I would suggest to simulate it for better understanding. Good luck!
  5. 2 likes
    Hello Digilent Community, I am now officially done with my term and I want to share what my experience was like, as per @D@n's question. I would like to attach our final report here (we got an 86 on it, so please understand that it won't be the rest report haha). It was quite rushed since my partner and I were travelling during the last few days before the turn in date and the code in the appendices are quite scuffed. Vivado won't print PDFs in color and I haven't figured out how to fix the sizing or formatting, which is really inconvenient because it looks bad and not easy to read. If anyone has any questions about the code or writing at all, please feel free to private message me or just respond on this forum by tagging me! The idea behind how we wanted it to work, what it actually became, the struggles we had, and our theory on why it did not work again are included in the report along with our VHDL files and some testbench images. If they end up being too small of pictures, just let me know and i can attach the original ones here so it's easier to see. Thank you all for your help and consideration; it means to the world to me now and it meant the world to me before while I was working on this project.
  6. 2 likes
    Hi, I have been working on a PMOD TFT LCD that can be used to play video directly from the FPGA using only two PMODs. I designed the hardware a couple of years ago but recently I had to do a project where I needed to use the Vivado block diagram interface. I thought it was pretty cool how fast it was to put a design together so I went about making an IP Core that controlled the PMOD. It has an AXI Lite interface used to initialize the LCD and then a AXI Stream interface that can be connected directly to a VDMA core. I ended up making three different demos including the following: Using the Microblaze to write directly to the screen. I wrote another core that behaves like a console output that will write directly to the screen for you so the MCU doesn't need to write the console stuff to the screen. I streamed video. Unfortunately this was harder than I expected and had to use the Pynq board instead. Here's a video of it working. I wrote a project page on hackaday.io with more details https://hackaday.io/project/25333-pmod-tft-board I was thinking of trying to sell the boards but I didn't know if there would be any interest. Dave
  7. 2 likes
    @Tickstart The simulator can have issues with figuring out what a signal should be when it is derived from itself or another signal that is derived from the first signal. This is only a problem when the signal is not initially defined or all of the paths to derive it depend on it. I am more familiar with verilog, so take vhdl suggestions from me with that in mind, but the following is what I would suspect would help fix the problem. //file D_flipflop.v: //Verilog Before: `timescale 1ns / 1ps module dff ( input clk, input d, output reg q ); always@(posedge clk) q <= d; endmodule //Verilog After: `timescale 1ns / 1ps module dff ( input clk, input d, output reg q ); initial q <= 0; always@(posedge clk) q <= d; endmodule And my attempt at VHDL for the same thing: //File D_flipflop.vhd //Before: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity D_flipflop is Port ( clk : in STD_LOGIC; d : in STD_LOGIC; q : out STD_LOGIC ); end D_flipflop; architecture Behavioral of D_flipflop is begin name: process (clk) begin if rising_edge(clk) then q <= d; end if; end process name; end Behavioral; //File D_flipflop.vhd //After addition of initial value: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity D_flipflop is Port ( clk : in STD_LOGIC; d : in STD_LOGIC; q : out STD_LOGIC := '0' ); end D_flipflop; architecture Behavioral of D_flipflop is begin name: process (clk) begin if rising_edge(clk) then q <= d; end if; end process name; end Behavioral; My other suggestion would be to take a look at the RTL Analysis -> Elaborated Design -> Schematic for your project, this tool is used to help figure out what the logical circuits that your design is being translated into are. I've attached the schematic I generated for your design. The important thing here is that looking at the I signal's paths, everything route from I to a 'd' pin goes through an AND gate. This means that if the other input to each gate is undefined, the output of that gate will be undefined. In short, this was just a long way of saying that you probably need to add ' := '0' ' to your D_flipflop file. Hope this helps, Arthur
  8. 2 likes
    @D@n, Tell you what mate I had swapped the yellow cable on my breadboard for the orange one. Once I swapped them over it worked! At least some past of the communication. I send a byte over the MOSI-line and link each bit up to leds on the Basys 3. Each second I increment the data sent (0 - 255) and a pretty binary pattern shows up! =)
  9. 2 likes
    A while ago there was a thread about writing a 'combination lock' design for an FPGA board. I finally got around to updating my Wiki with the design: http://hamsterworks.co.nz/mediawiki/index.php/Combination_Lock A short video of it in action is here:
  10. 2 likes
    When I get this it is usually the uppercase/lowercase of the top level signals doens't match those used in the .XDC file. This is the only place case matters in a VHDL project!
  11. 2 likes
    @artvvb The issue seems to solved after I've added the statement: XScuGic_SetPriorityTriggerType(IntcInstancePtr, INTC_INTERRUPT_ID,0x00, 0x3); Now the applications responds and counts interrupt sisgnals coming fro PL. Regards, N
  12. 2 likes
    Hi @bhfletcher, If you are concerned that the operating temperature is wrong I can tell that it is correct. I personally tested the SMT2 in the -40; +85 range temperature and everything worked without a problem. Regarding the storage temperature, like Jon said, we take it from the lowest level component. I checked them all but I couldn't find the one with -20 to +60. As for the PCB, it shouldn't have any issues. When we are guaranteeing a range it is said that it is functioning in normal parameters. For the PCB alone I will have to contact the factory but for the whole product the temperature is set at the component with the lowest range which from I found is -55 to 125 like Jon said. In this range you should not have issues. Best regards, Bianca
  13. 2 likes
    The trick is your code does not need to infer a block memory generator. It will actually need to explicitly implement the block memory generator INTERFACE. This is because the block memory generator is already being instantiated in the block diagram. You will need to design a state machine in VHDL that properly implements the interface. For a description of the signals (en, we, addr, etc.) you should refer to the block memory generator Product Guide. You can find the guide by double clicking the block memory generator IP and selecting Documentation in the upper left corner. The end goal will be to create a custom IP core that contains this custom VHDL. Since you do not have an AXI interface on your core, this should be pretty easy. I believe you can just create a new project that targets the ZYBO and has its top level ports be the desired ports on the IP block. Then I think you can run the Create and Package IP wizard from the tools menu to convert the project to an IP core so it can be inserted into you block diagram (which will be in a different vivado project). I'd recommend simulating your project before you convert it to an IP core to help make sure it is functioning as expected. BTW, you can just expand the BRAM_PORTB interface on the block memory generator IP core and manually connect each of the signals to your IP core if you have difficulty making you custom IP implement the BRAM interface. See the picture below for an example of what your end goal will be:
  14. 1 like
    I have never tried this app note. I will, when I get the chance, but no promises.
  15. 1 like
    Hi @RichardV, Here is a forum thread that might be useful for setting up the axi quad spi. Here is the AXI Quad SPI v3.2 LogiCORE IP Product Guide. I believe when you add the axi quad spi to your block design you can right click on it and run an xilinx made IP example to see how it is used. cheers, Jon
  16. 1 like
    HI @RichardV, I have attached a project in vavado 2016.4 with the cmod A7 and the PmodSF3 using JA. The sdk code is not 100% working but the block diagram is how you would connect it. If you are wanting to use different I/O pins other than JA then you would make the Pmodout external and constrain them with an xdc file. I know we are in the process of fixing the PmodSF3 IP core but we do not have an ETA. Here is a forum that discusses the PmodSF3. The project i attached has the main.c, PmodSF3.h and PmodSF3.c whihc a few changes from the forum thread I linked to which is closer. Also here is a tutorial about IP's that is going to be updated in the near future. cheers, Jon PmodSF3.zip
  17. 1 like
    @jpeyron https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-led-demo/start
  18. 1 like
    Hi @Nick Try using .alldata to get all the acquisition data. The .data returns only the visible samples. Thank you for the observation.
  19. 1 like
    The values that are read back over AXI are modified by changing what the "reg_data_out" register is set to. There should be a case statement in the IP wrapper that looks a little like this: 2'h0 : reg_data_out <= slv_reg0; 2'h1 : reg_data_out <= slv_reg1; 2'h2 : reg_data_out <= slv_reg2; 2'h3 : reg_data_out <= slv_reg3; This case statement needs to be modified so that on the appropriate read address, reg_data_out is set to your result. Hope this helps, Arthur
  20. 1 like
    Hi @Mark1000 The WaveFroms 2015 (v3) Windows installer can be launched in silent mode from command prompt or batch script: > digilent.waveforms_v3.5.4.exe /S /AllUsers In order to use the local version of the requirements, have these setups in a directory named "Kit" next to the installer. You can also install these before installing WaveForms, but a restart is required in between. - WindowsInstaller (this is only needed for Windows XP without SP) file: WindowsInstaller-KB893803-v2-x86.exe http://download.microsoft.com/download/1/4/7/147ded26-931c-4daf-9095-ec7baf996f46/WindowsInstaller-KB893803-v2-x86.exe - VC runtime 9 (2008) x86 SP1 + MFC update (needed by Adept Runtime and custom DWF SDK applications) file: vcredist_x86.exe http://www.microsoft.com/downloads/info.aspx?na=41&srcfamilyid=a821847e-4c44-45c0-9128-61c822bb3280&srcdisplaylang=en&u=http%3a%2f%2fdownload.microsoft.com%2fdownload%2f5%2fD%2f8%2f5D8C65CB-C849-4025-8E95-C3966CAFD8AE%2fvcredist_x86.exe On 64 bit Windows the following are also needed: - VC runtime 9 (2008) x64 SP1 + MFC update (needed by Adept Runtime and custom DWF SDK applications) file: vcredist_x64.exe http://www.microsoft.com/downloads/info.aspx?na=41&srcfamilyid=a821847e-4c44-45c0-9128-61c822bb3280&srcdisplaylang=en&u=http%3a%2f%2fdownload.microsoft.com%2fdownload%2f5%2fD%2f8%2f5D8C65CB-C849-4025-8E95-C3966CAFD8AE%2fvcredist_x64.exe - VC runtime 12 (2013) x64 (needed by WaveForms application) file: vcredist12_x64.exe https://download.microsoft.com/download/2/E/6/2E61CFA4-993B-4DD4-91DA-3737CD5CD6E3/vcredist_x64.exe Command line argument: /S - Silent mode installation without GUI. The driver installation might ask for allowance. /CurrentUser|AllUsers - Create shortcuts for current user or for all users. Only available on first install, when no other Digilent Software is installed. /QuickLaunch - Create Quick Launch shortcut only for Windows XP. /LogFile="log file" - The installer will append the installation log file to this. The log file must exist. /Architecture32 - Force to install 32bit version of WaveForms application on 64bit systems. /D=path to install - Install directory. It must be the last parameter used in the command line and must not contain any quotes, even if the path contains spaces. Only absolute paths are supported.
  21. 1 like
    Thanks for your answers, the truth is that it switches from SPI to UART, and can send information from arduino to fpga. But thanks to you I learned new things, I hope that the questions were not so simple, but how little I have been learning on my own since in my school practically we did not see any programming in fpga and they also asked me for a Semester project.
  22. 1 like
    Hi @MJ_SAL, Unfortunately, We do not have the MTFB for the JTAG_SMT2-NC. For your second question, the typical current consumption from VDD (at 3.3V, VREF = 3.3V as well) is 9.5mA with no USB cable attached. With the USB cable attached and no data transfer its 55.5mA. During data transfer its 60.4mA average (with a few spikes to 78mA). The typical current consumption from VREF (at 3.3V with VDD = 3.3V) is 26uA with no ongoing data transfer, regardless of the USB cable. With a 15MHz data transfer the current consumption is 6mA. thank you, Jon
  23. 1 like
    You can refer to many good advice on my thread in which I tried doing the same thing. I have functional SPI code between the Arduino and the Basys 3 now thanks to the help from this forum and AVRFreaks. http://www.avrfreaks.net/forum/solved-spi-m328parduino-uno-r3
  24. 1 like
    Hello @shubham dwivedi, and welcome to the forum! You sound like you are on the right track, but let me offer you some pointers (it's all I can offer, since you haven't posted any code ...) Starting with a signal generator is perfect! Keep that up, it's about as good of a test source as you will get Don't try debugging with the FFT until you know you are getting the right samples from the ADC Be careful with the clock issue--there's a trick or two involved in handling a 1MHz signal with a 100MHz clock. You'll want to make sure you are looking at only the right values Record samples from your device, and download them to your machine for graphical processing. I prefer processing things with Octave. Get away from a trace viewer as soon as you can--they just obscure the digital signal processing reality you are looking for (i.e., harder to see analog waveforms, harder to recognize analog waveforms in the middle of all the other surrounding logic, harder to visually separate the values of interest on every 100th clock from the other values, etc) If you haven't done so already, explore your results using a histogram. In my experience, one common problem with ADC's is getting the bit ordering right. A histogram will help you debug that. Sine/cosine waves and square waves have very clear histogram signatures--use them. Hope this helps! Please write back and let us know how you are doing. Sending code or traces from the component will also help us understand as well. Dan
  25. 1 like
    The XADC is a Dual 12-bit ADC. 1MS/s ADC. You are you getting the data off of the ARTY for analysis? Or are you using a Microblaze CPU? Are you getting 1,000,000 reading per second? The ADCs are shared between multiple channels, so if you have 5 channels enabled you will at best only get 200k samples per channel. It can also be set up as bipolar or unipolar mode - are you sure you have it configured right? can you show any of your configuration? For unipolar signals the XADC's range is only from 0.0V to 1.0V - are you sure you are not driving it out of this range?
  26. 1 like
    Hi @rappysaha, For the FMC you should be using the pins labeled FMC_CLK0 or FMC_CLK1... these pins were designed for clock input from the mezzanine to the board. I have reached out to my co-workers to see if they have any input on your second question. Have you looked into the clocking wizard? cheers, Jon
  27. 1 like
    Hi Sam, May I suggest to elaborate what is it you want to make. It will help others to help you. Based on my knowledge there are at least two type of constrains, one describing physical interface that is binding of the internal logic to the chip pins and the second is about timing constraints. I assume that you are asking about the first one. I am not aware of any possibility to generate such constraints automatically because it is highly dependent on PCB routing which is different for every board. Typically this is decided by the board designer during optimization process. For every commercial board manufacturers include .xdc file describing all connections to installed ports: Pmods, RS232, etc. Since you are using Zedboard you can uncomment statements in .xdc file and rewire some of default connections, for example if you want to use XADC for reading expernal voltages. Xilinx DocNav is the place to learn about constraints. In my experience it is not the easiest but this is information from the first hands without distortions. Good luck!
  28. 1 like
    @jpeyron thanks for the 3D data, it's just in time for me to integrate multiple boards into a chassis. Can I briefly say the 10GbE fiber interface from the FMC connector works. The IBERT runs over 10 min without logging any error from the fiber channels (SFP+) in the Vivado Serial I/O Links panel. Also I put two SATA connectors for cheap internal connection, those SATA connections also run stable under 10GbE until the SATA cable been touched. So the fiber is a lot more reliable and I'll probably run half of the speed for the SATA based internal connection.
  29. 1 like
    Hello I'm trying to take an FFT on the FPGA after getting sampled data comes from XADC , but i couldn't get any results ! Here i figured out that the problem might be from the XADC's data , i tried to fix it but so far still no results . In my design i'm inserting an analog input signal to VP/VN pins on XADC header , then i'm trying to get some data comes out from the 1MSPS XADC . When i plot the output data it looks as it sampled correctly , but when i try to take its FFT whether on FPGA FFT CORE or on MATLAB , i get no results . The sampled signal and its FFT are shown below in the pics . Also i tried many frequencies for the input signal starts from 10KHz up to 480KHz , but they are all giving the same result , empty window in the Freq-domain . If someones know what's the problem i would really appreciate the help . Regards
  30. 1 like
    thanks a lot for the super thorough response @jpeyron! Looking forward to a patch on the IP
  31. 1 like
    Hey @SkeptoLogic, Testing the configuration and mode settings you provided, I am getting similar outputs to what you stated you were reading (if I am understanding your post correctly). I am currently working on a library for the pmodAD5, so as I finish it up I should be able to give you some more definitive answers. In my recent experience with the AD5 though, and having read through the datasheet as well, I too have been having some difficulty deciphering differences between certain actual outputs and my expectations. Sorry for not having a whole lot of info for you at the moment, but I should have something more next week as I look into this further (and hopefully a library to share). Regards, Nate
  32. 1 like
    Hi @agaelema Currently you can use the script for such purpose:
  33. 1 like
    Hi @agaelema Sorry for this problem. It is fixed for the next software release. Thank you for the observation.
  34. 1 like
    Here's my new and improved design: That's actually more what I had in mind but since I didn't tie the input to a clocked module (DFF in this case) I thought I was "missing" a delay cycle. Simulation: I - Input Q - Slightly delayed output that should be a "clean" input I. I_R, I_F - rising- and falling edge
  35. 1 like
    @Tickstart, I'm not sure I understand from your description above ... what are you trying to do? The high level description, please ... Thanks, Dan
  36. 1 like
    Hi Jon, That was the problem, Waveforms 2015 has it working. thanks, Bob
  37. 1 like
    Here's how it turned out: And here's the schematic for the synchronizer curcuit we were discussing earlier. I am almost proud of myself, I think it's a neat design.
  38. 1 like
    Hi everyone! Today I present you another interesing project! This project is one application in SDSoC that contains a plugin architecture for standalone system. You can use this for develop interesting things, like an image or video processing platforms that you want add some filters without change the internal code. Into the project you can read how works. If you have doubts wrote here! Enjoy! See you soon!
  39. 1 like
    @mihai5, Sometimes it helps to actually name someone within the system. That'll send them an e-mail and an alert that there's something in a given conversation they want to know about. To do this, type an @ followed by the persons screen name. As you do so, a menu should come up. Select the persons name that you want to alert from the menu, and their name will be highlighted (like yours above). Since you want to get @jpeyron to notice a forgotten post, tagging him in this manner helps. As a guess, I'm thinking he might be trying to let @sbobrowicz know about your post but .... I'm only guessing at the internal structure of Digilent's operations. Dan
  40. 1 like
    Yes, I confused the uppercase/lowercase of 'x' in the top level and the XDC file as I thought it didn't matter, Thank you.
  41. 1 like
    Hi @attila, The problem is solved. Using the functions from dwf.dll I am able to mimic the behaviour of WaveForms "Auto sync" in Labview. Just in case someone runs into the same problem I post the working VI. Thank you very much for your help! testscope4.vi
  42. 1 like
    @Clarissa, You wrote in the original post:"Dose it mean that if I set the SET_VADJ(1:0) on 11, the VADJ voltage = 3.3V, so the FMC signalss' I/O standards can be set as LVTTL? " I assume that you're working with an FMC mezzanine card that replaces the old FX2 interface. It's important to follow my previous advice by checking all of the FMC voltage connections that are connected to the logic through this FMC card. In particular make sure that: - only the Nexys Video board is sourcing the 12V0, 3V3, and VADJ pins. Also that everything connected to these pins is compatible with those voltages. - any logic connected to the GA0 or GA1 pins is 3.3V compatible - any logic connected to any of the FMC logic pins is really is LVCMOS33 compatible. LVCMOS33 and LVTTL33 are not exactly the same. Once you have satisfied yourself that everything is OK then, you would want to do what you have stated above, I use a big counter that stops counting before it rolls over to 0 to time the operations stated in the manual. I assume that you didn't check out the code in the DIfferential PMOD Challenge. I've posted the toplevel module here. You'll want to set set_vadj <= "11". Look over the process that controls vcnt. Your implementation will depending on the clock frequency that you are using of course, but I'd suggest that you use my timing as a minimum. You'll want to allow for the power supplies to settle. As far as I know Digilent has never offered guidance on how to follow the instructions in their manual. There's one aspect of my code that you should note. If areset is asserted VADJ is disabled and the whole procedure is repeated. You may or may not want to do this. I suggest that you prove to yourself that the VADJ voltage is really working as expected by using an oscilloscope to capture VADJ before connecting your FMC mezzanine card. As written you can check this by asserting areset. Note that the switches and all but the CPU reset button use the VADJ supply ( likely there are more things using Vadj) .... Also note that the CPU reset button is doesn't have any hardware conditioning to correct contact bounce so you may want to debounce CPU reset in you code if that's what's used to assert areset. If you don't understand anything that I've already stated in this thread you'll have to address specifically. NexysVideo_SDR_Test.vhd
  43. 1 like
    @Tickstart, It's not a debouncer, but a synchronizer, even though it may have much in common with a debouncer. Unlike a debouncer, you want the synchronization to take place as fast as possible. Hence ... only two clocks. Some folks suggest three, I've never heard anyone suggest more than three--it's all a matter of the reliability you wish to create. Debouncers often have programmable wait intervals ... synchronizers have only the two clocks. Dan
  44. 1 like
    Hi @anuar, Looking at the tutorial you link to above here there is two different ways to download the same project made for Vivado 2016.4. I just completed this project in Vivado 2016.4. You first load the project into vivado 2016.4 using the tickle script. I then generate a bitstream, then export hardware and launch sdk. Once in sdk I import the dma and dma_bsp from in my case the path C:\Users\jpeyron\Desktop\Zybo-DMA-master\sdk. Then you program the fpga and then right click on dma and run as launch on hardware(system debugger). I attached a screen shot of teraterm(baud rate needs to be at 115200) and my project as well. cheers, Jon Zybo-DMA-master.zip
  45. 1 like
    @anuar, First of all you need to understand that Vivado is a tool which primary focus is configuring the chip hardware, both the ARM that is PS and the FPGA which is PL. This might require HDL programming but not always. In the case of the DMA example I believe HDL programming is not necessary. Vivado generates important hardware definition files, for example xparameters.h, for the EDK. The main purpose of the EDK is programming of processors either ARM or Microblaze if they are included in the project. Anyway, Vivado and EDK are complmentary and should be used together in sequence. The 2017.1 version works fine for me so far in manual mode. TCL scripts are typically written for the specific Vivado version and quit if the version does not match. You can try to edit the version in the script but it might not work. When starting EDK from Vivado give it some time to load all libraries and .h files generated in the Vivado otherwise you might see error messages and warnings in the C-code. I also recommend to watch training videos and read Xilinx tutorials. It will save you from a great deal of frustration. Good luck!
  46. 1 like
    Prompted by another thread here ( https://forum.digilentinc.com/topic/4180-mmcm-dynamic-clocking/ ), I've been experimenting the the Dynamic Reconfiguration Port on the Artix-7 MMCM You can find the code and constraints for the Basys3 here: http://hamsterworks.co.nz/mediawiki/index.php/MMCM_reset It might be of interest to somebody (e.g. to change a VGA clock frequency dynamically).
  47. 1 like
    Hi @r4d, I have reached out to our senior layout engineer about you question and will respond back on this thread when I get a response. thank you, Jon
  48. 1 like
    Hi @russan Unfortunately clock stretching is not supported, but I will try to add support for this in the next software version. The Protocol interface takes control over the device Patterns and Logic resources, so these can't be used simultaneously, except in Debug mode when it only uses the Patterns resource.
  49. 1 like
    Hi @s21jb By increasing the bus (or interpreter) row high in Logic Analyzer you will see the analog representation of the value. With the following script you can export the I2S data to csv. Then you can import it in Scope (under File menu) for further processing. var rg = Logic1.Channels.I2S.events //events var rgt = Logic1.Channels.I2S.eventStamps // event time stamps var c = rg.length-1 // number of events var i = 0 if(rg[0].charAt(0)!="R") i++ // make sure to start with right var file = File("~/Desktop/i2s.csv") file.writeLine("Time,Right,Left") for(; i < c; i+=2){ // trim leading R/L char // normalize to +-1 for 16 bit signed values var v1 = parseInt(rg[i].substring(2))/32768 var v2 = parseInt(rg[i+1].substring(2))/32768 file.appendLine(rgt[i]+","+v1+","+v2) }
  50. 1 like
    @Clarissa I was in a hurry to do something else and didn't complete my thought for my last post. When you use the FMC connector the IOSTANDARD needs to match whatever device is on the FMC mezzanine board. This could be 3.3V, 2.5V or 1.8V. Note that the 12V, 3.3V and Vadj rail are connected to the FMC connector AND FPGA IO banks Vcc pins. You can blow up your FPGA if not careful. Fortunately, Digilent has improved their FMC voltage supply designs though I prefer the Genesys2 design. My point is this; whenever I do a design on the Nexys Video using an FMC mezzanine board I am hyper careful.. like I am when I use a radial arm table saw. This is my basic check-list: 1 Check all FMC signals on the mezzanine board schematic paying special attention to the VCC3V3, VCC12V0, and VADJ pins. I always verify the constraints pins assignments agree with the Nexys Video ( or any FPGA board ) schematic. 2. Find out from the mezzanine board's documentation what the IO voltages are for the device(s) connected to the FMC connector are. This will tell you what Vadj on the Nexys Video board has to be. Understand that ALL pins on all IO banks on the Nexys Video board that use the Vadj rail have to have compatible standards. This also means that you may have to change IOSTANDARD assignments in your constraints file for other IO pins on the Vadj powered banks that you are using, like buttons, switched, LEDs etc. or bitgen will give you a DRC error. The idea is that the FPGA IO that are connected to anything on the FMC mezzanine card have to be compatible with the mezzanine card devices IO... AND the Vadj voltage has to compatible with that IOSTANDARD. AND all pins on those banks have to be compatible with the Vadj voltage. This isn't quite as complicated as it sounds. If your mezzanine card uses 3.3V differential LVDS then Vadj has to be 3.3V and your IOSTANDARD will be TMDS_33 ( because that's the only 3.3V differential IOSTANDARD available ) Any other pins on the Vadj powered IO banks will be LVCMOS33 if they are single-ended. 3. Once you know what Vadj needs to be you have to go through your constraints file and make sure that all the signals in your toplevel entity port list that are connected to Vadj IO banks are compatible with that voltage. It would be nice if Digilent made this a bit easier. I make a habit of listing the IO bank in the toplevel design comments: -- General I/O resources btnc : in std_logic; -- Vadj HR Bank 16 normally '0', '1' when pressed btnd : in std_logic; -- Vadj HR Bank 16 normally '0', '1' when pressed btnl : in std_logic; -- Vadj HR Bank 16 normally '0', '1' when pressed btnr : in std_logic; -- Vadj HR Bank 16 normally '0', '1' when pressed btnu : in std_logic; -- Vadj HR Bank 16 normally '0', '1' when pressed sw : in std_logic_vector(7 downto 0); -- Vadj HR Bank 15 or 16 led : out std_logic_vector(7 downto 0); -- VCC2V5 HR bank 13 4 Check EVERYTHING 5. Check EVERYTHING AGAIN 6 Do something else for 5-6 hours, or better yet wait till the next day and then check EVERYTHING again 7. If you can generate a bitstream for your design without bitgen complaining about incompatible IO assignments you can connect your mezzanine board to your Nexys Video with the power cord disconnected. The power switch on my Nexys Video has failed.... Things get a bit more complicated for the Genesys2 as the Kintex device has HP IO banks and HR IO banks... The good news that I have is that I've done designs using 5 different FMC mezzanine boards on both my Nexys Video and Genesys2 boards without either of them violating the "NO SMOKING" ban in my lab. Again, you can check out one way to handle FMC Vadj in my code in the Project Vault Differential PMOD Challenge code.