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Showing content with the highest reputation since 05/25/19 in all areas

  1. 3 points

    FTDI chip not recognized anymore

    I have not had any activity listed when trying the "dmesg" so I went to buy a new cable, and that actually was it. Thank you for the hint!
  2. 3 points

    FTDI chip not recognized anymore

    I think it's Linux... Try the "dmesg" command immediately after plugging or unplugging. It should show some related events. The obvious, try with a different computer and a different cable. Especially cables fail often.
  3. 2 points

    FIR compiler 7.2 stopband

    ... and how about a simple impulse response test (feed a stream of zeroes with an occasional 1 and check that the filter coefficients appear at the output). Just wondering, isn't there a "ready / valid" interface also at the output if you expand the port with "+"?
  4. 2 points

    FIR compiler 7.2 stopband

    @Ahmed Alfadhel, Why not run a simulated sweep through the band and read out what the actual filter response is? Dan
  5. 2 points
    Hi @NikosFotias, I heard back from our design engineer about this; the recommend input ranges are 0V to 5V, but the absolute maximum ratings for the PWM inputs are -58V to 58V. Thank you, JColvin
  6. 1 point
    Hi @jamesbraza Yes, you are right. The application, the IA measures the DUT relative to a reference resistor, using the Scope Channel 1 vs 2 inputs. From this it can calculate the voltage/current. Taking in consideration the scope probe impedance and open/short compensation can calculate further values: impedance Z/Rs/Xs (Rp/Xp rarely used); admittance Y/Gp/Bp (Gs/Bs rarely used); series or parallel equivalent inductance or capacitance... See the following documents: https://cdn.testequity.com/documents/pdf/series-parallel-impedance-parameters-an.pdf 1.6 Equivalent circuit models of components, page 13 : https://literature.cdn.keysight.com/litweb/pdf/5950-3000.pdf
  7. 1 point

    JTAG-HS3, FT232 chip erased

    Hi @thk3695, I sent you a PM about this. best regards, Jon
  8. 1 point

    Pmod da3 reconstruction filter

    Hi @lwew96, We have not used a reconstruction filter. I did find a paper that discusses a reconstruction filter with the AD5541 here. Hopefully one of the more experienced community members will have some input for you as well. best regards, Jon
  9. 1 point
    Hi @jamesbraza, I'm not an expert on the internal workings of WaveForms (that'll be @attila) but I'll see if I can answer your questions: What is the purpose of marking as series or parallel -- The purpose of looking at the series or parallel configuration is because you will get different results depending on the configuration; this website illustrates this for a set of 3 capacitors. Does WaveForms do additional computations with this information? -- Aside from the other impedance things that can be calculated (admittance, inductance, etc), I don't believe it does anything else. What if my DUT has multiple inductors/capacitors in a network, such that they are sort of both in a series/parallel arrangement? -- Generally, I imagine if you were interested in the individual sections you would measure them separately. Admittedly, I'm not certain the best way to consider an overall system if you are just treating it as a black box though. With regards to the Element parameter, I'm not certain. I would also recommend looking at this thread for some additional details. Thank you, JColvin
  10. 1 point

    FIR compiler 7.2 stopband

    @Ahmed Alfadhel, (Just read the prior, prior note--showing the beginnings of an impulse response ...) To get the "answer" from a trace file, there's a couple of things you can do: I use gtkwave for viewing traces. It has the option to view something as an analog value. You can do that and generally reflect that your impulse response has the right shape. That's useful, but it won't get you from a -20 dB stopband to a -80 dB stop band. What you really need to do is to take that impulse response and run an FFT on it. No, I don't mean dumping the impulse response into an FFT component, but rather taking the values of the impulse response from the filter and sending those values into an FFT. This often requires the ability to save values from your trace into a file of some kind of type that Matlab or Octave can read. I've done the same with a filter of my own, and you can red my report on it (and the links to how I did it) here. Dan
  11. 1 point
    Hi @YaBoyRock, Glad to hear you were able to find the demo's in question. best regards, Jon
  12. 1 point
    Hi @YaBoyRock, There are two demo's available for the DJTG one is called DJTGDemo and the other is called DJTGTwoWireDemo as shown in the attached screen shot below. Its my understanding that the DJTGDemo is made to work with a 4-wire set up. best regards, Jon
  13. 1 point
    Hi @jamesbraza, The series vs parallel values for resistance/reactance/inductance/etc refer to the device or system you are measuring these traits of, i.e. are the resistors and/or capacitors arranged in a series configuration or are they arranged in a parallel configuration. The reason both are listed in the Impedance tool is because the WaveForms software does not know how the device under test (the DUT block shown in the images of the 'impedance.html' page) is organized since it just applies a waveform and compares what the two oscilloscope channels see as the response and performs a variety of calculations to get the values you see in the Meter and Analyzer views. Let me know if you have any questions about this. Thanks, JColvin
  14. 1 point
    Hi @YaBoyRock, Welcome to the Digilent Forums! It my understanding that the DtjgDemo.cpp is made for 4-wire. Is there a specific function in the DjtgTwoWireDemo.cpp that you are interested in? Have you looked at the Digilent Adept JTAG Interface(DJTG) Programmer's Reference found in the \digilent.adept.sdk_v2.4.2\doc folder? best regards, Jon
  15. 1 point

    FIR compiler 7.2 stopband

    @Ahmed Alfadhel, Cool, you know how your filter should respond! But ... does it respond that way? You were suggesting that your filter wasn't working. One of the first things to check is whether or not the filter, as implemented, continues to have the response you designed. Measuring the impulse response, and then comparing it to your predicted response above, can be valuable to that end. There are a lot of bugs that might get caught by this, to include issues associated with properly setting the coefficients in memory, truncating them to fixed bit widths, etc. Dan
  16. 1 point

    FIR compiler 7.2 stopband

    yes, it's the highest positive 16 bit signed number 32767 (0x8FFF is the smallest negative number, -32768). You could also consider 0x4000, which is a single bit, makes your coefficients easier to recognize in the output (because multiplying with this number is a single bit shift operation).
  17. 1 point
    Hi Jon, That makes sense, I guess I shouldn't expect consistent results out of undocumented behaviour. Thanks again for all your help. I think that solves my problem, though in the process of solving this one, another problem came up. I guess thats a topic for another thread... Thanks, Daniel
  18. 1 point

    Cora Z7 - Booting - Terminal

    I figured out why it wasn't working...On Digilent github, it said to only copy _pre-built/linux/images/BOOT.BIN_ and _pre-built/linux/images/image.ub_ to the SD card. Instead, I copied all the files in the _pre-built/linux/images/ directory and the bitstream to the SD card. It's working now and I see the boot process in my UART terminal.
  19. 1 point
    Hi @dmishins, Welcome to the Digilent Forums! Please attach a screen shot of your Block design. Did you connect the 200 MHz clock to the MIG as instructed in section 10? What did you set the local memory and cache when running clock automation for Microblaze? best regards, Jon
  20. 1 point

    BASYS3 and Axoloti

    Thanks @OvidiuD, I'll take one step after another and the forums are quite a good source of knowledge. So far, I plan to start with very basic schemes in order to understand how Vivado works. Then I will work on communicating with the Axoloti through SPI. Best regards
  21. 1 point

    pmod wifi

    Hi @harika, The board connects to the router through the Pmod WIFI. That is why you need the login and password for the router added in the HTTPServerConfig.h. The mode jumper would be set to SD if you were booting your project from the SD card reader. In this case the project is just using the SD card reader and not booting from the SD card reader. You should have the Mode Jumper set to JTAG. best regards, Jon
  22. 1 point

    FIR compiler 7.2 stopband

    true but it's a five-line job e.g. in Verilog reg[15:0] counter = 0; reg [15:0] impulse = 0; always @(posedge clk) begin counter <= counter + 1; impulse <= (counter == 0) ? 16'h7FFF : 0; end plus the protocol interface (e.g. trigger a new valid sample if counter[7:0] == 0)
  23. 1 point
    Hi @m72 The preview will represent such corner cases correctly in the next software release. Thank you for the observation.
  24. 1 point
    Hi @jpeyron @xc6lx45 Thankyou for the quick reply! Changing the clock frequency setting worked!! Thanks a lot!
  25. 1 point

    LabVIEW and IIO data sources

    Thanks for pointers.
  26. 1 point
  27. 1 point
    I did some research on Xilinx.com and found this answer record: https://forums.xilinx.com/t5/Embedded-Development-Tools/XSDB-Server-ERROR-Hsi-55-1545-Problem-running-tcl-command/td-p/834915 I had two floating inputs on my concatenation block and once I connected these project creation proceeded correctly.
  28. 1 point

    Nexys4 DDR- USB-UART Bridge (J6)

    @jpeyron Thank you very much for your cooperation
  29. 1 point

    micro-USB cables for Zedboard?

    Hi @GMA, As long as they are not "charging only" cables, then yes they will be able to transfer data as well. Naturally, the cables do not facilitate the software side of the data transfer, but there are a number of existing materials to help get the software side of things working. Let me know if you have any other questions. Thanks, JColvin
  30. 1 point
    Hi @sgrobler, I guess it hasn't been updated for OpenLogger; I personally wasn't aware of an Android app for WFL in the first place. I'll ask about the plans for that, though I suspect since I don't recall hearing about it that there aren't any immediate plans to get it updated. I do agree about the phone browser not being ideal; even in landscape mode, it's difficult to see any relevant details. Thanks, JColvin
  31. 1 point

    ZedBoard and PmodCAN

    Hi @YellowYoung, Welcome to the Digilent forums! The PmodCAN facilitates CAN communication to another device through the PL.The PmodCAN uses SPI communication to communicate between the host board and itself. It would not be able to connect to the CAN on the PS. To use the CAN bus on the PS you would need to use the MIO Pmod JE1 as discussed in the user guide for the Zedboard here in section 2.9.2 Digilent Pmod Compatible Headers (2x6). The user guide states the bank that the MIO pins are connected to a 3.3V bank so you would need to make a level shifting circuit for CAN communication to work since CAN uses voltage level as part of its communication. If all you need to do is communicate data from the Zedboard using CAN communication. Then you can send data from the PS to the PL and then send that data through the PmodCAN. Here is an Avnet forum thread that discusses sending data from the PS to the PL. Here is a Xilinx forum thread that initially discusses how they accomplished sending data from the PS to the PL. best regards, Jon
  32. 1 point

    FIR compiler Amplitude

    My first guess is that the tool needs to know the position of the decimal point of your number format. It's off by 20 bits (=> 1048576 => 120 dB). Fixed point knows only integers, so it's a matter of interpretation.
  33. 1 point
    Yep, seen that they were back online. Thanks, Jon
  34. 1 point

    Howdy from NorCal

    Thanks Jon. And thanks for the links. Cheers, Jon
  35. 1 point

    Is C or C++ faster?

    You should maybe give more background. Otherwise the answers will be only as good as your question. C is faster because... C++ is faster because...
  36. 1 point
    @sgrobler: I've tweaked the project to hopefully make it simpler to install the dependencies (Kaitai Struct v0.9). If you have Python 3 installed, it should simply be a matter of: % git clone https://github.com/bdlow/dlog-utils-portable.git Cloning into 'dlog-utils-portable'... remote: Enumerating objects: 26, done. remote: Counting objects: 100% (26/26), done. remote: Compressing objects: 100% (19/19), done. remote: Total 26 (delta 8), reused 20 (delta 5), pack-reused 0 Unpacking objects: 100% (26/26), done. % cd dlog-utils-portable dlog-utils-portable% ls LICENSE dlog.ksy dlogcsv.py requirements.txt README.md dlog.py examples # set up and activate a Python virtual environment: dlog-utils-portable% python3 -m venv .venv dlog-utils-portable% . .venv/bin/activate # install the 0.9 runtime in the virtual environment: (.venv) dlog-utils-portable% pip install -e 'git+https://github.com/kaitai-io/kaitai_struct_python_runtime.git@0e3f6e0#egg=kaitaistruct' Obtaining kaitaistruct from git+https://github.com/kaitai-io/kaitai_struct_python_runtime.git@0e3f6e0#egg=kaitaistruct Cloning https://github.com/kaitai-io/kaitai_struct_python_runtime.git (to revision 0e3f6e0) to ./.venv/src/kaitaistruct Did not find branch or tag '0e3f6e0', assuming revision or ref. Installing collected packages: kaitaistruct Running setup.py develop for kaitaistruct Successfully installed kaitaistruct # run it! (.venv) dlog-utils-portable% ./dlogcsv.py ./examples/openlogger.dlog > openlogger.csv Header Information log format: openlogger stop reason: normal number of samples: 27097 voltage units: mV sample rate: 10E+3 Sa/s delay: 0 s number of channels: 3 channel map: [1, 2, 3] (.venv) dlog-utils-portable% less openlogger.csv
  37. 1 point
    Jon, Thank you kindly for your help - everything worked just like you said! Best, Zhanneta
  38. 1 point
    Hi @FPGAMiner, Welcome to the Digilent Forums. We have not worked with Altera's IDE or on of their FPGA's. The GitHub link for the OdoCrypt FPGA Miner states under requirements that it currently only supports Intel (Altera) FPGAs on Linux hosts. We have not ported one of Altera's projects to work with Vivado/Xilinx FPGA's. We do have petalinux platforms for the Zybo Z7 here. I would think that after installing petalinux on the Zybo Z7 you would then need to duplicate their functions. Unfortunately we have no experience with this process and would not have useful advice. Hopefully one of the more experienced community members will have some helpful input for you. I would also suggest reaching out to the creator of the OdoCrypt FPGA Miner to see if they have any suggestions for getting this project working with a Xilinx FPGA. best regards, Jon
  39. 1 point
    Hi @m72 It will be added to the next software. Thank you for the observation. In case you need it, you can also use the Scope in mixed mode, having Digital/Logic Analyzer channels in the same interface:
  40. 1 point

    fpga kit

    >> is this can be used for controlling of power switches like MOSFET ,IGBT? "yes but" Electronics 101 applies (look at the data sheet of your component: E.g. how much Vds remains with Vgs=3.3 V given the switched current?) You might want to use some intermediate driver circuit for the simple reason of protecting the FPGA against magic-smoke incidents in the power side. For e.g. a traffic light demo, a 10k series resistor to the gate will prevent the worst but this wrecks the switching speed for e.g. PWM.
  41. 1 point
    Hi @skaitmenukas I suppose you have different configuration for Trace than for the Ref traces. When data of multiple traces are exported in one table it takes as guideline the start/stop/samples parameters of the Trace. Make sure to have same start/stop/samples settings when Trace and all the Ref traces where made.
  42. 1 point

    Vivado sysnthesis fail..Pcam

    Hello Dear @jpeyron I've already solved the problem. It was related to selecting wrong language C instead of C++ when creating new application project. PCAM project was written in C++, but I wrongly selected C! After I corrected that mistake, now there is no any linking error. Thanks...
  43. 1 point
    Hi @ammolytics, This forum section will work. It definitely sounds like an interesting project. The main hurdle that I'm seeing with this project is that you will either need multiple Discovery's and OpenLogger to collect all of the analog inputs and the digital inputs. Accelerometers tend to provide their information in a digital fashion (such as through SPI or I2C) so while the Analog Discovery 2 can read in this data, the OpenLogger is not able to directly interpret protocol messages. However, the Analog Discovery 2 needs to be connected to a laptop to store the data, which you stated you do not need. The 3 strain gauges will likely have analog outputs as well as the output from the Magnetospeed Chronograph that you linked, though I don't know if it provides 1 or 2 analog outputs (since it uses 2 hall effect sensors). So that is 3 analog inputs required, plus 2 digital inputs (from the 2 hall effect sensors), as well as 3 digital inputs that will likely require interpretation. Looking at the sources you linked, it does not appear the required sample rate will need to be incredibly fast (guessing based the links where it said the stress wave travels from receiver to muzzle in about 0.12 mS, or 120 microseconds). Based on this, you likely could use a 1 MHz sampling rate (1 microsecond resolution) to capture all of the data you needed, of which the Analog Discovery 2 can achieve, while the OpenLogger will be limited (while using 3 analog inputs) to 166.7 kS/s (6 microsecond resolution), though depending on how many sample points you need, this may be sufficient for you. The main thing I'm getting at is that I don't think that either the OpenLogger or the Analog Discovery 2 will an all-in-one solution for you; the Analog Discovery 2 because it only has 2 analog inputs and you need at least 3 (and it can't store data to an SD card), and the OpenLogger because it doesn't directly interpret data protocols that will likely be coming from the accelerometers. To be fair, the OpenLogger could in theory receive all of the bit-banged data accelerometer data on digital inputs and then you interpret them later, but the logging functionality (or at least the ability to read the logged data) isn't integrated yet and this also presumes that accelerometers will power on and start sampling data in the exact configuration you want upon start-up with no instructions provided to them which is not a guarantee. What I would probably recommend looking into would be using a microcontroller or microprocessor to collect the data and store it on an SD card, since there are a number of microcontollers that have both enough analog and digital inputs and you can program them to to interpret the protocol data from the accelerometers for you and send only the relevant data to an SD card. You'll likely need to use an external analog-to-digital converter if the voltages you are measuring are outside of the ranges that the on-board ADC can accept (usually either 0V to 3.3V or 0V to 5V and Magnetospeed sensor you linked was showing 7.6V to 9V readings). Let me know if you have any questions about this. Thanks, JColvin
  44. 1 point

    Vivado sysnthesis fail..Pcam

    Hi @Sduru, I found a xilinx forum that that discusses this issue here. For their project the .project and .cproject files were referencing an obsolete hw_platform that no longer existed. They manually edited the files to the new hw_platform--now the design worked. Did you use the 2018.2 project from the release page here? Did you import the fsbl and pcam_vdma_hdmi from the sdk_appsrc folder in the Zybo-Z7-20-Pcam-5C-2018.2.1 folder? best regards, Jon
  45. 1 point
    Hi, reading between the lines of your post, you're just "stepping up" one level in FPGA design. I don't do long answers but here's my pick on the "important stuff" - Before, take one step back from the timing report and fix asynchronous inputs and outputs (e.g. LEDs and switches). Throw in a bunch of extra registers, or even "false-path" them. The problem (assuming this "beginner mistake") is that the design tries to sample them at the high clock rate. Which creates a near-impossible problem. Don't move further before this is understood, fixed and verified. - speaking of "verified": Read the detailed timing analysis and understand it. It'll take a few working hours to make sense of it but this is where a large part of "serious" design work happens. - Once the obvious problems are fixed, I need to understand what is the so-called "critical path" in the design and improve it. For a feedforward-style design (no feedback loops) this can be systematically done by inserting delay registers. The output is generated e.g. one clock cycle later but the design is able to run at a higher clock so overall performance improves. - Don't worry about floorplanning yet (if ever) - this comes in when the "automatic" intelligence of the tools fails. But, they are very good. - Do not optimize on a P&R result that fails timing catastrophically (as in your example - there are almost 2000 paths that fail). It can lead into a "rabbit's hole" where you optimize non-critical paths (which is usually a bad idea for long-term maintenance) - You may adjust your coding style based on the observations, e.g. throw in extra registers where they will "probably" make sense (even if those paths don't show up in the timing analysis, the extra registers allow the tools to essentially disregard them in optimization to focus on what is important) - There are a few tricks like forcing redundant registers to remain separate. Example, I have a dozen identical blocks that run on a common, fast 32-bit system clock and are critical to timing. Step 1, I sample the clock into a 32-bit register at each block's input to relax timing, and step 2) I declare these register as DONT_TOUCH because the tools would otherwise notice they are logically equivalent and try to use one shared instance. This as an example. - For BRAMs and DSP blocks, check the documentation where extra registers are needed (that get absorbed into the BRAM or DSP using a dedicated hardware register). This is the only way to reach the device's specified memory or DSP performance. - Read the warnings. Many relate to timing, e.g. when the design forces a BRAM or DSP to bypass a hardware register. - Finally, 260 MHz on Artix is already much harder than 130 MHz (very generally speaking). Usually feasible but you need to pay attention to what you're doing and design for it (e.g. a Microblaze with the wrong settings will most likely not make it through timing). - You might also have a look at the options ("strategy") but don't expect any miracles on a bad design. Ooops, this almost qualifies as "long" answer ...
  46. 1 point
    Hi Fonak, Thanks for your response. Unfortunately, the author or the developer removed the program from the web (probably due to the commercial importance). However, he still has some plugins (eg. audio analyser suite etc.) on his youtube account with download links. I think, the hardware section has several different modifications such as you suggested to use (LT1210, I am not sure from this driver, perhaps a smaller one such as OPA569 etc. can be a lighter version). If I would access to a source code perhaps I would give a try to modificate it with some effort. However, I am not able to reach it anymore. Btw, if you need previous versions of the advertised software on the video I may have in my download folder which I can share privately with you. Best wishes, Ferda
  47. 1 point
    Hi @srce, I have attached the bin file for the Genesys 2 OOB Demo. thank you, Jon genesys_2_demo.bin
  48. 1 point

    Beginner DSP Projects

    Well, if you want my opinion, DSP on FPGA is a fairly specialized niche application. It's a long walk to come up with a project that really fits into that niche, justifying an FPGA (rather pair a $0.50 FPGA for programmable IO with one or more high-end DSPs for the number crunching if someone claims "we need an FPGA"). For studying, it can be "interesting" in a sense that you get to know quite a few dragons on a first-name basis. But then, is it productive to spend weeks on fixed point math when everybody else uses floats on a DSP / CPU when "time-to-market" is #1 priority. Maybe not. DSP is more fun in Matlab (Octave). And there is no point in FPGA for performance unless you have exhausted the options at algorithm level (again, exceptions e.g. well-defined brute-force filtering problems) A lot of the online material is "sponsored" by companies that sell FPGA silicon by the square meter (Yessir. We have Floats!). But this is largely for the desperate and ill-informed (of course, there are viable use cases - say high volume basestations or automotive with need for EOL in a decade or two. As said, a niche application). When you take the direct route, you'll run into a question like, "how on earth could I implement an audio mixing console when the FPGA has only 96 multipliers". Challenge me or anybody who has read some books and you'll find it can be done on a single multiplier (say, 100 MHz at 96 kHz is 86 multiplications per sample for 12 channels. It's just an example. In reality I'd use a few with "maintainability" of the code my major concern). The point is, the skill ceiling is fairly high but so is the design effort. It only makes sense if I plan to sell at least a hundred gazillon devices. On the other hand, if you separate DSP and FPGA, you'll find that a lot of the Matlab (Octave) magic maps 1:1 to real life on any modern CPU platform by importing e.g. the "Eigen" library into my C code.
  49. 1 point

    WaveForms beta download

    3.11.9 digilent.waveforms_beta_v3.11.9_64bit.exe Added: - Scope Spectrogram 3D surface view, for 64bit Windows 3.11.8 digilent.waveforms_beta_v3.11.8_64bit.exe digilent.waveforms_beta_v3.11.8.dmg digilent.waveforms_beta_3.11.8_amd64.deb digilent.waveforms_beta_3.11.8.x86_64.rpm Added: - horizontal cursors for Scope/FFT, Spectrum and Impedance Analyzer - cursor delta as decade for logarithmic scales - Scope: - simple Math channel operations: RMS, ATan - LockIn amplifier as Math channel - XYZ 3D graph, for 64bit Windows Fixed: - Scope/Audio/Tempo option 3.11.7 digilent.waveforms_beta_v3.11.7_64bit.exe digilent.waveforms_beta_v3.11.7.dmg digilent.waveforms_beta_3.11.7_amd64.deb digilent.waveforms_beta_3.11.7.x86_64.rpm minor fixes and improvements 3.11.6 digilent.waveforms_beta_v3.11.6_64bit.exe digilent.waveforms_beta_v3.11.6.dmg digilent.waveforms_beta_3.11.6_amd64.deb digilent.waveforms_beta_3.11.6.x86_64.rpm Added: - Protocol - UART Spy - Max Lines option: log limit to prevent application slowdown - Line Wrap option - tooltips for UI controls listing Script access path - application and script Font options - dark theme support for Script 3.11.5 digilent.waveforms_beta_v3.11.5_64bit.exe Added: - Script open/save text file - application argument: -script myscript.txt/js Fixed: - warnings at low record rates 3.11.4 digilent.waveforms_beta_v3.11.4_64bit.exe Added: - Scope: - set/reset zero offset in each channel option - precision option for measurements Fixed: - Script: access to traces and channels from Instrument.Export - unit conversions V to Ṽ, A to à - I2S 32 bit data 3.11.3 digilent.waveforms_beta_v3.11.3_64bit.exe digilent.waveforms_beta_3.11.3_amd64.deb digilent.waveforms_beta_3.11.3.x86_64.rpm Fixes 3.11.2 digilent.waveforms_beta_v3.11.2_64bit.exe digilent.waveforms_beta_3.11.2_amd64.deb digilent.waveforms_beta_3.11.2.x86_64.rpm Added: - Spectrum, Network and Impedance Analyzer store time data when this view is open Fixed: - runscript argument - loading of docked views geometry 3.11.1 digilent.waveforms_beta_v3.11.1_64bit.exe digilent.waveforms_beta_3.11.1_amd64.deb digilent.waveforms_beta_3.11.1.x86_64.rpm Added: - Scope: out of range warning in measurements - Protocol/UART: - support up to 32bit/word - TX/RX format: text, binary, decimal, hex - Wheel Direction option - Logic Analyzer: option to swap previous/next events - Spectrum Analyzer: allowing higher number of BINs for CZT 3.10.7 digilent.waveforms_beta_v3.10.7_64bit.exe Added: - Spectrum: logarithmic magnitude scale for voltage units - Protocol: datetime stamp for SPI/I2C Spy Fixes 3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom mathematic channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Netowrk Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.
  50. 1 point
    Hello, I'm building this filter, generating a .COE file in Matlab, which I use in the FIR compiler IP. Here are two screenshots of the settings. Do you know if the difference between the two pictures, in terms of magnitude, are just a displaying fact or if there is a real amlpification involved by the FIR compiler ? If it's the case, do you know how to fix it to generate the same filter as I designed in Matlab, so without gain ? Kind regards, Yannick