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  1. 2 points
    attila

    Math on FFT traces

    Hi @lab!fyi We could add math to the Spectrum Analyzer interface. At the moment you could use Script with plot for such purpose. Collect the data in Spectrum Trace 1 and 2, in Script tool View/Add plot and Run the following script: plot1.X.Units.text = "Hz" plot1.Y1.Units.text = "dB" plot1.X.data = Spectrum1.Trace1.frequency var t1 = Spectrum1.Trace1.magnitude var t2 = Spectrum1.Trace2.magnitude var c = t1.length var d = [] for(var i = 0; i < c; i++){ d.push(t2[i]-t1[i]) } plot1.Y1.data = d
  2. 2 points
    attila

    Math on FFT traces

    Hi @lab!fyi 1. I think for your experiment you should use the Network Analyzer interface of the WaveForms application. Connect the Scope channel 1 to your filter input and channel 2 to the output. By default, the analyzer plots the magnitude and phase of channel 2 relative to 1. This will give the characteristics of your filter. In the NA under Wavegen gear menu select channel external (let you use external or custom wavegen control) and frequency extended (to let you use up to 50MHz). The Scope Math channel is performed on the time domain data not on the FFT. 2. The persistence view will be update with the next software version to handle curve interpolation option as well the min/max sampling.
  3. 2 points
    jpeyron

    Basys 3 XADC

    Hi @Rohit kumar jain, To add to @BogdanVanca's post , here is an XADC demo for the Basys 3 that uses 4 analog inputs. Here is the GitHub releases for the XADC demo. thank you, Jon
  4. 1 point
    Hi @luis.maldonado, I have sent the update in a PM. cheers, Jon
  5. 1 point
    JColvin

    VHDL BASYS3 internal clock problems.

    Dan beat me to the punch, but while I can't verify if the original poster is interested in this discussion, but the Technical Based Off-Topic Discussions subForum would be a better location for this particular discussion.
  6. 1 point
    Tickstart

    VHDL BASYS3 internal clock problems.

    I'm afraid they are correct But no one really knows how the Vivado simulator works, sometimes it does, sometimes it doesn't. As far as I know, there isn't any simulator-simulator to test the simulator and figuring out why it won't simulate properly. I just debug my VHDL code like I debug C, just stare at it long enough. But I know that doesn't cut it.
  7. 1 point
    attila

    Math on FFT traces

    Hi @lab!fyi In the Network Analyzer extended option lets you use Wavegen channels at up to 20MHz and with external up to 50MHz. In the Spectrum Analyzer you can select frequency range up to 10MHz but with auto option lets you set Stop frequency up to 50MHz. Selecting the dB unit will let you specify custom reference, for dBm I think it should be 0.316V
  8. 1 point
    Szia András, 1. The Spectrum Analyzer captures a buffer worth of data before processing it. For 200Hz it needs 400Hz capture of 8192 samples which takes 20 seconds. Reducing the number of samples to 1024 it will take 2.5 seconds. For slow progressive analysis you could use the FFT view in Scope with Scan Shift capture. 2. You can find the transparency option under WaveForms/Settings/Options. Also choosing light analog color might help in transparency. 3. You could do with a script like this eeg.dwf3work const neeg = 4 // sections const ceeg = 100 // history var rghistory = new Array(neeg); // history array for (var i = 0; i < neeg; i++) { // initialize array rghistory[i] = new Array(100); for(var j = 0; j < ceeg; j++) { rghistory[i][j] = 0 } } { // configure plot plot1.X.Units.text = "" plot1.X.Offset.value = -ceeg/2 plot1.X.Range.value = ceeg plot1.Y1.AutoScale.checked = false plot1.Y2.AutoScale.checked = false plot1.Y3.AutoScale.checked = false plot1.Y4.AutoScale.checked = false const vmax = 20 plot1.Y1.Offset.value = -vmax/2 plot1.Y2.Offset.value = -vmax/2 plot1.Y3.Offset.value = -vmax/2 plot1.Y4.Offset.value = -vmax/2 plot1.Y1.Range.value = vmax plot1.Y2.Range.value = vmax plot1.Y3.Range.value = vmax plot1.Y4.Range.value = vmax } Scope1.run() while(wait(0.5)){ // 0.5 second update rate var rgmag = Scope1.Channel1.fftmagnitude var rghz = Scope1.Channel1.fftfrequency var c = rgmag.length var rgeeg = [0,0,0,0] for(var i = 0; i < c; i++){ // calculate section power var hz = rghz[i] if(hz<4) rgeeg[0] += rgmag[i] else if(hz<7.5) rgeeg[1] += rgmag[i] else if(hz<12) rgeeg[2] += rgmag[i] else if(hz<30) rgeeg[3] += rgmag[i] } for(var i = 0; i < neeg; i++){ // shift history arrays rghistory[i].shift() rghistory[i].push(rgeeg[i]) } print(rgeeg[0],rgeeg[1],rgeeg[2],rgeeg[3]) plot1.Y1.data = rghistory[0] // yellow plot1.Y2.data = rghistory[1] // blue plot1.Y3.data = rghistory[2] // red plot1.Y4.data = rghistory[3] // green }
  9. 1 point
    D@n

    working of pipelined FFT architecture

    @farhanazneen, If you want to know "how" an FFT works, don't look at Xilinx's implementation. That's a trade secret and you aren't likely to get that answer. On the other hand, you might find the answers you are looking for by examining a similar open source FFT implementation, such as this one. It's actually a full FFT core generator, so if you don't like the example 2k FFT found in the rtl/ directory, feel free to rebuild it for the size you want. An FFT consists of a series of "stages" that implement "butterflies". Then this implementation, based around a decimation in frequency approach, those stages operate on samples k and k+N/2, then on k and k+N/4, then on k and k+N/8, etc. You can see the code for each stage here, or even the top-level FFT that connects the FFT stages together here. The last two stages are special, but only because they can be implemented without any shifts or adds. Now, to your question: Since each stage operates on two elements at a time, and since these elements are separated by 2^(stage_number-1) elements, each of these stages needs a memory equivalent to 2^(stage number -1). Values can be initially stored into this memory. Once the memory is full, the next 2^(stage_number-1) elements plus the memory saved value can go directly into the butterfly. Hence, the butterfly starts operating at this point. There's also a memory storage requirement at the output of the butterfly, since only the first of the two values can move forward immediately: the second value has to wait until all the first values have past, etc. If you were to count this, there's be 1 register for the 2-pt FFT stage, 2 registers for the 4pt stage, 4 registers for the 8pt stage, 8 for the 16pt stage, and pretty soon Vivado will start using block rams: 16 for the 32-pt stage, 32 for the 64pt stage, etc. If you want your FFT output in natural order, you'll also need to do a bit reversal stage. The way I do this, there's one buffer filling and one emptying at every time step, hence you have 2N sample buffers for N points. Now let's back up and talk about delay. For an N-point FFT, there's a delay of N/2 clocks til fill the butterfly for the first stage, plus about 3-4 clocks for the butterfly (I'm not counting--could be a bit more). The same would be true for the next stage, save that it would now be N/4 + (about) 4 clocks, then N/8 + 4 clocks, etc. The delay through the bit reversal is likely to be a full N clocks. All that said, I'd trust the FFT output to tell you when the first block was complete over these calculations above. I know that for my own FFT, these delays can vary significantly from one set of FFT parameters, size, bit width, etc, to the next. Dan
  10. 1 point
    Hi @jma_1 See the help of the application: The Protocol interface uses the device Digital Pattern Generator and Logic Analyzer resources to transfer data using UART, SPI, and I2C protocols. When the Debug option is enabled, the Logic Analyzer can be used to investigate the signals. In this case, the Protocol instrument will not receive data, it will only send data.
  11. 1 point
    JColvin

    Connect power to NetFPGA-SUME card

    Yes, that same connector will be electrically compatible with the SUME as well, so whatever is used for that will also work on the SUME without issue. Otherwise, this power supply (found personally by me, not formally recommended by Digilent) has the EPS 8-pin connector that you need. Thanks, JColvin
  12. 1 point
    attila

    About AD2 Scope function

    Hi @Paul Chang It looks like you are using an old software version. You find the newer one at: https://reference.digilentinc.com/waveforms3 or https://analogdiscovery.com/ You can find the latest beta versions at: https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ The Noise band plot can be disable under each channel gear dropdown. The capture of such Noise data for all channels can be disabled or under time options or in older software version under time gear dropdown . The Noise band is useful to highlight glitches or higher frequency components than the current sampling rate. Than might be hidden by the sampling process.
  13. 1 point
    BogdanVanca

    BASYS3 board - XADC ports

    Hello @donwazonesko, Please check this document : https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf for more info. "- what's the sampling rate (i think its 1 Mpsp)?" The sampling rate is indeed 1 MSPS. "- what's the delay between ports ?" Can you please be more specific ?. Are you referring to the delay between conversions ? If yes, 26 ADCCLK cycles are required to acquire an analog signal and perform a conversion. This implies a maximum ADCCLK frequency of 26 MHz. "- is it compatible with microphone output (diff or single ended)?" Probably yes. But you have to make sure that the microphone output doesn't exceeds 500 mV for bipolar mode and 1 V for unipolar mode . For more info, please check this document : https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf. Best Regards, Bogdan Vanca
  14. 1 point
    BogdanVanca

    Basys 3 XADC

    Hello @Rohit kumar jain, Yes it is possible. The on board xadc has 16 different aux analog inputs. Best Regards, Bogdan Vanca
  15. 1 point
    BogdanVanca

    Looking for the right board

    Hello @HelplessGuy, Zybo-Z7 will satisfy your needs. It has an Ethernet connector and also an On-chip analog-to-digital converter (XADC). When you say "160kHz" you probably refer to the sample frequency. The on board analog to digital converter has an sampling rate of 1MSPS and 16 different aux channels. You could also look on Arty Z7-10/20 version (https://store.digilentinc.com/arty-z7-apsoc-zynq-7000-development-board-for-makers-and-hobbyists/), or even ZedBoard(https://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-development-board/). Or if you want to work with an FPGA based board, you can go with Arty-A7(https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/) or Nexys4 (https://store.digilentinc.com/nexys-4-artix-7-fpga-trainer-board-limited-time-see-nexys4-ddr/). I also depends on how much money do you want to spend. Best Regards, Bogdan Vanca
  16. 1 point
    xc6lx45

    fft spectrum analyzer on SOC

    and I was curious what brings you to that question. It's so difficult to come up with a meaningful homework problem (this one would be good), I don't want to carelessly ruin it 🙂
  17. 1 point
    JColvin

    Hardware manager recognize problem

    Hello @ATIF JAVED, I believe this post describes the same issue you are encountering: https://forum.digilentinc.com/topic/13275-xup-usb-jtag-programmer/#comment-40008. It's for a slightly different cable, but I think it's the Windows 10 and drivers issue. Let me know how this works. Thanks, JColvin
  18. 1 point
    JColvin

    Pmod AD5

    Hi @Akshay Bhat, I would use the formula shown on page 39 of the AD7193 datasheet. I'm not familiar with the LMT84DCKT, so I don't know if it is the same or not. Thanks, JColvin
  19. 1 point
    BogdanVanca

    DRAM or ON-CHIP-MEMORY

    Hello @Ram, In SDK, there is an linker script file that specifies where different sections of an executable are placed in memory. Please check "lscript.ld". All of those sections are user-configurable. For all of our projects we use the "ps7_ddr_0" memory section. Best Regards, Bogdan Vanca
  20. 1 point
    Hi @Etienne Drouin, Here is the Arty-S7 reference manual. In Section 4 Quad-SPI Flash it says that "FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number S25FL128S)". Here is an older tutorial that should help you program the flash on the Arty-S7 from vivado's hardware manager. Here is an older tutorial that should help you program the flash from sdk if you have a microblaze project. thank you, Jon
  21. 1 point
    chuerta

    AD2 sample rate

    Thanks Andrew, reviewing the ADC datasheet I found de Control Clock (tq) divider bits, are those bits the one controlling the sample rate? If this is the case, is not clear to me why the max sampling rate is 6.25Mhz, the main clock is 24Mhz and the relationship between them should be an integer, am I right? Additionally, I am interested in use Labview and have FFT with less than 20Hz resolution to measure Frequencies lower than 1Mhz, is any vi available for this task?
  22. 1 point
    attila

    Analog Discovery 2 vs Raspberry Pi 3

    Hi @Phil_D The received data set may contain inserted or altered by dummy zero bytes so the data can be shifted randomly... To detect such it would require adding a custom CRC wrapper above the communication, firmware and software architectural changes...
  23. 1 point
    Hi @emfries, The JP1 is the mode jumper and should be shorted. Here is a working project I made that uses a compressed bitstream using the offset of 0x00300000. I used the beginning of the Arty - Getting Started with Microblaze Servers tutorial to set up the arty. I used step 1 to step 4.3 with a couple of changes like instead of a 25 mhz 3rd output clock it is a 50 mhz clock in the clock wizard on step 3.3. On step 4.2 do not select interrupt controller. Once you have completed step 4.3 drag the usb uart and the quad spi flash from the board tab to the block design. Connect the output clock 3 to the ext_spi_clk of the quad spi flash IP and then run connection automation. Next I created a wrapper. I then went to the How To Store Your SDK Project in SPI Flash tutorial. On step .5 I also clicked on configuration, set Configuration Rate (Mhz) to “33” and under Configuration Modes, select Master SPI x4. I then follow the How To Store Your SDK Project in SPI Flash with only one change i set the FLASH_IMAGE_BASEADDR to 0x00300000. I was able to use the PROG button to start the hello world program stored in flash as shown in the attached screen shot. cheers, Jon
  24. 1 point
    mouse123

    sampling filtering

    hi I got my AD2 and started to explore. some silly questions: 1. the sampling rate seems automatically set according to time division selected. why the sampling rate is changed based on the time scale? can it be set by customer at a fixed rate? 2. is there DSP filtering function available, such that I could added a new channel that was low-passed filtered channel of 1+ scope channel? 3. Can the scope graph display real time elapses of signals instead of fixed 8000 samples at fixed time window? how to export to the recorded traces?
  25. 1 point
    hamster

    Welcome!

    My name is Mike, and I've developed a bit of an obsession with FPGAs. You might be able to find some project ideas or inspiration on my WIki at http://hamsterworks.co.nz/mediawiki/index.php/FPGA_Projects I'm always happy to talk FPGAs, so feel free to drop me an email sometime