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  1. 2 points
    zygot

    Beginner DSP Projects

    Yes Dan he certainly would agree with your advice. Test, verify, test, verify. Let it be your mantra. Test and verify the main result that you are looking for. Test and verify all of the component parts ( particularly in logic ) in case you want to reuse any modules or components. Test and verify corner cases. Test and verify consistency of results between all of the implementations. For the logic implementation there will be more subtle and complicated aspects to consider and test for. Assume nothing. If all of this doesn't sound like fun ( I'm taking the long view by using that word) ... perhaps consider a different way to spend your free time. Oh, and I forgot to mention the most important part. Don't do it for self-defense. You can learn a lot more during the test and verification stages... you know, the part where most people have gone on to other things assuming that everything works, than you can learn during the basic design processes. Testing and verification generally requires another level of awareness to issues not obvious in the original conceptual stages. That's my experience.
  2. 2 points
    zygot

    Zybo serial port in Ubuntu

    @jacobfeder, Here's some handy tips for using serial ports in Linux Open a terminal window in Linux Find out what USB devices have been enumerated: Enter the command 'lsusb' to see a list of enumerated devices. You can get more information by adding -v or -vv command line arguments Find out what Serial port devices are available: Enter the command 'dmesg | grep tty' to see what serial ports are available and what name to use. If you are not sure what device is what try using the dmesg command with the USB UART disconnected and again with it connected. If you run Putty and hit the open button you will either get the screen that you mention if Putty successfully connects to an available device with the specifications you assigned to the current Putty session. Otherwise you get an error message and Putty exits. Now that you have a connection all that's left is to have a conversation between the computer and whatever is connected on the other end,. If what's connected on the other end is listening, try typing into the Putty terminal window and hit enter. If the connected device is able to transmit you should get some sort of reply back. Of course if Putty is connected to the wrong serial port that's a problem. Here is an edited example session telling me to use Putty with ttyUSB0: lsusb Bus 005 Device 003: ID 067b:2303 Prolific Technology, Inc. PL2303 Serial Port dmesg | grep tty console [tty0] enabled serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A 00:0b: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A usb 5-2.1: pl2303 converter now attached to ttyUSB0 happy communicating!
  3. 1 point
    JColvin

    Beaglebone connectivity using Linx

    Hi @adithya76, How are connected to your BBB? Via USB cable or are you connected to the BBB over ethernet? I've also asked another engineer more familiar with LINX to see if they have some thoughts on this as well. Thanks, JColvin
  4. 1 point
    Hi @irisphys, Are you holding the CS low? I would suggest to contact Avnet support here. Avnet has experience with the Microzed and the MIO Pmod port. thank you, Jon
  5. 1 point
    jpeyron

    Max chipkit and Max32

    Hi @Usmanrashid, In section 4 Reloading the MPIDE bootloader of the reference manual here it describes how to re-install the arduino/mpide bootloader hex file. thank you, Jon
  6. 1 point
    Hi @Dennis Jow, Additionally the Adept download includes a pdf titled "Adept Application User's Manual". Thanks, JColvin
  7. 1 point
    jpeyron

    Reprogram the PIC24 on Nexys 3 board

    Hi @Naipsys, The firmware for the PIC32 is not publicly shared. You will need to email support dot digilent at ni dot com to discuss getting the firmware for the PIC24 further. thank you, Jon
  8. 1 point
    Keon

    ERC: 0x3EC

    Changing my USB cable fixed the problem.
  9. 1 point
    Fa-b

    How can I use Trigger output pin?

    Hi WaRc3L, I have checked this today using an external Scope. I can confirm that the Trigger Output pin seems to not be implemented (though I did not have much time to test it, so I might be wrong). I didn't also find any hint in the protocol that there was a setting for activating the pin. Even tried it with a pullup in case it was an active low output, but with no sucess. I did not have enough time to check if the Trigger Input (ext. Trigger) works. But I guess it wont, since there is no such trigger source available from neither Waveforms Live nor the protocol. Waveforms Live had an error whenever I tried to use LA as the instrument with any of the GPIOs as trigger source. Does that at least work for you? If so, maybe you can use the red LED of the Openscope as the Trigger Output. I don't know how accurate its timing is though. Regards Fabian
  10. 1 point
    jpeyron

    issue with design.txt file in xadc

    Hi @farhanazneen, Please attach a screen shot of your block design. In your test bench are you giving the input initial values? Please attach your test bench. It looks like my previous post did not link the forum thread here that has the working zedboard xadc project done in Vivado 2016.4? If you do not have Vivado 2016.4 please download it (you can have multiple version of vivado installed) and see if you are able to run the zedboard_xadc project. thank you, Jon
  11. 1 point
    Hi @aiswarya, Based on your previous post your project is trying to use the AXI IIC IP Core with a zynq processor. Is that still the case? What device are you trying to communicate with? What FPGA dev board are you using? Have you looked at our Vivado library here as a reference? The PmodAD2, PmodCMPS2, PmodCOLOR, PmodHYGRO and the PmodTMP3 all have IP Core that use the AXI IIC IP Core. Also here is the Creating a Custom IP core using the IP Integrator tutorial that will be helpful for creating your own custom IP Core. thank you, Jon
  12. 1 point
    jpeyron

    issue with design.txt file in xadc

    Hi @farhanazneen, Looking at your previous posts it appears that you are using a Zedboard for this project. Here is a forum thread the discusses using the ps with the xadc Header that has a completed project for the Zedboard. Here is a tutorial with the ps and xadc Header for the zedboard. Looking at your screen shots the first thing i see is you are selecting vaux0 through vaux3. If you are using the XADC header then these are the wrong channels. If you look at the zedboard reference manual here on page 26 it shows that vaux8 and vaux0 are the only channels available on the xadc header. The rest of the channels are connected to the FMC. You will need a FMC mezzanine to access the other channels. thank you, Jon
  13. 1 point
    JColvin

    Network shield for MAX32 is revision C

    Hi @Marty, I'm taking a look into the older revisions for the network shield and let you know what I find. I imagine most of the boards will work as is if they were a product revision, but I'll double check. Thanks, JColvin
  14. 1 point
    attila

    Digital Discovery SPI interface

    Hi @Sung The WaveForms application can be used in demo mode to explore the features. In demo mode the protocol signals are not generated properly but you can see the options a real device would provide. 1. You can use the Logic Analyzer to capture and decode communication. This is mostly useful for debugging protocol like for timing, glitches... 2. You can use the Protocol interface to send or to capture data and save in text file. You can also use JS code to automate communication in Custom tab or Script interface. 3. You can use the WaveForms SDK to create custom application/script.
  15. 1 point
    A quick update - please ignore the "Segmentation fault". That was fixed, but the main problem still exists. Vic
  16. 1 point
    D@n

    xadc data reception on high frequency

    @train04, All of the charts you've shown above could easily be created under the appropriate circumstances. Not knowing the conditions of your test, or what sort of response you were expecting, it'd be hard for me to comment. Can you tell me what you were expecting to see and how/why the result you do see looks different from what you were expecting? Dan
  17. 1 point
    Hi @ The full part number for the microzed you have is XC7Z010-1CLG400C. After looking at the schematic for the mircozed you might need to make adjustment with the mio pins. I have not worked with the microzed board. With that in mind I would suggest to reach out to Avnet support about the configuration of the zynq processor. The ext_spi_clk on the PmodOLEDrgb should be 50 MHz. I am able to create a wrapper but I havent been able to generate a bitstream for the microzed with the PmodOLEDrgb. I have attached what i believe the xdc should be based on the schematic and the wrapper. thank you, Jon microzed.xdc
  18. 1 point
    In the block diagram view use the XADC wizard it gives an option to create a design.txt which you can use or modify
  19. 1 point
    D@n

    Beginner DSP Projects

    @ho0pla, You should thank @zygot for such sensible advice: build it in Matlab or Octave, get it working, then port to hardware. Let me add another step in the middle, though, that I'm sure @zygot would agree with: Octave, then simulation, then hardware. After that, the sky's the limit! Well, you might want to study a particular application of interest as well. DSP is such a varied field, and so many things from so many fields are called DSP that ... well, it's hard for me to pontificate from here. Still, if you are interested in some examples, feel free to read some of ZipCPU's DSP articles on line. (The ZipCPU is the name of a CPU/processor I've built, and now blog about under the name ZipCPU.) They tend to hit on many topics surrounding DSP theory and implementation. Indeed, I recently posted a rather cool simulation demo of a spectrogram to github. There's a nice screenshot avaialble there too in order to give you an idea of how far you might get with simulation. Perhaps these ideas might stir up in your mind a project you'd like to try? Dan
  20. 1 point
    zygot

    Beginner DSP Projects

    I'll offer a somewhat alternate view from the one that @xc6lx45has provided. In commercial practice there is a lot of DSP work done on FPGA devices. I would agree with the sentiment that I am inferring from xc6lx45's comments above that doing DSP in FPGA is really hard. It is not for beginners as you have to understand and account for all of the minutia without high level canned code ( libraries ) that are available in say OCTAVE or C libraries. I would respectfully disagree with most of the other commentary above. DSP on and FPGA is fun once you have a certain amount of expertise. Riding a unicycle is fun for a few individuals but certainly not something that I would enjoy ( I don't enjoy bleeding and bruising...). In my experience the typical approach to DSP in an FPGA is to test an algorithm in MATLAB or OCTAVE and all of the high level keywords that are available. Then devise a simpler easy to understand algorithm in OCTAVE just using basic math and if..then..else type statements that is good enough to accomplish the task at hand. You'll have to understand the basic math and difference between floats and fixed point ( and binary fixed point for that matter ). That simpler OCTAVE coding will be your map to implementing a DSP algorithm using the resources available in an FPGA. If you start off with something too complicated you'll get discouraged, quit and feel bad about yourself. That doesn't mean that you can't do some interesting things. I suggest that you start with a simple filtering ( no feedback ). Try to describe your idea in OCTAVE and then figure out how to do it in digital logic. OCTAVE can help design the coefficients. After you have working HDL simulations compare the HDL simulation results to the OCTAVE results. You don't have to do fixed point representation in OCTAVE to see if you are close to being correct. I spent many years doing DSP assembly coding for actual DSP processors before trying to implement DSP in logic. I would strongly encourage those interested in DSP to get some expertise in something like MATLAB, then C coding for a DSP processor using canned libraries ( look at Texas Instruments for resources ), and lastly trying to to DSP in logic. Of course, if you haven't mastered FPGA logic development this could be tough slogging. I certainly helps to have some basic and advanced experience instrumenting and debugging your logic on a working FPGA platform before trying to implement complex designs. I've mentioned this in another thread but understanding DSP theory using a MATLAB or C libraries that hide all of the hard stuff is one level of "understanding". Being able to implement an equivalent DSP algorithm using basic math and flow control such as the if..then..else commands is quite another level of "understanding". If you have reached the proper level of "understanding" then you might well find quite a bit of enjoyment and fun in doing DSP in an FPGA.
  21. 1 point
    Hi @roozeboos, I have sent you a pm about this. thank you, Jon
  22. 1 point
    Hi @irisphys, We do not have documentation specifically for Avnet's Microzed dev board. Since we did not make a board file for the Microzed you should follow most but not all of the ZYNQ platform part of the The Getting Started with Digilent Pmod IPs tutorial. The PmodOLEDrgb IP Core should work with the microzed board. Once you have added the ip core you will right click on the pmod out and select make external. After creating a wrapper you will need to use an xdc file to constrain the pins named in the wrapper. What version of Vivado are you using? cheers, Jon
  23. 1 point
    Nope, 32b is not supported by the Xilinx tools. But you are right what matters is not the architecture of the host but rather the guest, I messed that up 😕 You'll need this one.
  24. 1 point
    Ubuntu 16.04.3 LTS can be downloaded here For the exact variant you should use we need to know the architecture of your CPU (intel, arm, amd, 32b or 64b). You can check this in Win 10 system overview. To setup Ubuntu in VMWare, download the iso file from the link above. Then create a new VM, mount the iso in your VM, boot it then install it. I am not going into the details for these steps here.
  25. 1 point
    attila

    WaveForms beta download

    3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery