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  1. 3 likes
    @D@n , Here's a secret; I'm whispering because this is just between you and me: At places where they do a lot of quality FPGA development work no one ever brings up a GUI for anything. All of the toolchain invocation is done using Perl and TCL/TKL. Shhhh. Don't tell anyone....
  2. 2 likes
    As an easter egg that I just learned, such a thing is already planned for the next release
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    But in this particular case, just props to @attila since as far as I know, WaveForms 2015 == attila.
  4. 2 likes
    Dear All, The new software version can be downloaded from the following page: https://reference.digilentinc.com/waveforms3 The changelog is available here: https://reference.digilentinc.com/reference/software/waveforms/waveforms-3/change-logs/3-6-8 See this blog for more details: https://blog.digilentinc.com/software-update-waveforms-3-6-8/ Please let us know if you have any observation. Thank you, Attila
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    @shis, If you only need to read the matrix one column at a time, transpose it. Memory works well when you attempt to read adjacent memory areas or in sequence. Which memory you choose also depends upon your timing needs. Most of the flash devices on the boards Digilent sells can read 8'bits every 20-40ns. However, they may take up to 240ns to get that first byte through. (Some of this depends on whether you are running the flash serial clock with a 50MHz or a 100MHz clock) Open source wishbone controllers  are available, should you want one. SDRAM can be much faster. My Arty can read 128-bits every 12ns or so, although the first request may take about 300ns to complete--if I recall correctly, it's been some time since I measured that latency. I'm now working with a Nexys Video that can read 128-bits every 10ns, but I have no idea what the latency is through the controller. Should you choose to wish to use SDRAM, you'll probably want to initialize the SDRAM from the flash anyway. If you'll notice, I just gave two numbers for the speeds of each of those parts. The first is the speed you should be able to achieve if you read your values in sequence. The second, if you read your values in random order (i.e. column order) from your device. Just a thought or two, Dan
  6. 2 likes
    For all of those who have never dealt with a contact bounce, I just finished measuring the response of pushing a whole slew of buttons: those on the Arty, the CMod-S6, the PMod-Keypad, and even on an icoBoard. It was a fun project. Here's an image showing one of the responses I came across, I'm hoping to post the others soon, but I thought this was just too fun not to share, Dan
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    Hi @JessPlazas, Its in the same spot. I have attached a screen shot below. cheers, Jon
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    counter should be declared as a signal and std_logic_vector. Signals are the standard type for "variables" inside of a VHDL module. Likely you will need to define the PWM# signals as std_logic instead of bit, VHDL has very strict typing, and things just work more smoothly if you can make the types of signals on the left and right side of an assignment match. I don't believe that the constant keyword is required for PWM_COUNTER_MAX, generics are already evaluated when the design is synthesized, rather than when it is run. I formatted my previous response in the way I did for a reason, one of the best ways to quickly get something to work is to learn from others, in this case, I'd recommend reading the template code that surrounds your code, if you can read and understand what is going on in that, you will find yourself well prepared to write your own.
  10. 1 like
    Hi @gutielo, I reached out to one of our design engineers. What i found out is that the pin is an output and intend to power a peripheral board. The XADC itself is powered via the VCCADC on the Zynq, which is powered by an onboard regulator. We followed Xilinx’s spec for the header so it’s more or less the same as the XADC header on any of Xilinx’s series 7 evaluation boards. The design engineer believes the purpose of this particular pinout was to make it compatible with the following board: https://www.xilinx.com/products/boards-and-kits/hw-ams101-g.html. Sorry about the delay. cheers, Jon
  11. 1 like
    Hi @HansV Thank you for the you observation. I wanted to modify the protocol trigger for the current version similar to this but had no time for it, I hope to make it for the next version.
  12. 1 like
    An example of what I would do for this would be the two attached verilog source files. The attached image shows how to make the parameters visible in the customization GUI. In the IP Packager's Customization Parameters tab, double click on any parameter you want to be able to change from your block design and check the Visible in Customization GUI box. The IP that these files would instantiate sets things up so that the following should always evaluate to true. (the IP just copies slv_reg0 onto slv_reg1's address). Xil_Out32(BASEADDR, value); newvalue = Xil_In32(BASEADDR+4); return (value == newvalue); The led and sw ports can be resized by customizing the IP in your block design. If you make those ports external in the block design and then properly constrain them, then Xil_Out32(BASEADDR+8, value); will set your boards leds, while Xil_In32(BASEADDR+12); will return the state of your boards switches. myip_v1_0.v myip_v1_0_S00_AXI.v
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    I apologize if a lot of this is redundant with the tutorial. First, create a new axi4 peripheral, this you probably know. You can edit the number of registers and size of them, in case you need more than 4x32 bits in your interface. I believe that adding more registers or making them wider does not affect your bandwidth over AXI, so this is just a convenience. MAKE SURE you select edit IP before finishing. More to come...
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    Hello, some people might already know The PoC-Library. It's a collection of over 120 free and open source IP cores, that are platform independent. The IP core work on Altera, Intel, Lattice and Xilinx FPGAs of any device family. The core are describe in platform independent, generic VHDL code. If vendor primitives are required or better implementations can be achieved, a configuration mechanism will select a suitable implementation. PoC has gotten a first simple set of new I/O controllers abstracting Digilent's Pmods. These are located here: https://github.com/VLSI-EDA/PoC/tree/master/src/io/pmod I might wonder if users in this forum or Digilent itself would be interested to add more Pmod abstraction layers for modules like the temperature sensor, OLED displays, ... I'm going to release a set of basic I/O controllers for I²C, OW and SPI soon. These can then be used as a communication base for higher level protocol implementations to the Pmods. If one is interested or has questions, please let me know. You can contact me e.g. via Gitter: https://gitter.im/Paebbels Kind regards Patrick Lehmann
  15. 1 like
    @maximb This type of issue is typical of a logic-gated clock. Usually you can get around it by replacing slowclk with an enable strobe and clocking all of your processes on the main fast clock signal. Pseudocode of what I mean follows: generate_strobe: process (clk) begin if rising_edge(clk) then if <statement> then --however you would normally toggle slowclk froom low to high slowclk_strb <= 1; else slowclk_strb <= 0; end if; end if; end process; using_the_strobe: process (clk) begin if rising_edge(clk) then if slowclk_strb = 1 then <do stuff>; end if; end if; end process; Hope this helps, Arthur
  16. 1 like
    Hi @StudentAmsterdam, I got Lab 3 to work on a Zedboard. One of my co-workers got similar sdk code to work for the zybo in the first thread i link above. cheers, Jon zybo_xadc_test.c
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    Hi All, So sorry for the late reply. I just got back from a long vacation. I have good news. At first I was able to load a bit file using only this flash drives: 1. https://www.amazon.com/Kingston-DataTraveler-101-G2-DT101G2/dp/B008C4JIUE 2. https://www.amazon.com/SanDisk-Cruzer-Blade-SDCZ50-008G-SDCZ50/dp/B01276IYYS/ref=sr_1_3?s=electronics&ie=UTF8&qid=1502175071&sr=1-3&keywords=SDCZ50-008G These are the ones that does not work: 1. 8 gig version of this, https://www.amazon.com/dp/B00UW3JRIG/ref=olp_product_details?_encoding=UTF8&me= 2. https://www.amazon.com/16GB-USB-3-0-DATATRAVELER-G4/dp/B01MDODFQ0/ref=sr_1_3?ie=UTF8&qid=1502175335&sr=8-3&keywords=datatraveler+g4+16gb I don't have have then other one right now so I cannot give the part number or link of that. I then tried loading the files given by @elodg and amazingly the first drive that does not work has now work! Soon if I get hold of other flash drives I will test it. But I am already happy now so I think this issue is now closed. Thank you so much for the support. Kudos to all of you from Digilent and everyone who respond to this post. Regards, Nico C.
  18. 1 like
    @electronicsdevices, Gosh, look what your simulation just revealed ... (I reviewed MMultAB.v only, not MMultAB_tb.v) Your design (MMultAB.v) takes no time at all, since none of the transitions take place on the positive edge of any clock. The synthesizer did all your logic for you, and only programmed the result into the resulting registers. No operations actually took place. A simple set of 4-input LUTs (A, B, C, and MultAB) can be used to select among four apriori known answers. It's a memory lookup to the answer, rather than any computations taking place. So, let me ask, are you sure your design actually does what you want it to? And, since you hadn't simulated your design, you really only had a false sense of what your design was doing up until now. So, yeah, I am a big fan of simulation. This is a wonderful example of why. Were I to redo this, I'd rebuild the module so that the FPGA inputs could be set externally. That would keep the synthesizer from optimizing away your logic. It would also fail timing, forcing you to put the clocks back in that you need. As for setting it externally, may I recommend using a debugging bus? I like to use that to read/write an FPGA's data from software. I consider the debugging bus interface to be more reliable than buttons and switches, but you may need to read the next several blog posts to know why. (Or read the wikipedia paragraph on contact bouncing, and take a look at what buttons can do that you aren't expecting here) Dan
  19. 1 like
    @shis Yes, it is possible, but it can be more challenging to work with. Some of our low cost boards have DDR memory which can be accessed from the FPGA, if you can get the controller correct, or find one with interfaces that work for you. We also sell some peripherals that could work for you, the Pmod SF3 for example has a fairly involved programming and reading sequence that can be managed through the FPGA (though it's 32MB of memory may not be enough, depending on the bit depth of your matrix entries). You may also want to look into various ways of compressing your matrix, but this could depend on what your data looks like. Hope this helps, Arthur
  20. 1 like
    Solved the problem by creating a new Hardware Platform Specifiation (with the design_1_wrapper.hdf file), a new BSP based on this platform and a new application where I copied the c files. Thanks for your help !
  21. 1 like
    @rob Jon is correct, however, if you really need this functionality without using the ARM, you may want to look into the Pmod USBUART. Thanks, Arthur
  22. 1 like
    Greetings! Not only did I get the Openscope MZ working on ALL of my computers, I managed to get in on my home network and access it from the WaveForms Live app running on my Android tablet! We are cooking with Gas now! Thanks again for all of the assistance. Great Product and works as described. Who could ask for more? T.
  23. 1 like
    @lucileklang Which version of Vivado are you using? This error is typically seen when using a version more recent than the demo was developed for or updated to. The DMA Audio demo was built for Vivado 2016.4. If you are in a 2017 version of Vivado, try upgrading the IPs by clicking Tools / Report / Report IP Status in the top menu bar. From there select Upgrade Selected in the IP report sub-window that pops up at the bottom of the screen. Once you have the bitstream generated, launched SDK, and imported the SDK projects, you will likely need to Regenerate BSP Sources by right clicking on the *_bsp project and selecting that option. If Xilinx didn't update their IP or drivers beyond recognition (which is somewhat rare) this should get the project up and running. Hope this helps, Arthur
  24. 1 like
    @Ahmet, Your problem is that you are attempting to use the rising edge of the incoming information. The only rising edge your logic should depend upon is the rising edge of the clock. Everything should depend upon that rising edge, and no other rising edges. Now, given that advice, how to handle the encoder counts you are looking into? It'll take a couple of steps. Step one is to synchronize your input_bit with your system clock. This (mostly) avoids any metastability issues: always @(posedge S_AXI_ACLK) nearly_synched_input_bit <= input_bit; always @(posedge S_AXI_ACLK) synched_input_bit <= nearly_synched_input_bit; Step two is to detect rising edges in this synch'ed bit: always @(posedge S_AXI_ACLK) last_input <= synched_input_bit; always @(posedge S_AXI_ACLK) if ((synched_input_bit)&&(!last_input)) counter <= counter + 1'b1; Your separate timer can fit into it's own always block (Verilog term, VHDL term would be a process): always @(posedge S_AXI_ACLK) if (timer >= 32'd100_000_000) begin timer_stb <= 1'b1; timer <= 0; end else begin timer <= timer + 1'b1; timer_stb <= 0; end always @(posedge S_AXI_ACLK) if (timer_stb) counted_teeth <= counter; You can even adjust the original counter to clear itself anytime the timer has rolled over. This would replace the always block (VHDL process) defining the counter, since only one always block can ever set the values of any register: always @(posedge S_AXI_ACLK) if (timer_stb) counter <= 0; else if ((!last_input)&&(synched_input_bit)) // Count only positive transitions counter <= counter + 1'b1; Is that closer to what you are trying to do? Dan
  25. 1 like
    Hi @JASBIR SINGH SAINI, On the Zedboard it has C1 marked on the bottem left of the FMC connector. I will get you more specific information for the FMC pins tomorrow. I have reached out to our layout engineer to see what information I will be able to provide you for the circuitry present between FPGA and FMC. The FMC allows for high speed communication between the FPGA board and a mezzanine card. One of the ways that the FMC does this is by allowing you to change the voltage to other voltages besides 3.3V, such as 2.5V for LVDS communication. Here is a link to Xilinx FMC cards. If you are trying to make your own Mezzanine card here is a forum thread that talks about the process involved. cheers, Jon
  26. 1 like
    The microcontroller firmware that reads the bitfile is pretty simple... Maybe try renaming the filename so that it only contains one "."
  27. 1 like
    Hi @ma60510, I have not heard back yet from my co-workers. I am tagging an engineer that might be able to help with your question( @Bianca). cheers, Jon
  28. 1 like
    Hi @electronicsdevices, Here is a list of Vivado 2017 known issues that Xilinx has confirmed. I will spend some more time trying to get your code based on the HDL code from here working in an IP next week. In the mean time here is our Creating a Custom IP core using the IP Integrator tutorial that might be helpful. I did find a thread dealing with matrix multiplication that is for the Zedboard( zynq processor ) that could be helpful as well here. cheers, Jon
  29. 1 like
    To allow software developers to be able to easily get the computational benefits of FPGAs we created Hastlayer: it turns software written for the .NET platform into an equivalent (VHDL) hardware description. It does this while also handling everything in the background to allow the usage of the resulting hardware in the same way as the original software was run - basically where there was a function call there's still a function call but now it really executes on an FPGA, as logic hardware. Here's a demo video of how it works: And why do I post it here? You can also see from the above thumbnail that you can use Hastlayer with Nexys 4 DDR boards! Connecting the board to a host PC via USB as well as Ethernet is supported. You can even use multiple boards simultaneously if you use the latter. Do you own a Nexys 4 DDR? You can get access to Hastlayer, just ask! (And you can get access to it otherwise too!)
  30. 1 like
    Hi @JASBIR SINGH SAINI, On the 1st page of the schematic here is the pin out for the FMC on J1A and J1B. Page 9 of the schematic shows which bank and which pins its connected to on the FPGA. The XDC here also shows the pin assignments for the FMC as well. The reference manual here has some good information about FMC usage. cheers, Jon
  31. 1 like
    @Zoltán Lehóczky, I excited for you that you got things working! Your project looks like a lot of fun. Can I invite you to share your work in the Project Vault once the project completes? Either way, thank you for sharing what finally worked. I'm sure many others will find this answer record useful, Dan
  32. 1 like
    Thanks everyone for the help, but I ended up realizing that I don't necessarily need to collect several seconds of data at once, so UART will work for me.
  33. 1 like
    Hi @juanelete, Unfortunately, It will not work . It would requires the USB controller to support DEPP and the HS3 does not. DEPP is only on the older boards (Nexys 1 – 3, Basys 1, Genesys 1, Atlys) that use the cypress chip. thank you, Jon
  34. 1 like
    Hi @electronicsdevices, I reached out to a co-worker that has been doing some design work in Vivado 2017.1. They said that Vivado 2017.1 has had some bugs with updating hardware changes. It will show in synthesis that it is still using an out of date block design but will not stop the generate bitstream process. You need to manually stop generating the bitstream and update the top file. I have been having issues with you IP being locked even after I change the IP repo to look at \7-25-17_VHDL_2x2_MMult\7-25-17_VHDL_2x2_MMult.srcs\sources_1\bd\design_1\ip\design_1_myip2x2VHDL_0_0 in the project you linked to. Also why are you using both uart 0 and uart 1. I have had issues with the basis hello world when not using just uart 1. I have included screen shots of both of our configuration of the zynq processor below. If you are not needing both uarts then I would suggest to remove uart 0 from the zynq processor and try the hello world again. cheers, Jon
  35. 1 like
    Hi! Is the USB stick formatted with FAT32? I have had no problem with loading a bit file from a USB stick on my Basys3... except when it was formatted with NTFS ;-)
  36. 1 like
    Hi @Sophia_123, Here is a xilinx forum question dealing with issues with debug_net.ltx. I did a compare between the xadc-demo for the zybo made for Vivado 2016.4 here and the code you provide above. You have made changes to the demo. I just ran the unchanged demo with no issue in Vivado 2016.4. I have attached a screen shot of waveforms as well as pictures of the zybo and Analog Discovery 2. Have you been able to run the original demo in VIvado 2016.4? cheers, Jon pictures.zip
  37. 1 like
    HI @Shekhar, Here is a (unverified)tutorial for installing linaro ubunto. Here is a Avnet forum thread talking about installing linaro. Unfortunately, we do not have a current tutorial/demo for this. cheers, Jon
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    Hi @AndyHook1970 2. The recommended maximum voltage for scope inputs of Analog Discovery (1&2) is ±25V (50V differential) and the absolute maximum is ±50V. Exceeding the abs max could damage the device. See: https://reference.digilentinc.com/reference/instrumentation/analog-discovery-2/reference-manual#scope_input_divider_and_gain_selection 1. With 10x probe you could measure up to ±250V, but be cautions when working with high voltages. To see the real value, under channel options configure the applied attenuation:
  40. 1 like
    Many thx @jpeyron, you got it right at first try ! Much respect. This was exactly my problem : copying the lscript.ld from source instead of keeping the one created by SDK. Now everything works perfectly. One again, many thanx. </topic>
  41. 1 like
    Hi @chcollin, I did some searching on our forum and Here is a forum thread the might help with your issue. Could it be the issue with the lscript.ld file? cheers, Jon
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    Progress! The Degilent Agent now finds the Openscope! When I plug the Openscope in it comes up as COM 4. The Agent reports that the device is connected on COM 4. The Firmware has been updated by the agent to version 1.37.0. The Openscope has been calibrated and I can get to the Instrument Panel!!! I did all of this using the de-bug version on the Agent you sent me. Question...going forward, will I have to continue using the de-bug version or can I go back to the standard version? Now, give me the weekend to get over the shock and I will have more to report on Monday. Thanks very much for ALL of the assistance in getting the OpenScope MZ working on my system...You guys are WONDERFUL!!! Have A Great Weekend! Tony
  44. 1 like
    Hi @evan1138, I have reached out to one of my co-workers that will be able to better answer your question.( @AustinStanton). cheers, Jon
  45. 1 like
    Just to be clear jpeyron's suggestion is for educational purposes. Digilent does not recommended or supported modifying the board in this way. Any modification to Digilent hardware will void the warranty and make the board ineligible for RMA. -Kristoff
  46. 1 like
    Hi @mike lee, I have reached out to my co-workers again to see if they have some input for you. Sorry about the delay. cheers, Jon
  47. 1 like
    Hi @rahmat, The Vivado version unfortunately does make a difference. This project was originally made in an older version and updated to Vivado 2016.4 just recently. I just got this project working in Vivado 2017.1 by first going into the folder and editing the version to 2017.1 in the design_1_bd.tcl found here \Zybo-DMA-master\src\bd\design_1\hw_handoff. Once you have loaded the project upgrade the ip cores by going to tools tools->report->report status and upgrade all ip cores. Next you need to have vivado create a wrapper and then generate a bitstream. In SDK i only imported the dma and not the dma_bsp. then i created a new board support package calling it dma_bsp. I verified the terminal portion of the project worked. cheers, Jon
  48. 1 like
    Hi @mwnoble1910 The Protocol interface does not support CAN, nor master CAN. This interface only supports UART, SPI, I2C. You can use the CAN protocol interpreter in Logic Analyzer for communication verification. Protocol interface protocol interpreters in Logic Analyzer interface
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    @RichardV, Thank you. Now I understand more of the context of what you are up to and dealing with. To your question, I'm not sure at this time what it will take to resurrect your board. (I don't have one of those, or I might know ... I'll take any extras you have, though ) Can you tell me what O/S you are running? I have used ISE14.7 successfully many times over, as well as ADEPT. I haven't used IMPACT, but that "should" work as well. All of these should be able to help you on your journey. If you'd like, then go ahead an pick one (or more) and describe the problem you are having. Maybe we can get you a step closer. As for the program "bash", it's a very common and well used Linux program which can even run under Windows using cygwin. Indeed, there's hardly a day that goes by where I don't use it. bash is a command line interpreter that runs programs. Indeed, it is the default command line interpreter under Linux and has been for many years. If you have Linux, chances are you already have bash. If you are using Windows, then ... you might want to check that you downloaded the right adept installer before trying to install cygwin to get bash working. Oh, and one other point: JTAG consists of a series of pins: TCK, TMS, TDI, and TDO. You can find these pins on the configuration page (p6) of your schematic. Many programs I've worked with have wired their own jtag control pins to these wires--they're fairly standard. What I don't know is the voltage standard being used by this device (a voltmeter should tell you), or I might suggest hotwiring your JTAG pins from a different JTAG cable or from a micro (RPi?) to get you going. What I mean is, if the voltages match, any JTAG cable should work. Whether or not the software works ... that'd be another issue. The JTAG standard is not so complex that you can't bit-bang it from GPIO, however ... I'm not sure you signed up for that part of the journey. Dan
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    Hello Jon, Thanks a lot, it is working !!! That is exactly what I needed, but don't worry about the button, I mean the button I already have it in LabView. I just press it in the application and I send the string "Temperature" or "Humidity". So this part I already have done it. Now I just need to work on my sensors, to get the values. Thanks again! Kepler