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  1. 2 likes
    @Riteshkakkar, That's a much longer topic, and well beyond the bounds of this forum. While you may find some folks here who have worked on satellites built for radio communication, the full topic of how to do so is ... typically beyond the ability of any one individual. You should also know that the space environment isn't very friendly to computer chips. Unlike the earth where items can be electrically connected to ground, satellites in space have no solid ground. The space environment is known for accumulating charged particles on satellites until they experience "lightning" from one side of the satellite to the other. It's also known for tiny particles of radioactive energy that can enter into a circuit and toggle bits within an algorithm. Building chips and algorithms to operate successfully in this environment is a study in and of itself. Most chips, FPGAs included, can't handle this environment. It usually takes several years of working with a particular chip design before that design can be "space qualified". In the process, the chip becomes quite out of date. As a result, the electrical technology launched into space tends to lack what is on the earth by several years. Dan
  2. 2 likes
    @Tickstart From my experience you will be asked questions to verify claims you put on your resume. Expect, for example, to be asked HDL syntacsis, implementation of I2C protocol, digital filters, etc. Expect also several people who might be your coworkers will talk with you to get the feel and to test your skills. Everything depends on what is the company doing. Most of US companies don't train employees, they might pay for their classes but that's about all. If you are lucky and the company eager to higher you then they can give you time for training. Once more from my experience companies hire people who can bring something the company doesn't have. Think about it and decide if you have something to offer, otherwise spend time on learning. During the Internet boom one of my friends after reading a few software tutorials managed to be hired as a software developer. Needless to say he didn't last long and his experience was painful since he didn't have developer skills.
  3. 2 likes
    Hi @Tickstart, Since your question was not directly related one of the Digilent FPGA boards, I have moved it to a different section of the Forum to hopefully produce less confusion for other readers. As for my personal perspective, I'm in a bit of an odd spot since I have a degree in chemical engineering rather than EE/CS/CompE, yet here I am helping answer questions on all of those things, meaning I don't have a lot (i.e. any) formal education with HDL design. But like Dan hinted at, I'd like to make sure that the people to be hired can "engineer" their way through a problem, not just hope that a single approach works for everything. Thanks, JColvin
  4. 2 likes
    Apparently the problem was in github. Using git config --global url."https://".insteadOf git:// Seems to fix the issue. I had already modified the problematic .bb files by hand in a previous attempt, but then it didnĀ“t work
  5. 2 likes
    Hi @Arvind Gupta, I believe that header just provides an alternate location to program the board. You'll note the data signals also tie in to the JTAG header J8. Thanks, JColvin
  6. 2 likes
    @BYTEMAN My only major concern with the your current flow is that it is still relatively difficult to gain access to any control signals you might want to use. The Language Template GUI (which you can find in the Project Manager section of the Flow Navigator) has some boilerplate code for an AXI port map with customized parameters that you can add to your custom module. THis doesn't come with the actual AXI control template, but combining the syntax for the portmap with the IP you've created, you should be able to create the same design with only a single added module. AFAIK, added modules don't play as nicely with Connection Automation as actual AXI IP, but it may warrant some investigation. I am currently away from a PC with Vivado installed, so I am unfortunately unable to be more specific on where in the Language Templates you can find this... I'd suggest you try the above, but another method that can be useful to move data between Microblaze and HDL would be to use an AXI Stream interface (which is MUCH simpler than full AXI, there's some info in Xilinx UG761, starting at page 45) in your HDL module that connects to the transmit stream of an AXI4-Stream FIFO Controller (Xilinx PG080). I've been playing around with this a bit recently, and it seems like it works pretty well. This method is more useful for "bursty" data streams (Xilinx uses this for Ethernet communications), rather than "set and forget" registers (like LEDs or something), either on the processor or module side, but it's worth pointing out. Thanks, -Arthur
  7. 2 likes
    Hi guys, I attached a link to a tutorial where chip ADV7611 is configured via I2C and used. I use Xilinx zc702 board and FMC-HDMI Diligent, in the tutorial I explain how to make a motion estimation application. https://arcoresearchgroup.wordpress.com/2018/03/23/realizing-the-lucas-kanade-motion-estimation-algorithm-on-xilinx-zc702-board-for-full-hd-real-time-video-analysis/ I hope it helps.
  8. 2 likes
    Hi @Arvind Gupta, We reached out to one of our design engineers and they responded that the 200 ohm resistors are protection against drive conflicts between an offboard programmer attached to header J8 and the onboard USB controller. The pull-ups are there so that the TMS and SS lines idle in the inactive states. thank you, Jon
  9. 2 likes
    Hello @dgottesm, If you look into rgb2dvi module you will found out, on line 36 this sintax: "kClkPrimitive : string := "PLL"; -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true". So, by default the clock primitive is instantieted as an PLL. For an 27 Mhz it is impossible to respect the minimum value for the PLL VCO frequency. Please check table 38 from the attached document. But, it is possible to do it if you instantiante the clk primitive as an MMCM. In this case the low boundery for the MMCM VCO frequency is 600.00 Mhz. For more details you can check the Table 37 from the same document. So, you need to chose the value "5" for the "kClkRange", because that will outputs you an 675 Mhz frequency for the VCO (20 x 25). And that value respects the MMCM constraints and also the project constraints. Also, don't forget to set the 27 Mhz into the xdc file. A strong recommendation for you is to do all the modification manually into the vhdl's modules. And after that, if everything looks ok and you want go further into the block-design, you can do the same stuff there with the help of the "edit in ip packager" option. Answers for your questions: 1) Thats the minimum value if you instantiate the kClkPrimitive as an PLL. 2) For this question, you can take as an answer the above text. I hope I was clearly enough. I look forward to hearing from you. Best Regards, Bogdan Vanca ds181_Artix_7_Data_Sheet.pdf
  10. 2 likes
    I've just finished reinstalling the WF32 bootloader onto two of my WF32s, and I'm still getting the "Unable to signon, this does not look like a bootloader" error. I downloaded the bootloader from here: https://reference.digilentinc.com/reference/microprocessor/wf32/start I used chipKIT programmer, and programmed using the MPLAB IPE. The IPE claims that the bootloader was verified, so I'm wondering if there's maybe a problem with the bootloader I'm using. Either that or maybe the FTDI is busted? EDIT: I've figured out the problem and of course it was something stupid. While programming the bootloader, I had the VV Select jumper set to something other than UART. That's all. I've reprogrammed the bootloader and now everything works fine. Thanks for the help @james!
  11. 2 likes
    Hi @BYTEMAN, Feel free to put up your dropbox link to your project if you so wish; I know we had communicated about this earlier, but for the interest of letting other users know that they may put dropbox links or google drive or something similar links to their project if the Vivado project gets too big to upload. Alternatively, pictures can be uploaded via the Gallery which doesn't have the same upload restrictions as putting the image directly into the post. Thank you, JColvin
  12. 1 like
    @deppenkaiser, your macro to Access the Memory is wrong, if you would use the right macro, then your Offset calculation would work. @sbobrowicz: I found the error in my Offset calculation, thats could be also the reason for my uio issue! :-) I will tell you the results.
  13. 1 like
    Hi @JColvin The FTDI EEPROM reprogramming is only and only needed when the device is not detected/recognized by the software (Adept, WaveForms, Xilinx SDK...). This happens when the content (Digilent ID, SN) was erased by another application like FTProg. Unneeded reprogramming could lead to missprogramming the device, like programming AD as AD2 and we end up with more hassle to solve...
  14. 1 like
    Hi @Famartinez76, I have moved your question to a more appropriate section of the Forum. As a confirmation, in your main computer (it looks like you are using Windows), does the AD2 show up as a USB Serial Converter in the Windows Device Manager when you connect it? I personally haven't seen this error before, so what I would try to do is reload the data in the EEPROM since it appears that the AD2 is properly getting power from the host computer. You can do this by pressing Alt+F11 on the Device Manger screen of the WaveForms software and then clicking on the "My device is not listed" button that appears at the top to find your device and re-program it. As Attila recommends latter on in this thread, don't do this if your device is already correctly recognized. If this does not resolve the problem though, I will need to pass you off to @attila who is much more familiar with the WaveForms software. Thanks, JColvin
  15. 1 like
    Hello @BYTEMAN, Taking a look at this thread, you may need to re-generate your BSP sources, or potentially delete it and create a new one. I would also make sure that all of the SDK settings (I'm not certain if you have changed any) are on their default settings. Thanks, JColvin
  16. 1 like
    See my question here. git config --global url."https://".insteadOf git:// solved my github issues
  17. 1 like
    Hi @Manny The scope and awg lines are not available on the BNC adapter wire end (marked as NC) but only through the BNC connectors. Also notice the AC/DC jumpers for the scope inputs.
  18. 1 like
    Hi @BYTEMAN, I'm not certain on the differences between the two interrupt controllers, you will likely need to contact Xilinx to see if they have any additional thoughts or concerns on this. As for the SDK debugging behavior, according to this Xilinx site, the GDB mode is depreciated, so you will likely want to instead use the "Launch on Hardware (System Debugger)" option instead for some better results, as this Xilinx forum thread seems to indicate as well. Thanks, JColvin
  19. 1 like
    Hi @BYTEMAN, I verified that on my cmod A7 project i was able to re-program the elf(step 4.1) on the flash without having to re-program the download.bit into flash(step 4.2). I will point this out to out content team as well so they can confirm while updating/fixing the sdk flash tutorial. thank you, Jon
  20. 1 like
    Good day everyone, just a quick update. Everything is going quite slow but fine with this project. Unfortunately I can only spare up to 1-2 hours a day for it, but have learned a lot already. So far I've managed to: Design the DAC pcb and generate all clocks for it (16 bit, 48kHz); Build quite stable square, triangle and sine (1000 sample LUT) generators; Make small internal audio switcher (dependant on hardware switch position); Achieve ~0.2% THD+N on the differential (DRV134) output with 1kHz @ ~4Vpp; Next step is to wait for revisioned and better quality PCBs and reclock it for 24bits. Then it will be the time either for AES/SPDIF output or ADC design. AES output would be nice to have for development as I have a RTW AES audio meter (img attached) collecting dust. I've tried to include MicroBlaze with TCP server stuff so I could control the audio switch and generators, but it just got messy and I still couldn't find a way how could I make MicroBlaze to interact with my RTLs.. This will have to wait until ADC is finished. The saga continues..
  21. 1 like
    Hi @BYTEMAN, My understanding is we are trying to get a 3 MHz clock as shown on page 8 of the Using SPI Flash with 7 Series FPGAs. This accomplished by this (ext_spi_clk frequency) / (frequency ratio parameter) = (clock output frequency) ie. if FR is 16x1 and ext_spi_clk is 50MHz, then the actual spi clock will run at ~3MHz. The pins for the qspi are in the part0_pins.xml file of the Cmod A7 board files which are also reflected in the xdc file here. thank you, Jon
  22. 1 like
    Hello @KatG, I have moved your question to a more appropriate section of the Forum. How are you measuring the signal the WaveForm Generator is creating; are you using the oscilloscope of the AD2 or something different? Could you provide a screenshot of your setup in WaveForms so we can take a look at your settings? Thanks, JColvin
  23. 1 like
    Hi @BYTEMAN, Here is a verified and completed project for the Cmod A7 in vivado 2017.4 that puts a slightly altered hello world template (i put the hello world printf in an infinite while loop) into the flash using sdk. I compressed the bitstream but did not comment out the verbose code. As you mention above you can also skip step 2.3 since there is no DDR. I have also talked with the content team about the discrepancies in the tutorial. It is on their list to fix/update. They also agree that your thought process for how thing work for the qspi is as far as we can see accurate. thank you, Jon
  24. 1 like
    Thanks! I've already added the SSD LCD and the mono 128x32 OLED Pmods, and connected to a PC through the UART interface, using mostly my own source code. I'm planning on playing with the HYGRO and I2S Stereo Audio Output Pmods next. I'm not afraid of programming my own interfaces, but the thing that worries me is that there might be some incompletely documented hardware features/requirements that could hang me up. For instance, I had access to source code for the initialization routine for the OLED Pmod, and I think I could have struggled quite a bit without that. I guess I'll rely on what documentation and samples there are for the various interfaces, and come here for help if I get lost ... 8-)
  25. 1 like
    Hi @BYTEMAN, I am not aware of a way to have those specific microblaze configuration pages to be used after the initial block automation. I would suggest to reach out to xilinx about this question. I believe you are correct about the xdc overriding the board file defaults. thank you, Jon
  26. 1 like
    Hi @BYTEMAN, The Cmod A7 Programming Guide shows how to program the Cmod A7 flash with a project not using microblaze. The How To Store Your SDK Project in SPI Flash tutorial shows how to program the flash using microblaze and the quad spi flash(ext_spi_clk on the ip core needs a 50 MHz clock from the clocking wizard). if you need to use an external peripheral different than the on board memory (like a serial DAC) you would use one of the axi ip cores depending on the type of communication the serial DAC is using i.e. spi, i2c, uart, gpio. You would set the physical FPGA outputs for it through the XDC filles, e.g. using some pio pins. We have many different examples in our vivado library of how we facilitated the different communication along with sdk code to use the different pmods. We abstract a lot of the communication complexity from the hardware side of the design using the pmod bridge and the board files. If you are trying to learn how to use the axi quad spi ip core I would first start by looking at the AXI Quad SPI v3.2 LogiCORE IP Product Guide. thank you, Jon
  27. 1 like
    Hi @JColvin My problem has been solved, thank you for your help!
  28. 1 like
    I looked at the path directory you suggested and yes it was there. Thanks, seems strange that it didn't pick it up there by default as it usually does. Thanks again DC
  29. 1 like
    Hi @deppenkaiser, The Zedboard is a joint venture between Avnet and Digilent. The content is maintained through Zedboard.org. We have responded to your other post regarding the linux base build for the arty-z7-20. thank you, Jon
  30. 1 like
    Hi @humuji, What programmer are you using to connect to the Nexys 2; a JTAG-USB cable or something else? Additionally, where are you seeing the 1 MHz requirement for the JTAG frequency? From Table 123 on page 154 of the Spartan-3E datasheet, the JTAG frequency appears to be allowed to go as high as 30 MHz. Additionally, as @jpeyron mentioned, the programming interface on the Nexys 2 only operates at 1.8 MHz so you will not be able to change the frequency through Adept SDK. Thank you, JColvin
  31. 1 like
    Hello @moe, Unfortunately we don't have any pmods cameras. And that is because the pmod connector is not very suitable for video applications. If you want better performances, along with other resources, I can recommend you the Pcam 5C https://store.digilentinc.com/pcam-5c-5-mp-fixed-focus-color-camera-module/. But for that you need a board with a mipi-connector. Unfortunately arty z7 doesn't have one. Regarding to your question, the AES-PMOD-TDM114-G camera should be compatible with Arty z7. But, making them work together is an entire different story. You can try a different one, please check this link http://zedboard.org/node/819. You also have in there an example project. You can start with that architecture and adapt it for HDMI. Best Regards, Bogdan Vanca
  32. 1 like
    Hi @kastein As Colvin mentioned, in the Logic Analyzer you can add Custom interpreter and write java-script the needed protocol decoder. This should be much easier and hassle free than writing C or other code which would need to be compiled, linked... not talking about the development time required for HDL...
  33. 1 like
    Digikey shows 5 in stock as of today https://www.digikey.com/product-detail/en/digilent,-inc./410-309/1286-1137-ND/4969950?WT.srch=1&gclid=Cj0KCQjwnfLVBRCxARIsAPvl82FkLjauAMyeElJbFN7fn6QDyoqQtsQEwmLhEjwEAu6xJu1WDyK-2wEaAmjkEALw_wcB You might try other distributors as well if you need more. Bill
  34. 1 like
    Ugh, interrupt mappings. This is one of the reasons i like petalinux, because this is handled for you automatically when you import your .hdf. Assuming your mm2s interrupt is connected to In0 of the interrupt concat block and the s2mm interrupt is connected to In1, your channel interrupts look good. I think you can get rid of the interrupts property in the parent DMA node that attempts to map both of them, according to: https://github.com/Digilent/linux-digilent/blob/master/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt. I'm not familiar with the DMA test driver, but in these situations I typically would dig around in the dma and dmatest probe functions to see what is triggering the kernel msg you posted. Then go from there, and maybe add additional printk's to the drivers if you need them. Depending on your kernel version, the Xilinx DMA driver just may not work with the dma test driver. The driver code for the Xilinx DMA has proven to be very volatile over the years, and I remember previous cases of people not being able to get the test driver to work. You might want to try fishing around the xilinx kernel tree and see if anything has been done in regards to this recently.
  35. 1 like
    Hi, one hint: "regular" AXI is fairly complex and achieves its performance by writing bursts. AXI-Lite is in comparison very simple but limited to writing only a single value at a time (which is usually what I want). With a 667 MHz Zynq and the simple example I posted earlier, a single write takes about 0.5 microseconds (a for-next loop counting down from 2M writing a constant to the bus takes one second, give or take some). I wonder how a microblaze (at 100 MHz) will perform. "Polling" is one approach - repeatedly check, whether new data is available. In more complex systems, interrupts would be used, opening up a pretty standard but still XL-size can of worms...
  36. 1 like
    @JColvin, I've been using ISE 14.7 on Centos 6.x for some time and it does support the XC7A100T-1CSG324C device. Honestly, I don't recall if it's the full or free version. I have not however tried targetting that device as I don't have any boards using it.
  37. 1 like
    Hi @deppenkaiser, I don't know when the Arty-Z7-20 demos will be updated to 2017.4, though I do know that is on the list to be completed. I have let our content creators know that there is some customer interest in the types of demos you described. Thank you, JColvin
  38. 1 like
    Check out the AXI GPIO. For simple designs, it may be all you need. On the other hand, putting my own logic on the bus allows some elegant solutions like read-sensitive registers that may simplify the software greatly. Digitop design has its own little team in larger projects (at least on ASIC), don't expect this to just fall into place. Maybe someone else can comment on "standard way", those are just paths I figured out for myself.
  39. 1 like
    ... of course, a ready-made AXI GPIO might be just as good.
  40. 1 like
    Hi @tester11, I am out of the office currently and do not have a pmod Wifi or the arty-z7-10. I did make a wifi scan project in Vivado 2017.4 for the Arty-z7-10 using the Pmod Wifi on Pmod port JA that does not have this error here. I will test it tomorrow. What version of vivado are you using? thank you, Jon
  41. 1 like
    Hi, have you tried a different PC? There are some USB host chipsets which simply don't work reliably.
  42. 1 like
    Hi @AvnetRH, I haven't ever worked with this particular power supply so I do not know if this is true, but there is a possibility that the Xilinx Development boards may refer to development boards that Digilent sells (such as the Arty). After getting some more information from our sales team (since the part is not directly available on our website), it seems you will need to email our sales team, sales at digilentinc dot com, to be able to request that specific power supply. Thank you, JColvin
  43. 1 like
    Hi Gaston, It looks like your CAN receiver doesn't have interrupts enabled. Try adding the following to the RX code, just above the readRegisters function in main() mcp25625_setRegister(MCP_CANINTE, 0x3);//Enable read buffer full interrupts mcp25625_setRegister(MCP_CANINTF, 0);//Clear interrupt flags Hope this helps! -Tommy
  44. 1 like
    I suspect things will make sense if you connect the clock input pin only to the MMCM's input, without other connections to the net. Most likely, the IO can only drive a single clock-net buffer at the pin site, but you're trying to drive two. For that, the signal needs to go to the fabric => DRC 23-20 (theory!). Note, if you're using default MMC settings, "clk_div_inst" will include its own clock buffer. This can be disabled on the first page of the clkWiz IP configuration page (bottom right corner). If I had to measure jitter on the input clock per my own suggestion, the easiest way might be to simply build a 2nd bitstream
  45. 1 like
    Welcome to the forum! How you do this depends on the internal logic you want to read. Could you explain a little more about your project? There are two primary ways for MicroBlaze to interact with internal logic: First, via an interrupt controller. This is only used to trigger MicroBlaze to do something based on a single bit flag. Second, via an AXI interface. This is likely what you will need. There are a couple of ways to do this, but my suggestion, at least to start with, would be to connect your internal signals to the gpio_io_i port of an AXI GPIO controller. Note that if your signals change frequently, or you can't just poll the signals, then you will likely need a proper AXI interface. Thanks! Arthur
  46. 1 like
    Hi @skakon, I have sent you a PM about this. Thanks, JColvin
  47. 1 like
    It looks like you don't have the vivado-library repo. This typically happens if you downloaded the repo using the Download ZIP button on Github, which doesn't include git submodules. Two options: clone the base-linux repo with the following command line: git clone --recursive https://github.com/Digilent/Zybo-Z7-20-base-linux.git Or use you project: run the cleanup script in the proj folder, download the vivado-library repo from our github (you can use the Download ZIP button, it doesn't have submodules), and copy the vivado-library folder to the repo folder in your project. then re-run I recommend the first option, it will just make things easier in the long run if you use git. Whichever you choose, you should then run create_project.tcl, and you will see that same error again. Upgrade the IPs (it should work this time), and then close Vivado (don't forget to close Vivado). Then run the clean-up script in the proj folder (or just manually delete everything there except the cleanup scripts, release script, and create_project.tcl). Then run the create_project.tcl and all should work.
  48. 1 like
    @wanderso, I'm not sure I follow your thoughts regarding the jumper port. Do you mean directly from the device using Verilog? Shouldn't be a problem. As opposed to what? I've now worked with many different SPI devices, and I have yet to need to generate a clock via MMCM for a SPI device (SDRAM on the other hand is a different story). SPI devices are usually really easy to run off of logic generated from the system clock, and the software is a whole lot simpler to do so. Just ... don't try to trigger off of the positive edge of this logic-generated clock within your design. If your timing is really tight, then use an ODDR module to send the clock to the output port. (You might need to scope this to see what's going on if things don't work ...) Still ... SPI timing is rarely that tight. Even more, the SPI clock rate on this device isn't connected to the decoder rate. You can find a straight verilog example of how to interface with the MIC3 here, although I'll be honest: I haven't had time to actually test it on my board (yet). (I've been too busy with HDMI video) Still, the repo has a test suite integrated into it, "proving" it works ... whatever that means for code that hasn't touched hardware. While it'd be fun to hook it up to an FM transmitter hack that I've got, ... I'd be worried about getting feedback between the two that would then destroy my fun. Still ... I'm off topic. As built, the wbpmic module will divide the 100MHz Arty clock to generate a logical strobe at a rate that is any integer division of 100MHz. Since dividing 100MHz by 2083 only gets you close to 48kHz, you might wish to use a fractional divider instead. Adjusting it for fractional division shouldn't be difficult at all. My plan was always to run the output into a fractional, reprogrammable resampling circuit ... I just haven't gotten that far with my device. Dan
  49. 1 like
    The Pseudo bit is in the Configuration Register (register '010' ), bit 18 (page 27 of the datasheet). The power-on-reset value for the register is 0x000117. We want it set to 0x040117 (well, if we only want to set the Pseudo bit), or 0x040110 if the gain of 1x is desired, as per Mr Colvin's post. To do this, we need to write over the SPI interface. Whenever a new write to the ADC occurs, the first byte goes to the Communications Register (see page 22). These are the bits that need to be sent: 0 - active low write enable for the Communication Register 0 - active low write command 0 - REN(2),- The address of the register to write to 1 - REN(1) - The address of the register to write to 0 - REN(0) - The address of the register to write to 0 - continuous read off. 0 0 - must be 0. This is then followed up with the data that will be written to the Configuration Register ( in this case - 0x040110) So the stream of bits we want to send out are: 0001 0000 0000 0100 0000 0001 0001 0000 In the FPGA design code above,this can be done by setting the initial values of the shift registers: signal cs_shift_reg : std_logic_vector(63 downto 0) := x"FF000000007FFFFF"; signal mosi_shift_reg : std_logic_vector(63 downto 0) := x"0010040110000000"; [code=auto:0] So here what it looks like in simulation, as these registers are written while the design starts up: Just to reiterate, I don't have access to the PMOD, so all of this code has not been tested other than by me eyeballing that the simulation waveforms match what I think they should look like. You will need to do a lot of checking against the datasheet - you will need to read it very closely, and double check everything! Also, my initial understanding was that you only needed to read only one channel. To read many channels the design will get a lot more complex and may need to be structured differently, to include a more complex FSM to switch to different channels. Mike
  50. 1 like
    Hi i1116345, From a quick read of the datasheet, it seems that you need to send a few register writes to switch ADC into continuous sample mode, and then you can just clock the data in every time DRDY is asserted. You can take either the high road (with lots of levels of abstractions in your design) or the often-muddy low road (where you do all the work on paper, and then just make a design that achieves the desired result). The high road most likely involves a soft CPU, with a SPI peripheral interface, and software that talks SPI that will configure the device and retrieve the samples. The low road involves a long shift register to send out the SPI signals needed to configure the eight registers in the device, and then a simple FSM that clocks in the samples when they are available, storing the values into a flip-flops connected to the LEDs. So to me the low road looks to be something like two or three 128-bit shift registers (as it has to program up to eight 8-bit registers), a counter to act as a clock divider, and a small FSM that clocks in the samples . I know which road I would take - but that is just me. Mike