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  1. 2 points
    Hello, Hoping that this might help you, I am sending you a demo application. It is a 3D Vision demo, based on VmdoCAM. Please note that this demo was not released, so it is not "polished". https://www.dropbox.com/s/zoyo4ja8cbgzv2j/3D Camera Demo Project.zip?dl=0. Good luck!
  2. 2 points
    Hi, I haven't looked at the board's specs, but you can find examples at https://github.com/hamsternz/ArtyEtherentTX (100BaseT on the Arty board) https://github.com/hamsternz/FPGA_GigabitTx (1000BaseT on the Nexys Video board). They should be helpful to you.
  3. 1 point
    @Tickstart, Gosh, you want examples? Let's see ... I've used loops in FIR filters to describe the logic required at each tap. I've used them within CORDIC's to describe the logic that neeeds to take place in a multi-stage algorithm. I've used them to apply the same I/O logic to multiple bits in a vector. I've used them in loops to bit-reverse vectors. I've used them within my differential pmod-challenge code to look for bit-sync across multiple synchronization possibilities. I've used them to check for the synchronization sequence within an HDMI stream, knowing it could come in at any time and in any offset. I've used loops within initial statements, to initialize any memory that wasn't initialized by my $readmemh command. Dan
  4. 1 point
    loops can be used to describe HW. normally this isn't done to describe complex HW though. An example of a loops that can be useful in VHDL are: parity (xor-reduce), any (or-reduce), none (not or-reduce), all (and-reduce), bit-reverse, bit-count (maybe), gf2 inner product, etc... More complex logic like long-division or shift-add multiplication can infer much more logic. very complex logic like a sorting algorithm would result in long synthesis times and likely a large, slow design.
  5. 1 point
    @Tickstart, Yes. Loops in HDL just generate more logic, not sequential logic. Remember: *everything* runs in parallel. "Sequential" loops in HDL have only the appearance of being sequential--they actually just describe logic. If you can't fit the logic within one clock cycle, then you will fail to meet your timing constraints. Dan
  6. 1 point
    jpeyron

    Zybo I2c Master

    Hi @david.600, You will need to download the Vivado library here. The specific Pmod IP is here and the relevent code is main.c, PmodCMPS2.c, PmodCMPS2.h and Here is a tutorial on how to use the Pmod IP's. cheers, Jon
  7. 1 point
    jpeyron

    Zybo I2c Master

    Hi @david.600, I would look at our vivado library here. We have IP cores that use spi, I2c, uart and gpio. If you look towards the bottom of this website here we have out pmods listed with what communication they use. I would suggest to look at the Pmod CPMS2 as an example if using I2C with the zybo being the master. Here is the AXI IIC Bus Interface v2.0 LogiCORE IP Product Guide that should be useful as well. cheers, Jon
  8. 1 point
    hamster

    One-hot encoding mystery

    The "sensitivity list" is the list of signals that will cause the body of the process to be evaluated when their values change. It can be also thought of the list of all asynchronous inputs and any clock signals used in the process. For hardware, usually the synthesis tool will generate the correct hardware anyway, regardless of any errors or omissions. For simulation they need to have all the required signals, as otherwise they body of the process won't be evaluated when it should be. For clocked processes, it should usually just be the clock signal and any async reset signal (which shouldn't really be used in FPGAs anyway!) For unclocked processes (asynchronous logic), it should be any signal that is used within the process. A template for a clocked process is this: process_name: process(clk, async_reset) begin if async_reset = '1' then x <= whatever_the_reset_state_is; elsif rising_edge(clk) then -- all your usual stuff if a = '1' then x <= b AND c; end if; end if; end process; In this case, if a = '1', b ='1' and then c changes the output x doesn't change - it only changes when the clk rises or if reset is asserted, which is why a,b and c are not needed on the sensitivity list. A template for an unclocked ("async") process is this: process_name: process(a,b,c) begin if a = '1' then x <= b AND c; end if; end process; if a = '1' and b = 'a' the process needs to be evaluated every time 'c' changes, so 'c' has to be on the sensitivity list. Likewise the output might change if a or b changes value, depending on the values of the other inputs, so they have to be there too. Having additional signals that aren't needed to the sensitivity list doesn't break anything, but it can waste time in simulation as the process triggers but nothing changes. You can do other things like "wait until rising_edge(clk);", which avoids the "if rising_edge() then" and nesting, but that is not "the done thing", and considered being a bit of a smarty-pants.
  9. 1 point
    D@n

    One-hot encoding mystery

    @Tickstart, I'm going to bow out at that question--I'm not familiar enough with VHDL to answer. Perhaps @hamster can come back and answer better than I. Dan
  10. 1 point
    Kristoff

    USB Isolation

    Hey, Someone asked a similar question here. -Kristoff
  11. 1 point
    sbobrowicz

    NetFPGA 1G CML

    I'll provide a short answer: It will require work on your part. Probably several weeks, depending on your expertise. You can compile your HDL (assuming verilog or VHDL is used) in the equivalent Xilinx tools, but any references to primitives or IP Cores will need to be ported over to the Xilinx equivalents. The good news is that these two companies follow each other very closely from a feature perspective, so I would bet that you will be able to track down fairly similar equivalents in most cases. If you want to go down this road you can expect to receive some help here on the forum, but you will need to keep your questions scoped to reasonable size. Nobody is going to do this entire project for you (for free, there are contractors available out there). I'll also warn what Jon mentioned above: the NetFPGA boards (the 1G CML and SUME) are not "general use" FPGA platforms and were created specifically to be used with the NetFPGA project software. This means they don't have general purpose support content from Digilent, so you won't get a lot of out of box support either. You could avoid this if you went with a platform that is Digilent supported, such as the nexys video or Genesys 2.
  12. 1 point
    jpeyron

    Size series resistors used on PS/2 PMOD?

    Hi @dcooper, My co-worker let me know that they already answered your question on a different platform, but for the anyone looking for this information on the forum the size of the resistor is R0402. thank you, Jon
  13. 1 point
    Notarobot

    Zybo I2C

    @david.600, In my undestanding there are two ways to implement I2c on Zybo: - using I2C peripherals embedded in ARM; these can be conigured to be connected to Pmod JF because MIO pins can be wired to this Pmod only. You can use MIO configuration and select MIO 10 (scl) and MIO 11 (sda), for example. - using Xilinx AXI_IIC. You can get HDL source code from the PmodRTCC project and modify it to your requirements. Advantage of the first option is that all programming is done in C-code. I am not sure that you can implement interrupts. The second option has fewer limitations. It is possible to use four Pmod ports and implement interrupts but at cost of more coding and FPGA fabric. I think that it might be also slower that ARM peripheral because AXI peripherals introduce latency.
  14. 1 point
    Hello, First, thank you @Notarobot for the Linux fixes. I did not manage to run them all in Antergos, but the library symlinks actually allowed me to find out the processor gets into an infinite loop, without ever entering my main(). I decided it`s too much pain to try and run this on Linux, and have installed Vivado from scratch into Windows. Second, about the Digilent tutorial I was following, also mentioned by @jpeyron, I had made a silly mistake - I had selected only the "part" (the FPGA model code) on the project settings. That`s why there were no board interfaces to choose from in the Connection Automation step. I downloaded the board files and selected the correct one for the project settings, now I have all the right interfaces to choose from. I`m not sure how to mark this question as closed.
  15. 1 point
    Notarobot

    Zybo I2C

    Hi, @david.600 My advice would be to look at the Digilent PmodRTCC. It communicates with the Zynq ARM via I2c. I tested it in the past and it worked as advertised. Communication works two-way. I was able to read RTCC and write settings. Looking at the code provided on GiHub you will find answers for your questions. I made only few modifications when used it because had other components in the system. You can use other devices instead of RTCC, even several devices on the same I2c bus provided they have different addresses. Also I2c is very well supported on Arduino although not very fast. Good luck!
  16. 1 point
    D@n

    Advice for workstation configuration

    @random_cat, All of my designs support a TCP/IP->USB->UART interface. It allows me to control my board, connected to my desktop, from my laptop or indeed from any computer in my house. A VNC session, running over SSH, allows me access to Vivado, so I can build (and load) any designs. (I run Linux for everything, but discuss how to use my favorite tools from Windows here.) I blog about the TCP/IP->UART connection here. Feel free to ask if you think this is something that might work for you. I've discussed it extensively on my blog. Dan
  17. 1 point
    Hi, finally I have solved in this way: - I have modified the system-top-dts adding: usb_phy0: phy0 { #phy-cells = <0>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio0 46 1>; }; - I have also modified the pcw.dtsi in this way: &usb0 { status = "okay"; dr_mode = "host"; usb-phy = <&usb_phy0>; Attached the result. My usb key now is correctly detected and also the two partitions on it has been corectly detected into /dev. Thx again I hope this can be useful for others that have same problem. Michele
  18. 1 point
    Hi @Happybacon, The 12 bits represent a single sample. Each sample that you take from the MIC3 represents (in a sense) both the amplitude and the frequency of the measured signal. The ADC takes the resulting voltage coming from the microphone (after it goes through some filters) and digitizes the signal. Because the incoming signal from the microphone will be sinusoidal since it is measuring sound waves and the ADC takes up to 1 MSPS, you can get a nice collection of data points where you can view how quickly the data oscillates between the top and bottom peaks (the frequency) and how high and low those peaks get (the amplitude). The circuitry for the Pmod MIC3 is set up so that it oscillates around the voltage midpoint (Vcc/2). You can then put the data through an FFT if you wish. There is a demo of running audio data from a microphone through an FFT on a Nexys 4 DDR here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-spectral-sources-demo/start. Let me know if you have any questions. Thanks, JColvin
  19. 1 point
    Hi Terence, 1) Not sure how important this is but CS4344 datasheet lists 32kHz as its lowest sample rate, you're running at 8kHz. 2) Source code for HAL_I2S_Transmit 3) You could try this: double up sample array: uint16_t sawtoothUnsigned16bit[96] = {0x0, 0x0, 0x555, 0x555, etc... }; Then: HAL_I2S_Transmit(&hi2s2, &SINE_TABLE[0], 96, 0); 4) You're not checking the return value from HAL_I2S_Transmit. Setup an 8 bit GPIO for output and write the low byte to the GPIO. Use your lab monitor to see if you get any non-zero values.
  20. 1 point
    Hi @Michele, Unfortunately, I am not very experienced with embedded linux. I have reached out to a more experienced embedded linux engineer to look at this forum thread. cheers, Jon
  21. 1 point
    JColvin

    Zynq UltraScale board aka ZedBoard++

    Hi @ululuk, The best place to find out what new products are coming from Digilent will be through the Digilent social media channels including: Twitter, Facebook, Instagram, and the Digilent Blog. If you're looking for the secret sneak previews, I'd probably recommend checking out the Digilent Flickr where you get the added bonus of high resolution. Or so I've been told anyway. Thanks, JColvin
  22. 1 point
    Hi Terence, great to see you're making progress. I suspect the glitch is due to a hiccup in the data delivery software. For some reason the wrong value is making its way into the I2S channel. This could be due to 1) corrupted buffers/FIFOs, 2) timing delays, 3) debug or 4) interrupt priority inversion. I2S is an example of a 'hard' real time system. A new 32/48 bit value needs to be ready every 1/Fs th of a second, no ifs or buts. The I2S hardware will generally provide a FIFO bank (say 16 words), giving you a certain amount of buffer time. Your code needs to keep the buffer from becoming empty. I would normally use a DMA channel to service the I2S FIFO low signal (interrupt). This needs to be the highest priority task in the system. Polling probably won't cut it. I seem to remember you saying you were using an ST provided function. You will need to look at the source code to try and work out how it works. Is it using interrupts and/or DMA? Are there other interrupts in the system? The TI Cortex M4's have customisable interrupt priorities, ST are probably the same. Are there higher priority interrupts getting in the way? Do you have a single mainline testing/waiting for input and trying to deliver data? There are LOTS of things that it could be. This sort of thing can be difficult to debug as you generally need to run the processor at full speed without any breakpoints. It helps to flip GPIO bits around with the logic probe attached to see what is going on. For example, set GPIO1 on entry to an interrupt handler and clear it on the way out. Use a different GPIO for each distinct section of code and see what it gets you. If your lab device allows you to capture analog and digital signals together see if you can find any correlation between the glitch and the code path. For comparison, I am driving my PMODI2S with an Arty FPGA board. MCLK = 12.288MHz and LRCK is 64kHz (24bits/channel, internal SCK @MCLK/4). The internal calculation engine runs at 12,288,00MHz, same as MCLK. I don't buffer anything, my engine is hardcoded to load a 48 bit shift register every 1/64,000th of a sec. FPGA's make some things MUCH easier Cheers, Stephen
  23. 1 point
    Hi, congratulations. Ethrnet 0 MDIO seems to need to connect to MIO.
  24. 1 point
    jpeyron

    error in mux code using c for Tlut flow

    Hi @junaidahmad_k@yahoo.com, We do not have any experience with this software here. I would suggest to reach out through their contact email hes@elis.ugent.be. thank you, Jon
  25. 1 point
    Do you refer to https://reference.digilentinc.com/vivado/getting_started/start? If so, you don't need to use SDK since it only sticks to the logic part. What you need is to open the hardware manager and get Zybo Z7-10 connected.
  26. 1 point
    There were errors in the files I posted in an earlier post, mostly got confused and used THD+N everywhere. The math is probably ok, if anyone spot a fault, please let me know. Also take note that you need to setup your Waveform environment correctly, look at Attila post above to get a visual clue of what you need to enable. Otherwise there are going to be errors while running the script. I did not have time to have a shot at measuring IMD, still more to come. In hope that it is useful, here are some corrected files. THD_vs_Freq_%.dwf3script DummyLoad_2.pdf instructions.txt DummyLoad.dch Amplificateur_mesure.ods THD_vs_Power.dwf3script
  27. 1 point
    MDIO has been assigned to MIO by adding the following line to "Xilinx \ Vivado \ 2017.2 \ data \ boards \ board_files \ zybo-z 7-20 \ A.0 \ preset.xml". <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53" />
  28. 1 point
    jpeyron

    Ethernet shield

    Hi @Monics, I have moved you thread to a section that LabVIEW experienced engineers more commonly look. cheers, Jon
  29. 1 point
    jpeyron

    Zynq 7000 intr_dme example

    Hi @david.600, I am not aware of any code made to get around this situation. In the blog post you link to they disable the loopback mode. I would suggest to reach out to xinlinx to see if they have any suggestions about having the loopback function accept a realtec phy. thank you, Jon
  30. 1 point
    No problem. Here is the design in action - it's a kayaking trainer. I wanted to count flywheel revolutions so that I can calculate power output and log training sessions. I guess it's a standard data logging application. It was fun. I'm now considering a super accurate version that times the periods between each sensor event - but this will do the job well enough.
  31. 1 point
    Hi Terence, the waveform doesn't look great but it sort of looks like a 1kHz sawtooth with a fair bit of capacitance. I suggest using the analog ports on you lab tool. Connect the probe grounds to the shield (sleeve). Connect the two probe tips to the left and right channels (tip & ring). Declaring the array signed/unsigned makes no difference because you're 1) specifying the values in hex and 2) not performing any computations with them. The CS4344 cares, because it expects the values to be signed. You need to understand that sending 0x8000 (-32768) will send the output to its most negative point. Sending 0x7fff (+32767) will send the output to its most positive value. A zero value will result in a value halfway between the two extremes. The digital output needs to be MSB first, that means the sign bit (bit 15). Note that for the CS4344 (fig 7 again) the MSB needs to be in the second bit position following the LRCK transition. The first bit position should be occupied by the LSB from the previous frame. The little peak at the bottom of your sample suggests the framing is not quite right. Regards, Stephen
  32. 1 point
    thanks Jon - J1 has worked a whole load better than B13! it wouldn't have occurred to me that a file called Basys3_Master.xdc with the first line reading "## This file is a general .xdc for the Basys3 rev B board" and copied from the GPIO_Demo source code project would be wrong. but in my file the pin locations fed by the headers are all completely different from the one you linked at github. i shall take a copy from there and update all my local versions accordingly. many thanks!
  33. 1 point
    Hi @logicmonkey, If you can please share you wrapper. As for the xdc. Here is the Basys 3 xdc. It shows the constraint for JA[0] is: #set_property PACKAGE_PIN J1 [get_ports {JA[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] for your project it should be: set_property PACKAGE_PIN J1 [get_ports { mysensor }] set_property IOSTANDARD LVCMOS33 [get_ports { mysensor }] cheers, Jon
  34. 1 point
    Hi Terence, can't help with STM configuration. Glitches on LRCK are probably bad. Have you been able to find an I2S example program for the STM? Look for application notes against your processor and other related processors Do you have an oscilloscope? What does the analog output look like? It is worth checking the relationships between: (CS4344 Fig 7) 1) LRCK and SCLK. LRCK should change on SCLK falling edge. 2) SCLK and SDATA. SDATA should change on SCLK falling edge (SDATA gets sampled on rising edge of SCLK). You mention the data being unsigned (uint16_t). This is incorrect, it should be signed (int16_t). -ve sine wave peak occurs at 0x8000, +ve at 0x7fff. I generally use a spreadsheet to calculate this stuff then output as .csv before importing into code.
  35. 1 point
    Hey Jmason Have you tried using putty to SSH into your RPI 3? Also what version of Raspbian are you currently using? Thanks Austin
  36. 1 point
    Ok, are you using the SAI feature? What frequencies are MCLK and LRCK running at?
  37. 1 point
    Notarobot

    Using Canbus on the Zynq 7000 board

    @david.600 There are two Xilinx documents describing ARM implememtation of CAN interface controller: UG585 and PG096. CAN protocol is much more elaborate than RS232 or RS485 and I am not sure that starting oroginal development of CAN controller has reasonable justification. PmodCAN is an option but it will duplicate functionality of the existing controller implemented in Zynq. In my personal opinion the easiest way to implement CAN would be using approach described in UG585. You will need to use CAN SN65HVD230 breakout board, connect it to JF MIO Pmod and configure Zynq processing system for CAN0, for example. Xilinx also provides canps driver, example and test application in Vivado XilinxProcessorIPLib. Good luck!
  38. 1 point
    Piasa

    Using the Rj45 and Ethernet controller

    I don't think you can access the PS* (ARM) pins from the PL (FPGA) section of the SoC. You likely need to have ethernet connected to the ARM.
  39. 1 point
    Hi @david.600, The only Ethernet example that we have uses either Microblaze or Zynq processors along with the Echo server template in SDK. Here is the resource page for the zybo that has the getting started with zynq servers tutorial. Here is an Avnet forum thread that has some more information about using ethernet with zynq processor. thank you, Jon
  40. 1 point
    jpeyron

    Using Canbus on the Zynq 7000 board

    Hi @david.600, CAN communication can be reached using the Zynq processor through the emio pins on the board. Due to the way CAN works as described here you would need an external board to facilitate it since all of the i/o is 3v3. I have attached an Image of the Zynq processor for reference. We have a PmodCAN here that will facilitate CAN communication to other devices. This would be the way to go as long as your goal is working with CAN devices and not trying to make a CAN controller. cheers, Jon
  41. 1 point
    Hi @saurabhd, Welcome to the forums! This looks like a really interesting project. Unfortunately, I have not worked with GSM/GPRS. I would not be able to give helpful input. May be one of our more experienced community members may have some input for you. thank you, Jon
  42. 1 point
    jpeyron

    booting from QSPI

    HI @david.600, Here is a xilinx forum thread that deals with this issue. The member posts there process for adding their project to the flash. cheers, Jon
  43. 1 point
    Hi Terence, I'm afraid the PModI2S is the limit of my I2S experience. I'm using it with an Arty A7 to generate 91 sine waves in an attempt to clone a Hammond tone wheel organ. The master side of the interface is custom RTL (verilog). Basically a numerically controlled oscillator followed by a ROM (sine wave table) followed by a shift register. I had a quick look at the STM32F429 reference manual. On page 904: I2S Philips standard For this standard, the WS signal is used to indicate which channel is being transmitted. It is activated one CK clock cycle before the first bit (MSB) is available. Sounds like the CS4344 is 'Philips Standard' and will work with the STM processor. Cheers, Stephen
  44. 1 point
    Hi Terence, you've probably worked it out by now but I'll add this anyway. A 'gotcha' with the CS4344 can be found in Figure 7 of the data sheet. There is a 1 bit delay between the edge of LRCK and the MSB beginning on SDATA. In other words, the LSB of the previous L/R channel value is found as the first bit of the following R/L channel frame. Regards, Stephen
  45. 1 point
    D@n

    Correct Input and Outputs for PMODI2S?

    @Terence D, If you look at the data sheet for the CS4344, and specifically on page four of that datasheet, you'll find that the DEM/SCLK pin is an input signal to the chip, not an output. Digging a bit further, page 12 discusses how the SCLK can be generated internally, but also states that when doing so the DEM/SCLK pin is used as an emphases/de-emphasis selection pin. So ... I think what's going on is that while the device will generate an SCLK signal, I don't think that signal ever leaves the chip. Looking over your other numbers, a 24.4kHz LRCLK suggests a 24.4kHz sample rate. That's a not an audio rate I'm familiar with, neither is it one of the rates listed on 12 of the spec as being a supported rate. Are you sure you need this rate? If your incoming data is at this rate, you might wish to upsample the data to a higher rate. I put a resampling tutorial together some time ago although ... it does assume a certain level of DSP understanding. Holler if you need help, and I can help you go over it if this is something you decide you need to do. Hope that helps, Dan
  46. 1 point
    shockmonky

    Zybo ZYNQ Beginners help

    I had the same problem and switching the "reset Processor" to "Reset entire system" worked like a charm! Love you guys at Digilent!
  47. 1 point
    circuitsense

    FreeRTOS on Zybo

    Hello Everyone, This is just for reference. FreeRTOS running on the Zybo. I could not find any FreeRTOS based post on this forum so i thought this might help anyone trying to attempt the same... http://bit.ly/freertos-on-zybo
  48. 1 point
    JColvin

    Welcome!

    My name is James and I am one of the interns here at Digilent and am currently working to become a Pmod expert and will be happy to help you out with any difficulties you might be encountering.