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  1. Past hour
  2. Hello, I have a problem concerning the Digital Discovery using the Waveforms SDK. I thought it is possible to use the full 256MBytes on-board recording memory for 8-bit sampling, but I am only able to read 64M samples, no matter if I use 32 bit, 16 bit or 8 bit sampling (which I configure with the function FDwfDigitalInSampleFormatSet). The maximum size I can set via FDwfDigitalInBufferSizeSet() is 64M (i.e. 67108864), no matter what sample size I set via FDwfDigitalInSampleFormatSet(). That is, if I try to set a higher value for the buffer size, FDwfDigitalInBufferSizeGet() will still return 67108864, regardless which sample size is set (8, 16, 32). So I thought this buffer size value is the value for 32-bit sampling, and therefore 4 times as big when using 8 bit sampling. But unfortunately, when I try to read the data via FDwfDigitalInStatusData(), with a countOfDataBytes value that is higher than 67108864, all bytes after the 67108864 byte are zero. I am using single aquisition mode, and start an aquisition with FDwfDigitalInConfigure(handle, true, true) and then wait until the device state becomes DONE. I would be very thankful if someone could explain what I am doing wrong here. The Waveform GUI seems to be possible to do that (64M samples for 32 bit sampling, 256M samples for 8 bit sampling), so I thought it is possible with the SDK, too. Thanks.
  3. @PG_R Typically Ethernet PHY devices such as the Marvel 88E1111 are optimized to work with Cat5e cables. The interface between the PHY and the FPGA is immaterial; it doesn't make any difference whether it's RGMII, GMII, or SGMII. As long as the PHYs on both boards are setup properly to communicate at a particular speed, say Gigabit, and auto-negotiate you can just connect a cable between the boards and the PHYs will establish a connection without any assistance from the FPGA logic or ARM cores. Of course when the PHY is connected to FPGA logic then RGMII and SGMII is a bit more complicated, especially if you want to support 10/100/1000 rates. Most PHYs can be set to automatically switch input/output signals on the cable side so there isn't a driver conflict ( you needn't worry about using a cross-over cable ). The bad news is that programming many Ethernet PHYs is not always easy... the Marvel products require an NDA to see the register functionality. The good news is that for Xilinx and Digilent FPGA boards the PHYs are typically initialized on power-up or reset in the proper mode. For Intel based FPGA boards this is not the case as Intel wants you to be dependent on their IP to use the Ethernet PHY; this extends to their partners in crime. I've used the Ethernet PHYs to pass data between FPGA boards for many years. The next question then becomes; Do you want to use a MAC? For Zynq based boards the Ethernet PHY is connected to the ARM core through a MAC in the PS.. no getting around the MAC. For boards where the PHY is connected to logic you can do anything that you want. Once the PHYs on your boards have auto-negotiated a connection you will be responsible for the actual passing of packets and supporting particular protocols.
  4. Thanks for your help, I am sorry to say i am having problem with vivado identifying my ARTYS7 connected to my laptop
  5. Today
  6. Hi @KevL The Scope inputs are differential but not floating. A common ground connection between the analyzed circuit and device is needed. Without such the measurements can be wrong or the device and the circuit can be damaged. Connecting a floating battery is fine, since this gents balanced through the 1M scope input impedance. To test if the scope/awg is working you should connect the Scope 1+ (orange) to AWG W1 and Scope 1- (orange/white) to GNG (black) wire, generate and capture some signal.
  7. Esti.A

    OpenCV and Pcam5-c

    Hi @bogdan.deac, I followed your instructions but I found a error message while booting from the sd card the reVision platform that says the following: U-Boot 2017.01 (Aug 05 2018 - 22:17:14 -0700) Model: Zynq Zybo Z7 Development Board Board: Xilinx Zynq I2C: ready DRAM: ECC disabled 1 GiB MMC: sdhci@e0100000: 0 (SD) Using default environment In: serial Out: serial Err: serial Net: ZYNQ GEM: e000b000, phyaddr 1, interface rgmii-id SF: Detected s25fl128s_64k with page size 256 Bytes, erase size 64 KiB, total 16 MiB Warning: ethernet@e000b000 using MAC address from ROM eth0: ethernet@e000b000 U-BOOT for Zybo Z7 ethernet@e000b000 Waiting for PHY auto negotiation to complete......... TIMEOUT ! Hit any key to stop autoboot: 0 Device: sdhci@e0100000 Manufacturer ID: 1d OEM: 4144 Name: SD Tran Speed: 50000000 Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 58.9 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes reading image.ub 3910868 bytes read in 340 ms (11 MiB/s) ## Loading kernel from FIT Image at 10000000 ... Using 'conf@2' configuration Verifying Hash Integrity ... OK Trying 'kernel@0' kernel subimage Description: Linux Kernel Type: Kernel Image Compression: uncompressed Data Start: 0x100000d4 Data Size: 3878632 Bytes = 3.7 MiB Architecture: ARM OS: Linux Load Address: 0x00008000 Entry Point: 0x00008000 Hash algo: sha1 Hash value: 4b23816e227252b7549419997f26b3edbd525a7e Verifying Hash Integrity ... sha1+ OK ## Loading fdt from FIT Image at 10000000 ... Using 'conf@2' configuration Trying 'fdt@0' fdt subimage Description: Flattened Device Tree blob Type: Flat Device Tree Compression: uncompressed Data Start: 0x103b30b0 Data Size: 30941 Bytes = 30.2 KiB Architecture: ARM Hash algo: sha1 Hash value: 6bda90ed3c9361add0bd7bb38aeb560c25288661 Verifying Hash Integrity ... sha1+ OK Booting using the fdt blob at 0x103b30b0 Loading Kernel Image ... OK Loading Device Tree to 07ff5000, end 07fff8dc ... OK Starting kernel ... Uncompressing Linux... done, booting the kernel. Booting Linux on physical CPU 0x0 Linux version 4.9.0-xilinx-v2017.4 (digilent@ubuntu) (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11)) #1 SMP PREEMPT Mon Jul 9 19:13:02 PDT 2018 CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache OF: fdt: Machine model: Zynq Zybo Z7 Development Board bootconsole [earlycon0] enabled OF: graph: no port node found in /amba_pl/xilinx_drm EXT4-fs (mmcblk0p2): couldn't mount as ext3 due to feature incompatibilities INIT: version 2.88 booting Starting udev udev: Not using udev cache because of changes detected in the following files: udev: /proc/version /proc/cmdline /proc/devices udev: lib/udev/rules.d/* etc/udev/rules.d/* udev: The udev cache will be regenerated. To identify the detected changes, udev: compare the cached sysconf at /etc/udev/ udev: against the current sysconf at /dev/shm/udev.cache Populating dev cache ALSA: Restoring mixer settings... No state is present for card ZyboZ7SoundCard Found hardware: "Zybo-Z7-Sound-C" "" "" "" "" Hardware is initialized using a generic method /usr/share/alsa/init/default:26: value write error: Input/output error /usr/share/alsa/init/default:26: value write error: Input/output error /usr/share/alsa/init/default:263: value write error: Input/output error /usr/share/alsa/init/default:263: value write error: Input/output error /usr/share/alsa/init/default:265: value write error: Input/output error No state is present for card ZyboZ7SoundCard hwclock: can't open '/dev/misc/rtc': No such file or directory Tue Jul 10 02:14:48 UTC 2018 hwclock: can't open '/dev/misc/rtc': No such file or directory Starting internet superserver: inetd. INIT: Entering runlevel: 5 Configuring network interfaces... udhcpc (v1.24.1) started Sending discover... Sending discover... Sending discover... No lease, forking to background done. Starting system message bus: dbus. Starting Dropbear SSH server: dropbear. hwclock: can't open '/dev/misc/rtc': No such file or directory Starting syslogd/klogd: done Starting tcf-agent: OK as you can see it is not finding this device and I dont know if this causes not to display any image in the hdmi. I am using filter2d demo, as is suggested for PCAM-5c set-up.
  8. Hi @DurandA Please disable the data compression to prevent this issue, to make sure the last digital samples are recorded at such low rate.
  9. Hi @Luighi Vitón, Thanks for your reply and for your heads up, I'm glad you managed to get it working. --Ciprian
  10. Hi @DurandA The digital channels can't be accessed from the Logger tool, but you could perform a recording in the Scope with low rate like this: From Script you can access the StaticIO readings or captured data in Logic or Scope like this:
  11. Szia @Andras At the moment you have WAV RIFF WAVE export under Scope/View/Logging/Script/Example.
  12. Hi @Frenchpark43 It should work, it is working for me on Ubuntu 18.04 amd64 You could try install with: sudo dpkg -i --force-depends digilent.waveforms_3.9.1_amd64.deb
  13. First, it utilizes an FPGA that you can use the Xilinx Vivado FPGA Design Tools. The BASYS2 uses a Spartan-7 and that is not supported in VIVADO. Second is that the BASYS3 board has quite a few switches and displays that can be used out of the box without wiring anything up, and or debugging, so that you can immediately start to program and use buttons and switches and control displays and use the online starter labs without wiring up peripherals and then wondering if you are having an interface problem or a program problem.
  14. revathi


    Hi everyone, Am doing research in Signal processing. My aim is to obtain the samples from xadc and it should be applied to my signal processing algorithm. Am working in Zynq 702 board. Still n ow i have applied the external analog signal to the dedicated pin Vp an Vn and by using AMS gui i have debugged the xadc converted value. Now without using any GUI , i would like to debug only the Vp and Vn converted value by using ILA, i have attached the block diagram of my design and the specifications.kindly refer it. My Problem is i have selected channel sequencer and i need to visualize only the xadc data of Vp and Vn input signal. But in Do[15:0] am geeting all the datas like temperature, alarm etc. KIndly reply me it will be helpful for my research progress. XADC block dgm.docx
  15. I am just using the Analog Discovery 2 (no BNC adapter). I am using the solid orange wire on the positive side of the battery and the orange with white stripe wire on the negative side. The 30 pin connector is fully seated in the AD2. I've also tried using individual 2 pin connectors instead of the 30 pin connector and got the same results so I don't think the issue is with the connector. I was using the oscilloscope view but have switch to the voltmeter view to narrow down the issue. Do you have any other suggestion? Thanks for your quick response.
  16. Yesterday
  17. Hi @LazerBoi64, I heard back from the engineer who designed LINX and got it working with the Rasberry Pi and the BeagleBone Black. Unfortunately though, they don't remember the exact version that was used beyond it being an 8.X variant. Based on this, I would guess it would probably be a slightly earlier version than 8.6 was loaded (such as the 8.5 variant), but again, that is just a guess. I'm sorry I don't have more definitive information for you. Thanks, JColvin
  18. Hi, as I mentioned in the previous post as the Zybo-z7-20-base linux was not referenced by the Petalinux project build, so I sourced the hardware description: petalinux-config --get-hw-description=<PATH-TO-HDF-DIRECTORY> I did as well the petalinux-config and selected SD card instead of initramfs . The outcome is that there is some activity of the board afterwards the sd with boot.bin and image.ub are copied on the card and fed into the Zybo: the LED Green is blinking I tried connected to the serial terminal with screen , but no establishing of the communication is done. With dmesg -w , the Zybo device seems restarting and the peripherals listed by the dmesg are ftdi and /dev/ttyUSB0 , and it seems disconnected and the serial is enumerated afterwards on the /dev/ttyUSB1 and this restarting of the Zybo board is like continous after 5 or 10 seconds. Also the HDMI synk to the display is without effect and I can not see the "desktop" of the Petalinux. I had a post here: that only the pipeline_mode_change(vdma_driver, cam, vid, Resolution::R640_480_60_NN,OV5640_cfg::mode_t::MODE_720P_1280_720_60fps); worked when debugged on ARM the project . I would be interested if something similar - a setting of the HDMI -dvi2rgb or other display driver could be done when initializing the Programming System - ARM : something like the following snippet set video resolution (Resolution::R640_480_60) into this file ?? Thanks and regards!
  19. Hi @KevL, When you are measuring across the battery with one of the channels (channel 1 for example), I presume you are using the solid orange wire on the positive side of the battery and the orange wire with the white stripe to measure the negative end of the battery? In the interest of covering all of the bases, is the 30 pin connector connected all of the way into the Analog Discovery 2? Additionally to clarify, are you just using the Analog Discovery 2 or are you using a BNC adapter? Additionally, if you are using the oscilloscope view (as opposed to the voltmeter view), do you have any attenuation set? Thanks, JColvin
  20. Hi @JColvin, Thanks for your reply. I am trying Petalinux with Zybo-Z10 and PCam 5C. I tried reproducing the setup from here and listed my blockings if you could help. Thanks and regards!
  21. Hi @Ciprian, After some time, I managed to solve this issue. In fact, It was a problem in the hardware and device tree configuration. I discovered it when probing with another example project named Zybo-hdmi-out ( However, as this project is for a previous version of Vivado, I tested with Vivado 2017.4. Surprisingly, it worked fine but with another pixel-format in the device tree. The Zybo-base-linux project which I used, has a pixel format in DRM device tree configuration set to "rgb888", however, for the Zybo-hdmi-out, it displayed correctly with pixel-format "xrgb8888". If I use other pixel formats, no output is displayed in both cases. Going deep into the configuration of both projects, I discovered that there are some differences in the VDMA and Subset converter settings, which changed to the configuration in Zybo-hdmi-out, solves the problem of colors and rendering, considering also a pixel format in the devicetree equal to "xrgb8888". I attached the images of both configurations. In addition to this, I managed to update the design for the Vivado version I use (2018.2) with no more differences that a change in the AXI memory interconnect replaced by the AXI Smart connect in the newer version, which is added automatically when using Vivado autoconnect tool for the VDMA block. Hope this information could help others which run in the same issue. Thanks for your help. Luighi Vitón
  22. jpeyron

    Data compression

    Hi @Mukul, I have worked a little bit with data compression in software. I am not very experienced with using data compression in FPGA's. Hopefully one of the more experienced community members or staff will have some good input for you. best regards, Jon
  23. @sbellamy Why yes, there is a document that indicates Xilinx pin naming conventions: UG475 7 Series packaging and Pinout Product Specification User's Guide, see Table 1-12. This is one of the many valuable documents that is required reading for the FPGA developer. Use the Document Navigator. Download all relevant documents for your device as your personal library. Check often for updates. I realize that there is a ton of stuff to read but learn how to find answers to your questions. Xilinx doesn't always make it easy to find specific information which is why it's important to get familiar with what's available and where specific information might be.Your question is a very good one and I'm surprised that it hasn't shown up before ( well as long as I've been using this forum...). [edit] A peculiar thing about the Zynq family is that Xilinx seems to treat it like an ARM product even though different versions have a PL based on different Xilinx FPGA families. This means extra work for the customer. The pin name conventions work for Zynq PL pins and all other Xilinx FPGA families.
  24. jpeyron

    PCIE on CMOD-A735T

    Hi @Charles Li, Welcome to the Digilent Forums! To meet a specific tier of development board not all of the FPGA's capabilities are facilitated in every Digilent FPGA development board. Here is the Cmod A7 resource center. On the schematic for the Cmod A7 you can see on page 3 what pins have been routed on banks 14, 16, 34 and 35. Here is a list of Digilent boards that have the transceivers routed. Zedboard Nexys Video Genesys 2 NetFPGA Sume best regards, Jon
  25. jpeyron

    SDK issue

    Hi @Kris Persyn, It looks like your first first screen shot with the application sw you selected empty template. You will need to add or import a main.c under the scr folder. If you expand your bsp as well as the HW platform you should be able to find the libraries included in the IP cores in your HW platform. best regards, Jon
  26. Kris Persyn

    SDK issue

    Hi, I'm using a zyb z7-020 and have made a block design with PS and PL elements. However when I export my hardware (w bitstream) and try to create a new project SDK makes an incomplete project folder? Any ideas about what could cause this? For another project I basically did the same steps and it produces no errors..
  27. Hello, I have a problem with connection to my local WiFi network. I make everything as it is said in tutorial. The connection is possible only with my mobile phone hotspot but not with my local network with WPA2 Personal security system. Always there is Error setting WiFi parameters. Can anybody tell me what am I doing wrong or how to connect OpenScope to my local network ? Thank You Vroobee
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