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  2. I am considering the AXI USB 2.0 Device Controller https://www.xilinx.com/products/intellectual-property/axi_usb2_device.html I need about 400 Mbps total speed. I think the speed on USB UART is around 12 Mbps. Thank you for the link. I might use USB UART for the first round with smaller number of data channels (not the total 128 output channels of my setup). Is there any other way to reach this speed? I need to record a couple of seconds of data. Can I write on a memory with this speed and then transfer it to the computer with a lower speed of USB UART? Is there an example for using the on board RAM?
  3. Hi @andre19, Is there a reason you are trying to use microblaze on a zedboard which has a zynq processor? best regards, Jon
  4. Hi @HasanWAVE, Digilent board files makes connecting the buttons through the boards tab. Using the boards tab constrains the pins as well. Otherwise you can find the Arty-Z7 XDC here. Here is an GpioPS interrupt example that should be helpful. Best regards, Jon
  5. Hi @RFtmi, Welcome to the Digilent Forums! Are you referring to using the USB OTG and the USB 2.0 On-The-Go IP? Or the USB UART Bridge and the uartlite and the uart16550? I'm not aware of a free IP Core that facilitates using the USB OTG without linux. The USB UART Bridge is accessible through the ZYNQ Processor. Here is an Cora-Z7-10 XADC project that uses the USB UART Bridge which can be used through the Webpack edition of the Vivado. best regards, Jon
  6. Hi @jpeyron It is my IP blocks: For external clock i write next: set_property -dict { PACKAGE_PIN F7 IOSTANDARD LVCMOS33 } [get_ports { clk_in1_0 }]; create_clock -period 30.303 [get_ports { clk_in1_0 }];#set Clock connected to clocking withard IP
  7. Today
  8. Hi @andre19, The Digilent board files correctly configures the DDR as well as constrains the pins. You can not use the mig since the DDR is directly connected to the PS. Here is an Avnet thread that discusses this as well. You will need to use the Zynq processor to interact with the DDR. Please attach your block design to better help with the clk. Make sure that the xdc name needs to be the same as the pin name in the wrapper file. best regards, Jon
  9. The total data rate will be less than the full speed of USB 2.0. I can multiplex the lines before feeding the FPGA or pick another board with more IOs. The main question here is 1- Do I need a license? 2- Is there an example of doing it? (without Linux just through the hardware and possibly a C code)
  10. Another update. I decided to try the DE0 Nano with the Jetson Nano since the code and application have evolved a bit since the CMOD-A7 versions. Win7 PC Up^2 N4200 Jetson Nano Data Sectors Payload Bytes Upload MB/s Download MB/s Upload MB/s Download MB/s Upload MB/s Download MB/s 127 65024 43.1471 42.1225 42.853889 45.721241 35.106934 38.934151 511 261632 42.1225 42.7433 42.979492 46.239983 35.065121 38.884438 767 392704 42.0514 42.7561 42.898247 20.149193 33.739391 16.723478 1023 523776 41.9084 42.7521 42.931019 12.217526 35.086201 10.197824 2047 1048064 40.4817 42.7381 42.907658 9.832075 35.111324 7.109247 4095 2096640 42.0431 37.316 6143 3145216 41.3916 39.1262 As you can see the problems previously reported for the Jetson Nano were likely due to compilation issues. I've made no attempt at a threaded application which might help. The drop-off in data rates for higher payloads might be due to Linux driver behavior. The Jetson is archaa64; the UP Squared is x86_64. The data rates for the UP^2 at or below 256KB payloads are unexpectedly high. All rates are based on the total time that data was being sent or received by the FPGA and measured in 60 MHz clock periods.
  11. Plus How to corectly in XDC file connect CLOCK and RESET? Microblaze need clock, i have external clock and manualy in XDC write : set_property -dict { PACKAGE_PIN F7 IOSTANDARD LVCMOS33 } [get_ports { clk_in1_0 }] [DRC NSTD-1] Unspecified I/O Standard: 2 out of 53 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_rst_0, and clk_in1_0. Best regards
  12. isn't that 512 Mbps, with USB 2.0 ~ 480 Mbps max? And I wouldn't bet on achieving that. You could set up a simple Ethernet UDP dummy data generator on Zynq with what would be a few lines of C code on regular Linux, to check how much of that "gigabit" is actually achievable. But I suspect your requirements are deep in PCI territory. BTW, I'm still looking for the 128 IOs on this board.
  13. Hi @jpeyron Some questions about true/not true my understandings. In Arty A7-35 in "Block design - board"i clicked on "DDR3" and DDR3 connector will avtomaticaly conected to MIG_7 IP. In Zedboard i work with another chip wy, i manualy in XDC file wrote adresses for all DDR3 conector Some remark In Z7020 chip in IP design i added MIG_7 but IP was without out for DDR3 like in project for Arty-A7 board. Than i changed properties (double click on IP) and change type of memory and then i seen output for DDR3 (like are in screan above). What do you phink? Best regards.
  14. Hi @rohanchakraborty function date() { var now = new Date(), year = '' + (now.getFullYear()%2000), month = '' + (now.getMonth() + 1), day = '' + now.getDate(); if (year.length < 2) year = '0' + year; if (month.length < 2) month = '0' + month; if (day.length < 2) day = '0' + day; return [year, month, day].join('_'); // '' no separator } .... var filename = "~/Desktop/SeeIfIWork/"+date()+"/Messung"+Index+".png" Impedance.single() Impedance.wait() Impedance.Export(filename)
  15. It is interesting article.
  16. Hello, I have an ARTY Z7 board and I am trying to use the push buttons as an interrupt source for the PS. I want to use GpioPS not the FPGA Gpio. What I cannot understand is which pin will my switch buttons be located on ? Which pin should I put in XGpioPs_SetDirection(Gpio,XX,0x0) in the XX field. I read the schematic but couldn't understand. What I understand is that XX value would be one of the MIO values which use the GPIO, but I can't seem to make it work. Regards, Hasan
  17. Here's my code StaticIO.Channel0.DIO[3].text = "0"; StaticIO.Channel0.DIO[4].text = "1"; StaticIO.Channel0.DIO[5].text = "1"; StaticIO.Channel0.DIO[0].text = "0"; StaticIO.Channel0.DIO[1].text = "0"; StaticIO.Channel0.DIO[2].text = "0"; Impedance1.single() wait(120) ... BUT I'd like to export my file with respect to the date and time it was created. Can anyone help. So the date and time should be as a folder Impedance1.Export("~/Desktop/SeeIfIWork/"#ddmmyy"/Messung"+Index+".png")
  18. On VCU118 FPGA, getting wrong results for "Rout" as the dept increases more than 20 in the following RTL code. In Behaviour simulation and post-synthesis functional simulation, I am getting the expected results. But, on FPGA not getting the same results? what would be the reason, can some one please help me? ----------------------------------------------------------------------------------------------------------------------- module BRAM_resi #(parameter Bit_size=10, parameter dept=50)( input clk,clk_ila,reset,reset_of, input [(Bit_size+5):0]in, output reg [Bit_size*2-1:0]Rout ); (* ram_style = "block" *) reg [(Bit_size+5):0] mem [dept-1:0]; reg[9:0]cnt,cnt2; reg [Bit_size*2-1:0]R1,R2; reg signed [(Bit_size+5):0]sub; reg R_on; reg state; always@(posedge clk) begin if(!reset) begin cnt<=0; R_on<=0; Rout<=0; R1<=0; R2<=0; state<=0; end else case(state) 1'b0: begin R1<=R1+in; Rout<=R1; mem[cnt]<=in; if (cnt<(dept-1)) cnt<=cnt+1; else begin state<=1; cnt<=0; end end 1'b1: begin Rout<=R1; mem[cnt]<=in; if (reset_of) R1<=(R1>>1); else R1<=((R1+in)-mem[cnt]); if (cnt<(dept-1)) cnt<=cnt+1; else begin cnt<=0; end end endcase end endmodule --------------------------------------------------------------------------------------------------------------------------------------------
  19. Thanks, that works like a charm! I am now limited by the OS's handling of USB, I think, which means I can set DC values at up to 1 kHz (or slightly below if the OS is busy), and settling time is < 100ns. That exceeds the performance we'll be needing with some margin to spare. Great.
  20. Ok, I hope to hear from you next week then! Best regards Mats
  21. I edited the question and included more details.
  22. Reading between the lines (apologies if I'm wrong, this is based solely on four sentences you wrote so prove me wrong): I see someone ("need the full speed ...") who'll have a hard time in embedded / FPGA land. For example, what is supposed to sit on the other end of the cable? A driver, yes, but for what protocol and where does that come from? Have you considered Ethernet? It's relatively straightforward for passing generic data and you could use multiple ports for different signals to keep the software simple. UDP is less complex than TCP/IP and will drop excess data (which may be what I want, e.g. when single-stepping code on the other end with a debugger).
  23. Short story: I want to use the Cora board to combined multiple low data rate signals and send it through the USB 2.0 port to a computer. I need the full speed of the USB 2.0. Do I need to buy a license for USB 2.0 from Xilinx to use Vivado for programming it? Is there any example code for running the USB 2.0 you could refer me to? Long story: I have a test setup for a chip that has 128 digitized data outputs less than 4Mbps each. I need to transfer these data outputs into a computer with real-time speed. I thought the easiest way is to use an FPGA, combine the 128 data lines, and send them through the USB port. I am looking at the Digilent Cora Z7 board that has the USB 2.0 port on the board. When I was reading Xilinx USB 2.0 manual I noticed the licensing part. Does the license come with the Digilent boards? Do I need to purchase a license to activate the USB IP on Vivado and programming the FPGA? Also, it seems that it is a lot of work to figure out the USB IP and getting it working. Is there any example code for running the USB 2.0 you could refer me to? Would it be easier if I use Ethernet or something else?
  24. Yesterday
  25. Hello @mustafasei, It looks like from your screenshot you did not create a string constant but are still using the VISA Resources drop-down since the correct USB device for the Arduino will not appear on the list. I imagine you are using a cdc-acm USB serial device (such as the Arduino Uno or Leonardo) so there was a bug in VISA that got an update though I don't know if it was ever formally rolled out, but this LabVIEW MakerHub thread discusses this. You might also use "dmesg | grep tty" as a way to find out the attached devices rather than listing everything. Thanks, JColvinn
  26. jpeyron

    Webserver using Zybo Z7

    Hi @sgandhi, I did a quick internet search for "create a FAT image on linux" and this blog looks like it should be helpful. I have not worked with this example. I would suggest reaching out to Xilinx support about the LWiP examples since they would have experience with the webserver example. best regards, Jon
  27. sgandhi

    Webserver using Zybo Z7

    Hello @jpeyron, I was looking into some examples in the \lwip202....\examples and found one lwip webserver example that uses index.htm file present in FS! Now when I follow the readme.txt file for directions to execute the example, I see some steps as follows: ********************************************************************** Creating FAT image on Linux --------------------------- This requires root (sudo) access on the Linux host Following commands can be used on terminal to create FAT image to be used with webserver application: # create image file of 3MB dd if=/dev/zero of=example.img bs=512 count=6144 # format image with FAT /sbin/mkfs.vfat example.img # mount it mkdir /tmp/fs sudo mount -t vfat -o loop,rw example.img /tmp/fs/ # copy your webpages sudo cp -r webpages_dir/* /tmp/fs/ sudo umount /tmp/fs *************************************************************** And then it tells to run the application... I just tried to run the application w/o creating FAT image, which is obvious to give me the errors!! In order for the webserver to gain access to index.htm, the file needs to be present at the specific location. Is that why we create a FAT image on linux??? Also, the steps in readme.txt tells me to runs those commands on the terminal... How do I start with this? Is it talking about the sdk terminal? As per the directions, I added all the necessary source files and I also included the BSP settings as mentioned! Next step is to create a FAT image on linux... I am wondering how do I start with this! Thanks, Shyama.
  28. Hi @jpeyron Yes I folow the instructions on you tube and I can see the port number for arduino in the device manager and I put the same port in .vi when I connect the arduino directlly on PC USB port but. my problem is when I connect the arduino on raspberry pi3 USB port what will be the port name because in the thread below some says it is (ex /dev/ttyUSB0 andsome says it must be (ASRL2::INSTR ) and other say (/dev/ttyACM0) or (/dev/ttyACM1) I have used this command (ls /dev/tty*) on RPI and I got ports as picture below but still not work when i put it in the .vi and give me the same error of 5006 in my previous post. any idea please ?
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