All Activity

This stream auto-updates     

  1. Past hour
  2. Today
  3. Hello, I'm using MTDS, that is working well in portraito mode. But when I change orientation to landscape mode, the TextOut() dosen't draw beyond 30 chars(240 pixel?). My initialization code as follows. Do I need some more setting for landscape mode? regards, mtds.begin(); hdsDisp = mtds.GetDs(); hbmp = mtds.GetDisplayBitmap(); mtds.SetDrawingSurface(hdsDisp, hbmp); mtds.SetFgColor(hdsDisp, clrWhite); mtds.SetBgColor(hdsDisp, clrBlack); mtds.SetTransColor(hdsDisp, clrBlack); mtds.SetPen(hdsDisp, penSolid); mtds.SetDrwRop(hdsDisp, drwCopyPen); mtds.SetBkMode(hdsDisp, bkOpaque); mtds.SetFont(hdsDisp, hfntConsole); mtds.SetIntensity(hdsDisp, 100); mtds.SetDisplayOrientation(dsoLandscape); mtds.TextOut(hdsDisp, 0, 0, 40, "1234567890abcdefghijABCDEFGHIJ!@#$%^&*()");
  4. @Ciprian hi .. i appreciate your help and with ur post i easily build the petalinux package.. now i have an issue... i put the BOOT.bin and image.ub in SD card... and i can see on my terminal zybo is booting... but there is no display on HDMI... nothing that is boot log # Loading kernel from FIT Image at 10000000 ... Using 'conf@1' configuration Verifying Hash Integrity ... OK Trying 'kernel@0' kernel subimage Description: Linux Kernel Type: Kernel Image Compression: uncompressed Data Start: 0x100000d4 Data Size: 3747152 Bytes = 3.6 MiB Architecture: ARM OS: Linux Load Address: 0x00008000 Entry Point: 0x00008000 Hash algo: sha1 Hash value: 9148b4404b115a186177ed7382575198177ace89 Verifying Hash Integrity ... sha1+ OK ## Loading ramdisk from FIT Image at 10000000 ... Using 'conf@1' configuration Trying 'ramdisk@0' ramdisk subimage Description: ramdisk Type: RAMDisk Image Compression: uncompressed Data Start: 0x10397780 Data Size: 5710888 Bytes = 5.4 MiB Architecture: ARM OS: Linux Load Address: unavailable Entry Point: unavailable Hash algo: sha1 Hash value: e746a76fc1a540d3ce401458e53bfb6f97a4da98 Verifying Hash Integrity ... sha1+ OK ## Loading fdt from FIT Image at 10000000 ... Using 'conf@1' configuration Trying 'fdt@0' fdt subimage Description: Flattened Device Tree blob Type: Flat Device Tree Compression: uncompressed Data Start: 0x10392f18 Data Size: 18360 Bytes = 17.9 KiB Architecture: ARM Hash algo: sha1 Hash value: ac86165606bbdd5ddb6ede988a4b11dd1a6ac878 Verifying Hash Integrity ... sha1+ OK Booting using the fdt blob at 0x10392f18 Loading Kernel Image ... OK Loading Ramdisk to 07a8d000, end 07fff428 ... OK Loading Device Tree to 07a85000, end 07a8c7b7 ... OK Starting kernel ... Uncompressing Linux... done, booting the kernel. Booting Linux on physical CPU 0x0 Linux version 4.9.0-xilinx-v2017.4 (bilal@ubuntu) (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11) ) #1 SMP PREEMPT Tue May 21 20:56:12 PDT 2019 CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache OF: fdt:Machine model: xlnx,zynq-7000 bootconsole [earlycon0] enabled cma: Reserved 16 MiB at 0x3f000000 Memory policy: Data cache writealloc percpu: Embedded 14 pages/cpu @ef7d0000 s25932 r8192 d23220 u57344 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260608 Kernel command line: console=ttyPS0,115200 earlyprintk PID hash table entries: 4096 (order: 2, 16384 bytes) Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) Memory: 1007272K/1048576K available (6144K kernel code, 200K rwdata, 1460K rodata, 1024K init, 229K bss, 24920K reserved, 16384K cma-reserved, 245760K highmem) Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xffc00000 - 0xfff00000 (3072 kB) vmalloc : 0xf0800000 - 0xff800000 ( 240 MB) lowmem : 0xc0000000 - 0xf0000000 ( 768 MB) pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) modules : 0xbf000000 - 0xbfe00000 ( 14 MB) .text : 0xc0008000 - 0xc0700000 (7136 kB) .init : 0xc0900000 - 0xc0a00000 (1024 kB) .data : 0xc0a00000 - 0xc0a32000 ( 200 kB) .bss : 0xc0a32000 - 0xc0a6b698 ( 230 kB) Preemptible hierarchical RCU implementation. Build-time adjustment of leaf fanout to 32. RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2 NR_IRQS:16 nr_irqs:16 16 efuse mapped to f0802000 slcr mapped to f0804000 L2C: platform modifies aux control register: 0x72360000 -> 0x72760000 L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000 L2C-310 erratum 769419 enabled L2C-310 enabling early BRESP for Cortex-A9 L2C-310 full line of zeros enabled for Cortex-A9 L2C-310 ID prefetch enabled, offset 1 lines L2C-310 dynamic clock gating enabled, standby mode enabled L2C-310 cache controller enabled, 8 ways, 512 kB L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001 zynq_clock_init: clkc starts at f0804100 Zynq clock init sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns Switching to timer-based delay loop, resolution 3ns clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns timer #0 at f080c000, irq=17 Console: colour dummy device 80x30 Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) CPU: Testing write buffer coherency: ok CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 Setting up static identity map for 0x100000 - 0x100058 CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 Brought up 2 CPUs SMP: Total of 2 processors activated (1333.33 BogoMIPS). CPU: All CPU(s) started in SVC mode. devtmpfs: initialized VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns pinctrl core: initialized pinctrl subsystem NET: Registered protocol family 16 DMA: preallocated 256 KiB pool for atomic coherent allocations cpuidle: using governor menu hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers. hw-breakpoint: maximum watchpoint size is 4 bytes. zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0xf0880000 zynq-pinctrl 700.pinctrl: zynq pinctrl initialized e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 26, base_baud = 6249999) is a xuartps àconsole [ttyPS0] enabled console [ttyPS0] enabled bootconsole [earlycon0] disabled bootconsole [earlycon0] disabled vgaarb: loaded SCSI subsystem initialized usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb media: Linux media interface: v0.10 Linux video capture interface: v2.00 pps_core: LinuxPPS API ver. 1 registered pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> PTP clock support registered EDAC MC: Ver: 3.0.0 FPGA manager framework fpga-region fpga-full: FPGA Region probed Advanced Linux Sound Architecture Driver Initialized. clocksource: Switched to clocksource arm_global_timer NET: Registered protocol family 2 TCP established hash table entries: 8192 (order: 3, 32768 bytes) TCP bind hash table entries: 8192 (order: 4, 65536 bytes) TCP: Hash tables configured (established 8192 bind 8192) UDP hash table entries: 512 (order: 2, 16384 bytes) UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) NET: Registered protocol family 1 RPC: Registered named UNIX socket transport module. RPC: Registered udp transport module. RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. Trying to unpack rootfs image as initramfs... Freeing initrd memory: 5580K (c7a8d000 - c8000000) hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available futex hash table entries: 512 (order: 3, 32768 bytes) workingset: timestamp_bits=30 max_order=18 bucket_order=0 jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc. bounce: pool size: 64 pages io scheduler noop registered io scheduler deadline registered io scheduler cfq registered (default) dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330 dma-pl330 f8003000.dmac: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16 xilinx-vdma 43000000.dma: Xilinx AXI VDMA Engine Driver Probed!! xdevcfg f8007000.devcfg: ioremap 0xf8007000 to f086d000 [drm] Initialized brd: module loaded loop: module loaded m25p80 spi0.0: found s25fl128s, expected n25q512a m25p80 spi0.0: s25fl128s (16384 Kbytes) 4 ofpart partitions found on MTD device spi0.0 Creating 4 MTD partitions on "spi0.0": 0x000000000000-0x000000500000 : "boot" 0x000000500000-0x000000520000 : "bootenv" 0x000000520000-0x000000fa0000 : "kernel" 0x000000fa0000-0x000001000000 : "spare" libphy: Fixed MDIO Bus: probed CAN device driver interface libphy: MACB_mii_bus: probed macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 28 (00:0a:35:00:1e:53) RTL8211E Gigabit Ethernet e000b000.etherne:00: attached PHY driver [RTL8211E Gigabit Ethernet] (mii_bus:phy_addr=e000b000.etherne:00, irq=-1) e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k e1000e: Copyright(c) 1999 - 2015 Intel Corporation. ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver ehci-pci: EHCI PCI platform driver usbcore: registered new interface driver usb-storage mousedev: PS/2 mouse device common for all mice i2c /dev entries driver cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 23 xilinx-vtc: probe of 43c10000.v_tc failed with error -2 cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer at f087e000 with timeout 10s EDAC MC: ECC not enabled Xilinx Zynq CpuIdle Driver started sdhci: Secure Digital Host Controller Interface driver sdhci: Copyright(c) Pierre Ossman sdhci-pltfm: SDHCI platform and OF driver helper mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using ADMA ledtrig-cpu: registered to indicate activity on CPUs usbcore: registered new interface driver usbhid usbhid: USB HID core driver NET: Registered protocol family 10 sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver NET: Registered protocol family 17 can: controller area network core (rev 20120528 abi 9) NET: Registered protocol family 29 can: raw protocol (rev 20120528) can: broadcast manager protocol (rev 20161123 t) can: netlink gateway (rev 20130117) max_hops=1 Registering SWP/SWPB emulation handler hctosys: unable to open rtc device (rtc0) of_cfs_init of_cfs_init: OK ALSA device list: No soundcards found. Freeing unused kernel memory: 1024K (c0900000 - c0a00000) mmc0: Problem switching card into high-speed mode! mmc0: new SDXC card at address 0001 mmcblk0: mmc0:0001 SD64G 58.2 GiB mmcblk0: p1 INIT: version 2.88 booting Starting udev udevd[736]: starting version 3.2 random: udevd: uninitialized urandom read (16 bytes read) random: udevd: uninitialized urandom read (16 bytes read) random: udevd: uninitialized urandom read (16 bytes read) udevd[737]: starting eudev-3.2 random: udevd: uninitialized urandom read (16 bytes read) FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck. Populating dev cache random: dd: uninitialized urandom read (512 bytes read) hwclock: can't open '/dev/misc/rtc': No such file or directory Wed May 22 03:58:06 UTC 2019 hwclock: can't open '/dev/misc/rtc': No such file or directory Starting internet superserver: inetd. Running postinst /etc/rpm-postinsts/100-sysvinit-inittab... update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (continuing) Removing any system startup links for run-postinsts ... /etc/rcS.d/S99run-postinsts INIT: Entering runlevel: 5 Configuring network interfaces... IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready udhcpc (v1.24.1) started Sending discover... Sending discover... Sending discover... No lease, forking to background done. Starting Dropbear SSH server: random: dropbearkey: uninitialized urandom read (32 bytes read) Generating key, this may take a while... random: dropbearkey: uninitialized urandom read (32 bytes read) random: dropbearkey: uninitialized urandom read (32 bytes read) Public key portion is: ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAABAQCQZ25idtThpIUIA3l0VqrmPk/CNM/vZzpo4Ks1du8zcbaH8y/6Podg/DOc/WeL3W4ruDerandom: dropbear: uninitialized urandom read (32 bytes read) dR6boCnNyjRVtQuVdCbUx3c+yy/gzH5sWfH+nu6AvTAu+ZaqnZZORAB/zA8Bx1ErLb8nMNxi6lo/PKRBWVyq7Lqo+F2dg5THBdAdznYPTRSiHKs/q/IwtmCfdIw2NjPJ/4HQbLBi3eTwSjo+j7nORE5u9eig4LqPoZOQaw0edrwnbEyntMwUuC8vOpU0GRlYm86xYYc/4IWg4+rS8JfzmiTJ2JNy86NTDSOe1vx8gFFAtPwxM+Dr/KJrB1BD/20CNm2U+m4ZvzE5AEdyX root@test_02 Fingerprint: md5 eb:2b:38:dc:87:cc:a0:36:28:b8:db:e9:64:96:49:4e dropbear. hwclock: can't open '/dev/misc/rtc': No such file or directory Starting syslogd/klogd: done Starting tcf-agent: random: tcf-agent: uninitialized urandom read (16 bytes read) OK PetaLinux 2017.4 test_02 /dev/ttyPS0 test_02 login: root Password: root@test_02:~#
  5. Hi @jpeyron, Thank you very much for your reply. Seriously i am really appreciate it. I have attached together the images of the error i obtained. This is the path where i paste the src files for the LSM9DS1: C:\Users\aliff\Documents\Arduino\libraries\src
  6. Yesterday
  7. Hi @bharaths, Can you provide some more detail on what DDR you are attempting to read from/write to? Are you using the on-board DDR present on the Nexys Video? If you are, the DDR chip is hardwired to a 1.5V bank so you would not able to readily use 1.8V logic with it. If you are using an external DDR chip (presumably DDR2 if you are using 1.8V logic), you could use the FMC connector to facilitate the communication between the LVDS and HSTL logic. Based on this forum thread from Xilinx, you should be able to directly use HSTL and LVDS with AC coupled termination with both receiving the others signals without issues. Let me know if you have any questions. Thanks, JColvin
  8. can LVDS18 drive a diff_HSTL_II_18 in the artix video board? I want to capture 250Mbps DDR data using the FPGA, it is driven by a LVDS driver, can I use diff hstl II in the artix video board @jpeyron
  9. Hi @rosey12, I would recommend you look at online troubleshooting instructions for this as the error does not pertain to an FPGA board of any kind, but your computer; if you are uncertain of how to fix this I would recommend you take your computer to a local repair shop. If you have any questions about Digilent products, please feel free to post them. Thanks, JColvin
  10. hayesjaj

    Zybo-z7-10 Step File

    Thanks, I can manage measuring it. Just hoped I could get around it.
  11. Hi @rprevost453@gmail.com, Homework solutions for the Real Analog materials do exist (though they are all scanned copies of the original solutions made by the creator of the Real Analog materials, so Digilent has not gone through to verify the complete accuracy of all the solutions). However, it is my understanding (I am verifying this) that only verified instructors/teachers will be able to get these solutions in the interest and spirit of helping maintain academic integrity for those are taking this as a course at a university. I do not know the policy of providing solutions to users who are going through the material on their own time without a formal setting, partially because of the reality that there is no real way to determine if this is actually true (or just a student pretending to do this on their own time) outside of the honor system, though again, this is just a guess on my part and not an answer. I have contacted our product manager responsible for the Real Analog material to get her thoughts on this, though they are out of the office this week at a conference, so it may be a few days before I hear back. Thank you, JColvin
  12. Hi @Sduru, I found a xilinx forum that that discusses this issue here. For their project the .project and .cproject files were referencing an obsolete hw_platform that no longer existed. They manually edited the files to the new hw_platform--now the design worked. Did you use the 2018.2 project from the release page here? Did you import the fsbl and pcam_vdma_hdmi from the sdk_appsrc folder in the Zybo-Z7-20-Pcam-5C-2018.2.1 folder? best regards, Jon
  13. Hi @vivekraj2992, We provide board files for our FPGA development boards that include QSPI flash IP configured for the Genesys 2 as shown in the attached screen shot below. Here is a tutorial that will assist with installing the Digilent Board files. best regards, Jon
  14. malexander

    DDR3 input clock source

    There is only a single 100MHz oscillator that's loaded (IC3). The other one (IC2) is not loaded. In order to meet timing the DDR reference clock and DDR system clock have to be in the same column as the bank that contains the DDR3 interface. I don't recall what the thinking was when we included the 12 MHZ USB clock (UCLK) that goes into Bank 15, but you should be able to clock the entire device from pin R2.
  15. jpeyron

    xadc_zynq

    Hi @revathi, Please attach a picture of your XADC wiring to the ZC702 dev board along with a screen shot of the XADC wizard adc setup page. best regards, Jon
  16. Hi @cliftw, Digilent simply sells the Multisim Student Edition (as opposed to licensing it), so we are not able to readily comment with certainty in terms of who is authorized to install and use that particular edition of Multisim, though it is my understanding that the $40 version is a permanent license, so long as the user remains in enrolled in the Academic Institution, as per section 4 of Addendum E in the English version of the National Instruments Software License Agreement, https://www.ni.com/pdf/legal/us/software_license_agreement.pdf. I am not a lawyer, but the language used in National Instruments Software License Agreement makes it seem like to use a Student Edition License the user would need to be in "continuing education classes"; there is apparently an option for a secondary school license (as mentioned in Section 5 of Addendum F of the same license agreement), though I don't know the details of that beyond what is stated there. In terms of the limitations of the software, I am not certain if there is limitation between this particular Multisim for students vs the one for education in general. I do know that the $40 version does not come with a Standard Service Plan (which according to NI's website offers live phone and email support from NI engineers, automatic version updates, access to training and demonstrations, and access to historical versions). I don't know what you are planning to use in your course, but depending on your needs/planned classroom material the free version of Multisim Live from National Instruments may suit your needs. In the end, you will likely need to contact National Instruments for accurate information on the available licensing details. Thank you, JColvin
  17. Hi @Annie B, Welcome to the Digilent Forums! Glad to hear that the terminal commands worked for you. best regards, Jon
  18. jpeyron

    HID protocol on Basys3

    Hi @fpga_babe, Glad to here that your verilog module works! best regards, Jon
  19. jpeyron

    AXI4 and Vivado ILA

    Hi @Sduru, Glad to hear that the problem has been resolved! best regards, Jon
  20. Hi @andre19, Welcome to the Digilent Forums. What ZYNQ development board do you have? I would suggest following the Getting Started with Zynq tutorial along with making sure that you have the Digilent board files installed. Digilent has board files that correctly configures the ZYNQ processor along with the DDR3. Here are the tutorials that we have available Getting Started with the Vivado IP Integrator, Getting Started with Vivado, Installing Vivado and Digilent Board Files and Getting Started with Digilent Pmod IPs. I will pass on your desire for more information on the Zynq core, AXI interconnect, GPIO, proc reset IP Cores to our content team although I believe that currently we do not have the bandwidth to create tutorials for how to edit properties of the Zynq core, AXI interconnect, GPIO and the process reset IP Cores. I would suggest looking through the Zynq-7000 SoC Technical Reference Manual, AXI Interconnect v2.1 LogiCORE IP Product Guide, Processor System Reset Module v5.0 LogiCORE IP Product Guide and AXI GPIO v2.0 LogiCORE IP Product Guide. Xilinx does have a lot of documentation/examples on how to use their IP Cores available from the block design by right clicking on the IP. I would also suggest looking here (if you used the default installation path): " C:\Xilinx\SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers" for examples on how to uses their IP Cores in SDK. The ZYNQ book is also a good source of information as well. If you are still having issues with the Getting Started with Zynq tutorial please attach screen shots of your block design. best regards, Jon
  21. We have both of these and would like to use either of them to measure dc voltages. The problem is we are using robotics to move our sensors so we also need the x,y,z coordinates as well as the voltage read at those coordinates. Is there any way to ask the hardware to report what it is reading? Our software basically positions the sensor in one of 900 possible grid locations and we then measure 2 voltages and compute the current from the voltage drop across a know resistor as well as reading magnetic field strength. If we could put the coordinates into the log perhaps using the digital i/o. We just need a way to indicate the position where we took the readings in the log file somehow. Thanks.
  22. Hi @sambuls, LabVIEW 2014 Home Edition is indeed based on LabVIEW 2014; it includes the Full Development Version of LabVIEW (as opposed to a Student Version of LabVIEW) and is a lifelong (perpetual) license (more details available on the license agreements here and here). I'm not familiar with the Student License so I'm not certain if it's yearly or not; that would be a question for National Instruments rather than Digilent. Unfortunately, there are currently no plans to update LabVIEW 2014 Home Edition to a newer version of LabVIEW, nor do I anticipate there being any plans to do so. Let me know if you have any questions about this. Thank you, JColvin
  23. Hi @aliff saad, Please attach a screen shot of the Arduino IDE errors. Please attach the path of where you have install the LSM9DS1 library. best regards, Jon
  24. jpeyron

    DDR3 input clock source

    Hi @mishu, I believe we added the additional oscillator to help meet timing and eliminated propagation delays with the DDR3. I have reached out to a more experienced engineer to see if they have any additional input as well. best regards, Jon
  25. Hi @PallaviCharupallli, Here is is the resource center for the Zybo Z7. The DMA Audio Demo on the resource center should help with understanding how to use the audio codec. The Digilent board files correctly configure the Zynq processor along with the DDR which is tied directly to the ARM processors. I have attached an image to help visualize the ZYNQ processor architecture. Here is the ZYNQ book that should be helpful with better understanding the DDR and Audio codec. best regards, Jon
  26. Esti.A

    OpenCV and Pcam5-c

    this is what I get as result:
  27. I am also facing the same issue on my device. I am using an ASUS. The main issue is the Asus Error Code 55. Do you have any proper idea to fix this?
  28. Sduru

    AXI4 and Vivado ILA

    Hello Jon, Thanks for your reply. The problem has been solved.
  1. Load more activity