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  2. I edited the question and included more details.
  3. Reading between the lines (apologies if I'm wrong, this is based solely on four sentences you wrote so prove me wrong): I see someone ("need the full speed ...") who'll have a hard time in embedded / FPGA land. For example, what is supposed to sit on the other end of the cable? A driver, yes, but for what protocol and where does that come from? Have you considered Ethernet? It's relatively straightforward for passing generic data and you could use multiple ports for different signals to keep the software simple. UDP is less complex than TCP/IP and will drop excess data (which may be what I want, e.g. when single-stepping code on the other end with a debugger).
  4. Today
  5. Short story: I want to use the Cora board to combined multiple low data rate signals and send it through the USB 2.0 port to a computer. I need the full speed of the USB 2.0. Do I need to buy a license for USB 2.0 from Xilinx to use Vivado for programming it? Is there any example code for running the USB 2.0 you could refer me to? Long story: I have a test setup for a chip that has 128 digitized data outputs about 4Mbps each. I need to transfer these data outputs into a computer with real-time speed. I thought the easiest way is to use an FPGA, combine the 128 data lines, and send them through the USB port. I am looking at the Digilent Cora Z7 board that has the USB 2.0 port on the board. When I was reading Xilinx USB 2.0 manual I noticed the licensing part. Does the license come with the Digilent boards? Do I need to purchase a license to activate the USB IP on Vivado and programming the FPGA? Also, it seems that it is a lot of work to figure out the USB IP and getting it working. Is there any example code for running the USB 2.0 you could refer me to? Would it be easier if I use Ethernet or something else?
  6. Yesterday
  7. Hello @mustafasei, It looks like from your screenshot you did not create a string constant but are still using the VISA Resources drop-down since the correct USB device for the Arduino will not appear on the list. I imagine you are using a cdc-acm USB serial device (such as the Arduino Uno or Leonardo) so there was a bug in VISA that got an update though I don't know if it was ever formally rolled out, but this LabVIEW MakerHub thread discusses this. You might also use "dmesg | grep tty" as a way to find out the attached devices rather than listing everything. Thanks, JColvinn
  8. jpeyron

    Webserver using Zybo Z7

    Hi @sgandhi, I did a quick internet search for "create a FAT image on linux" and this blog looks like it should be helpful. I have not worked with this example. I would suggest reaching out to Xilinx support about the LWiP examples since they would have experience with the webserver example. best regards, Jon
  9. sgandhi

    Webserver using Zybo Z7

    Hello @jpeyron, I was looking into some examples in the \lwip202....\examples and found one lwip webserver example that uses index.htm file present in FS! Now when I follow the readme.txt file for directions to execute the example, I see some steps as follows: ********************************************************************** Creating FAT image on Linux --------------------------- This requires root (sudo) access on the Linux host Following commands can be used on terminal to create FAT image to be used with webserver application: # create image file of 3MB dd if=/dev/zero of=example.img bs=512 count=6144 # format image with FAT /sbin/mkfs.vfat example.img # mount it mkdir /tmp/fs sudo mount -t vfat -o loop,rw example.img /tmp/fs/ # copy your webpages sudo cp -r webpages_dir/* /tmp/fs/ sudo umount /tmp/fs *************************************************************** And then it tells to run the application... I just tried to run the application w/o creating FAT image, which is obvious to give me the errors!! In order for the webserver to gain access to index.htm, the file needs to be present at the specific location. Is that why we create a FAT image on linux??? Also, the steps in readme.txt tells me to runs those commands on the terminal... How do I start with this? Is it talking about the sdk terminal? As per the directions, I added all the necessary source files and I also included the BSP settings as mentioned! Next step is to create a FAT image on linux... I am wondering how do I start with this! Thanks, Shyama.
  10. Hi @jpeyron Yes I folow the instructions on you tube and I can see the port number for arduino in the device manager and I put the same port in .vi when I connect the arduino directlly on PC USB port but. my problem is when I connect the arduino on raspberry pi3 USB port what will be the port name because in the thread below some says it is (ex /dev/ttyUSB0 andsome says it must be (ASRL2::INSTR ) and other say (/dev/ttyACM0) or (/dev/ttyACM1) I have used this command (ls /dev/tty*) on RPI and I got ports as picture below but still not work when i put it in the .vi and give me the same error of 5006 in my previous post. any idea please ?
  11. Hi @mustafasei, Did you follow this YouTube Video when trying to get the LINX project working? Does the Arduino show up in the device manager? Did you select the com port for the Arduino you are using in the LINX device settings? best regards. Jon
  12. Hi @Mats, The co-worker in question is out of the office, so unfortunately I do not expect to hear back from them until next week. Thanks, JColvin
  13. Hi @PhilG, 1. That is accurate; the aggregate input is divided based on the number of channels that are being read, so if you read all 8 channels, the sample rate ends up being 62.5 kS/s per channel (I think you missed a decimal point there). However, it is a bit more nuanced as the embedded ADC within the on-board MZ chip limits how channels are read. What I mean by this is if you choose to read only channels 3 and 7, the sample rate will be limited to 71.43 kS/s because the embedded ADC (by internal design that isn't changeable by a register setting) will read channels 1 through the last channel enabled (in this case channel 7) even if the in-between channels are not enabled. So if you want to read multiple channels, make sure they are on the lower analog channel numbers to minimize the impact to sample rate. A single channel enabled (even if it is channel 7) will still keep a 500 kS/s sample rate though. 2. It should have a max logging rate of 500 kS/s; I have corrected that bit of detail on the OpenLogger Resource Center, let me know if you see that elsewhere in the documentation. Originally, it was only going to be 400 kS/s but the firmware was streamlined to make 500 kS/s achievable. 3. Well, they aren't powered by Digital to Analog chips directly (it's done through through discrete components), which to be fair is all DAC's are made out of anyway. But I think the idea that the they have their own op-amps to produce the DC outputs (IC8 on page 6 of the schematic, makes it fair to call them power supplies. They are not beefy power supply lines, but do provide more current (50 mA) than a typical digital-to-analog converter (at least as far as I know). Let me know if you have any questions about this. Thanks, JColvin
  14. As promised I ported my PC test application to run on Linux Mint 18 64-bit. The platform is an Up Squared SBC with a Pentium N4200 and 8 GB of memory. This platform is still within a 15W power envelope useful for embedded projects. My Windows PC development application was C++ though the only C++ functionality was using streams for file IO. I had a devilish time trying to port it to Mint so I ended up just making it into a C program and having no file IO. Using the DE0 Nano I was able to send data up and down error free at average data transfer rates > 40 MB/s consistently. Curiously, past 256KB data payloads I observed download rates fall below 15 MB/s though upload rates stayed above 40 MB/s. This is definitely not consistent with what my experience has been with PC platforms. As all application data storage is kept in memory I assume that this is a bottleneck on this board. My FPGA design counts 60 MHz clocks the the state machine spends in the data download and upload states so the rates are extremely accurate, from the point of view of the FPGA. Timing and other instrumentation is reported to the host application in the Status Sector for every transaction. From the point of view of the SBC there are a lot of factors diminishing those rates. Anyway, I've shown that it's possible to cheaply combine an FPGA and a cheap SBC on at least one platform with a relatively high speed interface. Overall performance suffers from platform dependent factors; so experimenters should not make assumptions about expected performance for a particular application.
  15. jpeyron


    Hi @andre19, I responded to your other thread here. best regards, Jon
  16. Hi @andre19, On the Zedboard the DDR is tied directly to the ZYNQ processor. Here is a Xilinx WIKI that discusses this topic. I have not used microblaze on a ZYNQ FPGA. Here is a that might be helpful as well. best regards, Jon
  17. Hi! Hi @jpeyron Nowadays i have get Zedboard) and decided to try on it soft core MicroBlaze. I created project and add IP cores in analogy with my experiment with Arty A7-35. In Arty DDR3 has been added avtomation, in Zedboard i written adreses manual in XDC for each pins : It is in .XDC file: #MEMORY DDR # ddr3_dq_0 set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[0] }]; set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[1] }]; set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[2] }]; set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[3] }]; set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[4] }]; set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[5] }]; set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[6] }]; set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[7] }]; set_property -dict { PACKAGE_PIN AA22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[8] }]; set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[9] }]; set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[10] }]; set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[11] }]; set_property -dict { PACKAGE_PIN AB19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[12] }]; set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[13] }]; set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[14] }]; set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[15] }]; set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_p_0[0] }]; set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_p_0[1] }]; set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_n_0[0] }]; set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_n_0[1] }]; #ddr3_addr_0 set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[0] }]; set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[1] }]; set_property -dict { PACKAGE_PIN AB16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[2] }]; set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[3] }]; set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[4] }]; set_property -dict { PACKAGE_PIN AA17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[5] }]; set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[6] }]; set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[7] }]; set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[8] }]; set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[9] }]; set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[10] }]; set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[11] }]; set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[12] }]; set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[13] }]; set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[14] }]; #ddr3_ba_0 set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ba_0[0] }]; set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ba_0[1] }]; set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ba_0[2] }]; #ddr3_ras_n_0 set_property -dict { PACKAGE_PIN AA14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ras_n_0 }]; set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_cas_n_0 }]; #ddr3_we_n_0 set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_we_n_0 }]; #ddr3_reset_n_0 set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_reset_n_0 }]; set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ck_p_0[0] }]; set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ck_n_0[0] }]; set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_cke_0[0] }]; set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dm_0[0] }]; set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dm_0[1] }]; #ddr3_odt_0 set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_odt_0[0] }]; # DDR3 STOP 1) After start generating Bitstream i get ERROR: [DRC MDRV-1] Multiple Driver Nets: Net system_i/mig_7series_0/u_system_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/write_buffer.wr_buf_out_data_reg[112]_0[0] has multiple drivers: system_i/mig_7series_0/u_system_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/mem_reg_0_15_0_5_i_4/O, and system_i/mig_7series_0/u_system_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/mem_reg_0_15_0_5_i_5/O. DRC report in Syntesys are next: and 2) Next problem place: InOutTerm #1 IO Standard LVCMOS33 does not support IN_TERM, but I/O port ddr3_dq_0[0] has IN_TERM set to UNTUNED_SPLIT_50. What is mean @IO Standard LVCMOS33 does not support IN_TERM@ ??? How to fix "1)" and "2)" ??? Best regards.
  18. Hi Thank you for your responding I check the thread and I dont know what the port name must I select in my case . please see the screenshot for the error which I have any advice please ?
  19. Hi @reddish Use the amplitude setting for faster response. Initialize like: - FDwfAnalogOutEnableSet - FDwfAnalogOutIdleSet DwfAnalogOutIdleInitial - FDwfAnalogOutFunctionSet funcSquare To change the output level use: - FDwfAnalogOutAmplitudeSet See the related post:
  20. Hi @Sbacica, I took a look at the Digilent Digital WaveForms example (Digilent_WaveForms_Digital (DIG).vi), and when using the Analog Discovery 2 it is correctly providing a logic high voltage of 3.3V as verified by a multimeter and an LED. I think the pins might be tristated when the Analog Discovery 2 is initialized and the outputs aren't configured, but I don't know for certain. Thanks, JColvin
  21. Hello, i am trying to use an Analog Discovery 2 in a Python-based control system. Specifically, I want to use its first analog output channel to set a control voltage, based on some (independent) sensor, approximately like this: CHANNEL1 = 0 while True: x = get_sensor_value() v = 0.1 * (x - 2.0) analog_discovery.setvoltage(CHANNEL1, v) I want to do this as fast as possible; and I want the transition of the AD's channel 1 voltage to be glitchless and as-fast-as-possible. I tried two approaches: - Keeping the channel IDLE, and manipulating the offset of the Carrier node: it takes about 10 ms for the analog out channel to reach the new offset value when I make a 1V jump. - Put the channel in DC mode, and manipulate the offset: this also takes ~ 10 ms for the channel to reach the new value. I would like to make the jumps a lot faster. Clearly if I could precalculate the waveform the AD is fully capable of delivering the required bandwidth, but is there a way to improve the performance when the value needs to be calculated on-the-fly, on an attached PC?
  22. Hi @Chouchene, You have a private message. Regards, Bianca
  23. Good morning, My similar problem was solved replacing USB-RS232 dongle with the one supporting high speed, specifically, Silicon Labs part number CP2102N-EK. It should be mentioned that Zynq PS side was utilized for RS-232 at 921600 bit/s without flow control and parity. It worked flawlessly since for tw-way communication and sending large files. Hope it'll help!
  24. Hello, My JTAG HS2 firmware accidentally erased while i was trying to program another FTDI device connected to the PC and the programmer is not detected anymore by Vivado. Please i need your help to recover it Thanks.
  25. Hi @Erkang The Analog Discovery Studio should be supported by MatLab 2018a. The ADS has identical device ID to AD2, only the device variant is different. The DAQ toolbox support package filters the devices based on ID. That is why MatLab 2013a supported only the AD(1). In 2018a AD2 was added. I don't think MatLab support looks for variant ID, so it should work with ADS too. See related post:
  26. Thank you very much, @attila; I guess for the first experiment we can keep it simple and neglect temporal jitter/drift during time scales < 10 µs.
  27. Hi @JColvin @rprr It looks like all the USB 2/3 ports of RPi4B are working reliably with AD2. I have updated the post:
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