All Activity

This stream auto-updates     

  1. Past hour
  2. well, by default your signal is between 0 V and Vref. The opamp circuit has a gain of 2 (range 0.. 2 VRef) but subtracts a constant VRef (range now -VRef..Vref). It'll just shift the waveform on the scope, and double its AC magnitude.
  3. @Boris_S Since you are using Windows it might be worth your time to try an experiment. xc6lx45 has posted his awesome busbridge3 demo in the Project Vault. I have created an executable that runs on my WIn7 computer using the source code and SharpDevelop compiler. If, as I suspect, the issue is completely a hardware one then you shouldn't be able to run the code and configure your board. I made slight modifications to the source so that I could confirm the configuration step. Read the project postings. Once I resolved some basic C# issues I had no problem running the executable with either of my two boards ( again, I've not had issues programming them ). This project does not require a separate JTAG FPGA configuration application to be running. Download the project and read through the source code just because it's a great tutorial for anyone who hasn't tried creating a PC application that configures and interacts with an FPGA board before. When I first ran into the problem it certainly 'smelled' like a software or driver issue; Vivado Hardware Manager doesn't play nice with other applications, including the Adept tool for Windows which I generally favor for configuring Xilinx FPGA boards. Since I've been able to use my boards with a simple work-around I haven't allocated the time to doing what Digilent should have done and resolved long ago; that is fix this once and for all. The FTDI JTAG and UART should be enumerated as separate endpoints and not interfere with each other. I don't have a USB bus analyzer ( Digilent most certainly has no excuse for not investing in one ) so ferreting out the source of OS disconnects is more work than I want to do. FTDI doesn't provide the level of debugging support that Cypress does for their USB devices so tracking down issues involving a lot of software and hardware elements is non-trivial. Even so, there's simply no excuse for these reoccurring customer complaints not being aggressively addressed and resolved by the vendor.
  4. Today
  5. I have just started hitting this in the past week (Ubuntu 18.10) with my Cmod A7 35T. It was hit and miss before then, now I can only connect perhaps 2% of the time. I have two other boards (Basys3 and Nexus Video) and I am using the same usb cables that work 100% of the time with them. But have tried multiple cables. Here are my observations (for what they are worth) and even a guess at what the problem is. Using a combination of 'sudo lsusb' and looking at the logging from 'hw_server' I can see that the A7 appears as a JTAG Digilent devices, then drop out before being seen as a FTDI driver on the same physical device. It seems to me that the A7 is booting, my machine briefly recognises it as a JTAG device, then (*sadly) the A7 starts it's demo app, which appears to tear down the JTAG port so it can communicate with the host via the UART. At this point the hw_server thinks it has lost the JTAG/USB and so no longer sees the device, so drops it. I see the UART drop then reappear in cycles from this point out. If I have the Vivado UI up (usuallly I avoid). I will see multiple dialogs stacked, as it see's, then loses connection with the device. I think that when I am lucky (the 2% of the time!) I am hitting the hw_server just as the device is being seen for the first time, or in one of these 'cycles'. I really think that it it was not for the demo app trying to use the UART my connection would be stable. So I would love to know how to disable/delete the demo app. I think after that, I would be in good shape. Maybe these observations might help someone with more experience to determine a plan of action.
  6. Hi Zygot, I really wanted to thank you for taking the time to provide such a detailed answer for me, its hugely appreciated ­čśÇ I have everything working now and your tool is absolutely incredible. For years I've been relying on a bunch of LED's to try and figure out what was going on in my designs. This tool is like replacing a stick with a machine gun. Its amazing! I was basically over thinking things and had made some changes to the TB which broke it. After your note, I removed my changes, fired up the TB which worked first time of course and then was able to build another TB which better tested my IO. The other thing that had me stumped for a while is that your TB code has another UART in it and I just couldn't figure what that was doing there until I had the preverbal 'light bulb moment' and thought how stupid I was being I'm actually on ISE 14.5 but haven't touched it for a long while because I only have an old Spartan 3A Starter Kit which is several years old and the USB drivers stopped working under Windows 10. Thanks Xilinx for abandoning us all btw ! Anyway, I finally managed to create a Windows 10 driver workaround and was therefore able to go back to one of my old projects which is the conversion of an ancient arcade machine to FPGA - The arcade game Gorf from 1981. One major part of the puzzle was getting a circa 1970's Votrax SC01 speech synthesizer chip interfaced to the FPGA. Previously I'd managed to do this with an Arduino by just simply building a circuit and sending it the correct sequence of bytes. What I really wanted to do however was to use my FPGA to do the same thing. I've been building or should I say tinkering with (for years) a full board reproduction of the machine which consists of several custom chips and a Z80 CPU. The problem was that although I could see what I thought was the right data coming from the machine by feeding it to the LED's on my board, I didn't know if this was just garbage or the Z80 sending the speech synthesizer the correct data. I ran the Debugger at both 115,200 and 9,600 baud with a 50Khz clock and although I've not yet built the circuitry to interface the FPGA to the Votrax, I was able send those bytes I captured with your UART Debugger and simply edit the data in to the correct format and paste it in to my Arduino sketch to test. Low and behold, there was a talking Gorf arcade machine straight out of 1984, truly awesome! Zygot - This is a really great tool. Most of the UARTS I've tried tie the input to the output of your keyboard and echo what's typed straight back to the user. That's all well and good, but when there is no input that sync's up with the output, its quite difficult (at least for me) to just get the output part working. I will be able to use this tool in loads of projects, I just wanted to say thank you once again ­čĹŹ
  7. Hi, Currently I'm working on a project in which I want to transfer 1MB data from PS to PL using BRAM using custom IP. I receive correct data at PL whenever I send data less then 32 bits from PS to PL but when I send more bits from PS, I'm unable to receive even a single bit. is there any clock issue as I'm using clock of PS for my custom IP or their is any other problem? Regards, Sami
  8. Yesterday
  9. @Boris_S I've written about this so much that I've been avoiding responding to posts such as yours any more. I decided to add my 2 cents to your thread because your experience is very similar to mine. For my older 2 CMOD-A35T boards I've never had an issue configuring the CMOD-A35T but do have USB disconnect issues with Vivado Hardware Manager if I try to use the ILA for some time. I have a drawer full of cables and none of them make a difference. I find the board useful if I use an external TTL USB UART attached to 2 IO pins. You obviously can't do that if you can't even configure the FPGA device. Digilent is set on blaming the problem on cables... yet they don't sell the board with any or guarantee operation with any known vendors cable even after a few years of complaints. You are correct that this is the only FPGA board that Digilent ( or anyone else that I know of ) makes with this problem; and Digilent has made a lot of boards with roughly the same programming interface over the past 5 years or so. My personal suspicion is that the particular FTDI device used on this board ( the newer cheaper ones have fewer power and ground pins), pcb layout decisions, and possibly the way that whatever makes their interface proprietary is different for this board is causing the issue but I can't prove that and frankly it's not worth my time to try. Neither you nor I can make Digilent take any particular action with regard to these boards but it is clearly not doing anything positive for their reputation ( I sometimes wonder if they even care about reputation ). Since they are cheap, if I were the vendor, I'd re-spin the board, test the JTAG interface exhaustively, and sell the modules with a mated cable. I suspect that the board needs a different stackup and less component density and a JTAG re-design. Making customers eat the cost of a poor design just isn't good business if you want to engender good will. There have been customers that support Digilent's claim that a different USB cable makes the problems disappear but, as you and I know, not all of us customers can verify this. I happen to think that if a customer can't use a new board with known design problems a more liberal replacement policy should be in order... the vendor can figure out what's going on working with the returns. It's problematic that the same board and cut & paste copies of newer versions are being sold without a fix. Perhaps Digilent doesn't think that the cost merits testing product but for their customers the cost is signifiant, especially when the board is unusable. I know what I do when a vendor has a habit of not treating me well... I use a different vendor. The Terasic DE0 Nano is about the same cost but comes with a USB cable and has more IO pins in a slightly larger form factor but is still quite usable for attaching to a custom board that I design. It doesn't use an Artix device but for what these embeddable modules are good at has served me quite well. I've designed a few dozen boards that have integrated either the 2 CMOD-A735T or the DE0-Nano as a component over the past couple of years. If Digilent were willing to replace your board, given the known issues, then I'd try that for the modest cost of shipping but if not I certainly wouldn't throw more money at a different one hoping for a different outcome. There are a few vendors offering similar modules but I only have experience with the two that I've mentioned. Trenz makes a few similar FPGA boards but I've never used any so I can't offer any opinions about them.
  10. @Boris_S Hi, I didn't even mean you should rig up a test cable. It would, most likely, show when the FTDI chip goes into shutdown, but that's it (it would be more useful if you could compare with a known-good board, but I think that's not the case) Of course, there is always the possibility of broken hardware. If I had to make the board work, I'd try to supply 5 V externally, with e.g. 47┬Á tantalum cap in parallel. There is one corner pin for external supply. I suspect it will not reach the FTDI chip directly (D1 in the schematic), but may help to suppress current spikes from the FPGA.
  11. I am tring ti install waveforms on Ubuntu 18.04 on a Lenovo 64bit laptop. I downloaded and installed adept2.19.2 from the digilent website. Then I tried to install waveforms , it stalled with a message "Error dependencies not satisfiable digilent.adept.runtime (=> 2.17.1). It seems like it should install - what gives ?
  12. I am tring ti install waveforms on Ubuntu 18.04 on a Lenovo 64bit laptop. I downloaded and installed adept2.19.2 from the digilent website. Then I tried to install waveforms , it stalled with a message "Error dependencies not satisfiable digilent.adept.runtime (=> 2.17.1). It seems like it should install - what gives ?
  13. eray

    SOUNDS WITH VHDL

    Hello everyone, I am pretty new to VHDL and need some help! My project is air-drumming with gyroscopes. I found a code to connect MPU6050 with BASYS3. However, I need to implement drum sounds (Bass, Hi-Hat and Snare). my question is: How can I obtain "drum" sounds by using VHDL?
  14. Let me offer a suggestion to all newbies, regardless of how smart you are, before trying to do FPGA development. Read all of the user guides for the FPGA device resources that you are likely to be using. These will include the SelectIO, Clocking, CLB , and memory guides at a minimum. [edit] also read the AC switching part of the device data sheet. Like it or not what you are doing in FPGA development is digital design and you need to have a sense of how design decisions affect timing. Read the Vivado user guides for design entry, constraints, simulation, timing closure, and debugging. Understand that even though various Zynq devices are based on certain FPGA families the documentation tends to be unique for these devices. You will be overwhelmed with all of the 'basic' information. Spend a week or so running though all of the basic documentation, spending more time on specific topics each read-through. The object isn't to memorize or understand everything but to get a general feel for how Xilinx presents its information. You can also learn stuff that you will miss in specific IP documentation by using the simulation, but only if you are careful to read all of the simulator messages. This is complicated stuff and the tools, even when they behave as described in the reference material is even more complicated. The purpose of doing this is to get a general feel for how the devices work and specific use limitations and how the tools work. It will take a year or so before you start becoming competent at it if you are a normal human.
  15. @askhunter Tip if you want to notify someone that you are responding to a post type @and the first few letters of their username. A selection of usernames will appear in a popup window to choose from. If you just type @ and the whole name you won't get the desired result. I confess that I'm not an expert on using the features of this site but I did figure out this one. As to understanding all of the Xilinx documentation what yo are doing is correct. Speed-read though a document to get a general sense of what's being presented and don't worry about the things that you don't grasp. Just being familiar with what information is where will help with a specific question later. The DSP48E is a very complicated piece of hardware. You only understand how complicated by trying to instantiate it as a UNISIM component to implement a particular algorithm. I've done this and it take time. You understand by doing; one step at a time. In your case I'm assuming that you are starting with someone else's code and trying to modify it. This approach takes a difficult task and turns it into an extremely difficult task. [edit] Vivado uses the multipliers in a seamless way when you specify a multiply in your HDL code. It takes care of a lot of little details, such as that the multipliers are signed 18-bit. There are a LOT of options with the DSP48E blocks. Once you start making decisions for Vivado, by say, using the use_dsp attribute in your code you are taking on responsibility for more of those details... so you had better understand how the DSP48E blocks work. Trust me, even after you have figured out all of the necessary behaviors of the DSP48E blocks it doesn't get easier as you will have to contend with routing issues that might dramatically reduce your data rates. This is a general rule for using FPGA device resources. You can use the IP wizards to help construct a component that's useful for your needs or do it yourself in HDL code and assume the responsibility for getting all of the details and constraints right.
  16. thank you for interesting. Actually, I read this documentation but this has so many detail and i'am very newbie in fpga. so i didn't understand mostly. even so I'll read it again.
  17. @askhunter I suggest that you read UG479 to see what the DSP48E blocks do. Then read UG901 to see what the use_dsp attributes do. Reading the recipe doesn't always help improve the cooking but it never hurts. A long time ago having signed multipliers in hardware was a big deal for FPGA developers. For the past decade or so these have become integrated into more complicated and useful 'DSP' blocks. The DSP nomenclature is a holdover from the days, long before IEEE floating point hardware was available, when having a fast multiplier in hardware meant that you could do some fun stuff in a micro-controller that you couldn't do with software routines. These days the lines are blurry. Most FPGA devices have some really fast hardware features, block ram and DSP blocks ( depending on how they are used ) being the most useful for grinding out mathematical algorithms. By the way, the DSP blocks can be useful for more than multiply-add operations.
  18. Hello friends, i have been build HelloWorld Linux application using Xilinx SDK cross compliler=C:\Xilinx\SDK\2017.4\gnu\aarch32\nt\gcc-arm-linux-gnueabi\bin\arm-linux-gnueabihf- after creating hello.elf .. I copy this file into sd card and then switch on my zybo board containing sd card (hello.elf) then after running Linux over zybo zynq soc, I tried to run hello.elf, but I am getting following error... zynq> hello.elf - /bin/ash: hello.elf: not found why it is saying not found ...what is meant by that... please reply if you have any solution regarding this issue. thanks regards Arjun
  19. first : without dsp attribute - attribute use_dsp of sum : signal is "no"; second image : with dsp attribute - attribute use_dsp of sum : signal is "yes";
  20. Hi, I try to simple multiplication, but when i use dsp attribute then i got different result in simulation .what is the reason of this? without dsp attribute - attribute use_dsp of sum : signal is "no"; with dsp attribute - attribute use_dsp of sum : signal is "yes"; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.types.all; entity convolution2d is port ( clk, rst : in std_logic; start : in std_logic; window : in frame9; done : out std_logic; pixel : out pixel8 ); end convolution2d; architecture rtl of convolution2d is constant mask : mask_9 := (-1, -1, -1, -1, 8, -1, -1, -1, -1); signal sum : integer:=0; attribute use_dsp : string; attribute use_dsp of sum : signal is "yes"; begin -- iterative way process(clk) is --variable tick : std_logic:='0'; begin done<='0'; if rising_edge(clk) then if start = '1' then sum <= 0; for n in 0 to 2 loop for k in 0 to 2 loop sum <= sum + (to_integer(unsigned(window(n*3 + k))) * mask(n*3 + k)); end loop; end loop; done<='1'; pixel <= std_logic_vector(to_unsigned(sum, 8)); end if; end if; end process; end rtl; "
  21. I am using Xlinux ZYBO-7000 board with Debian Jessie Linux, the FPGA programming is done by my professor. as part of my project I have to display my PyQt5 application via HDMI, in order to display pyqt45 application via HDMI, I have to point PyQt5 application to framebuffer /dev/fb0. but it gives me "cannot connect to X server" error. I had used qt designer to create my GUI application in ubuntu16.4 and then I copy my project into ZYBO (Debian-Jessie). but then I find out that I have to compile pyqt5 with linuxfb then it will display GUI into framebuffer. but I do not know how to do it? I search on the internet but I could not found a solution. can anyone please suggest me so tutorial or something regarding how to run the pyqt5 application in zybo 7000?
  22. is it possible to run Application by writing it in SDK on video passthorugh/HDMI demo given
  23. Mukul

    Data compression

    I'm working on Data compression so studying different code techniques such as follows to implement on zybo board Golomb coding special case Rice code compression Huffman code Arithmetic code And finally Dynamic Markov compression I selected DMC because it is dynamic in nature and work well with sensor (as input).Here is the problem that i don't know exactly markov´╗┐´╗┐´╗┐ compression is good for this or not.´╗┐ Also when i study the DMC it's algorithm is similar to sequence detector (so are they same?). Secondly in video processing/image processing ´╗┐or in general which tech. Is used in Data ´╗┐´╗┐compression´╗┐.
  24. @SGY What you will get is a pretty nice, somewhat elderly but very useful FPGA development hardware. You also get the Zedboard community and all of its postings. There are numerous tutorials written expressly for a version of this board. I highlighted 'a version' because you need to know that there were a few important hardware changes in the life of the board. Because it's older most of the tutorials were written for long gone versions of ISE or Vivado and might be difficult to follow as the Vivado user experience changes with every new version. As to RTL code you can find some but since this is a ZYNQ product the emphasis is on the ARM development. I've had the C version of the board for quite a while and still make use of it when I need a Zynq solution. The Zedboard contributions are at this time mostly old at this time so you will have to learn the whole Zynq development ecosystem. Once you've done a few PL designs it will get easier. Zygot's hint for the day is to let Vivado create a Zynq HDL toplevel source file in a project that you, not Vivado, manage. You can instantiate that into your own toplevel design with all of the PL magic that you can conjure up. You'll have to trust me that this is the far easier way to go if you want to do FPGA development with ARM support. Your opinion is more important (to you) than mine however...
  25. @Reggs Thanks for posting your question. My first suggestion is that you figure out how to use the testbench in Vivado. You can create a special Vivado project using just the UART_DEBUGGER,vhd and YASUTX.vhd source files. It doesn't matter what device you use. Just make sure to add the T_* testbench files as simulation sources after the project has been created. Both Vivado and ISE mark source files as implementation or simulation or both and it's important that VIvado knows which are which. All of this was easier in ISE. ( in a lot of ways Vivado is a really badly conceived software application ) In Vivado Simulation Settings you can select which of the testbenches you want to simulate. I strongly suggest that you get to know how to do simulation in Vivado or ISE ( simulation is actually easier in ISE ). None of the code uses a particular feature of any particular FPGA device so you could use the free version of ModelSim that comes with Quartus to run the simulations as well. If you really can't get the simulation running let's work on that first. Once you have the simulator working it will, by default, show you the toplevel (in this case the testbench) signals. You can then add any or all of the lower level code in the hierarchy to the simulation waveform viewer. Just understand that the more signal you show and the finer the time resolution the longer the simulation takes. For this code what takes time is the slow uart output. You did read the commentary at the top of the source files, right? You should be able to use a 50 MHz clk and get out a message at a 115200 baud rate. I've used this component often and with a few baud rates ( I haven't tested it exhaustively at lots of different baud rates ). The idea is to send a string of hex numbers in ascii form so that you can read the value of a register in your code at a particular event or time. This particular tool isn't meant to send text, only hex numbers in ascii format. The number of hex digits displayed in the terminal should match your DATA_CHARS assignment. Are you sure that the clock that drives the UART_DEBUGGER matches the generic CLK_RATE? From what you depict as your output it looks as though your problem is not with baud rates ( clearly there are recognizable characters being printed ) but in using the data_write_stb and busy signals. data_write_stb should not be asserted until after busy is de-asserted (low). The busy signal indicates that the YASUTX transmitter is in the process of sending a set of characters and not ready for another set. Make sure to strobe data_write_stb for only 1 'clk' clock period. In your code you will decide what conditions or event starts a message. It should be obvious that any baud rate is going to be pretty slow relative to whatever is going on in your design at 50 MHz so you need to make logic to select the instant where your data is captured and sent. By the way you can capture multiple data states in successive clocks by putting a fifo between your data and the UART_DEBUGGER; that way you can feed say, 1000, snapshots of your data to the fifo and let the UART_DEBUGGER read them at its own slow uart time frame. I have an example of this lying around somewhere around here... Oh, if you look at S3_PGMR_D.vhd in the S3_PROGRAMMER_R1.zip source in the S3 Starter Board Programmer project that I've posted here in the Project Vault you can see an example of using a FIFO with UART_DEBUGGER. You may wonder why you'd want to print out data faster than you can read it but if your use Putty as your terminal it can be set up to fork all incoming and outgoing text to a file so that you can read it later... how cool is that? Once you get the code simulated you will quickly figure out what's going on. Hopefully, you will be encouraged to start on creating your own debugging IP. You can, with a bit of skill and practice make better and more useful debugging tools than Vivado provides. [edit] Xilinx has a number of helpful guides to using the Vivado simulator in tutorial, reference manual or user guide formats. There's a lot of information about the devices and tools to digest but you don't have to understand everything in order to learn enough to do a specific thing. Being able to use the Documentation Navigator and material is key to success with FPGA development.
  26. Last week
  27. want to buy ZEDBOARD ZYNQ-7000 ARM/FPGA SOC. Will RTL code provided with the board? what do i expect to get? Thanks,
  28. Dear Sir/Madam, I am trying to create a single pulse using the wavegen in labview but couldn't find the subVIs in the DigilentWF library. I was able to use the Waveform software to create a single pulse. Attached are the pictures. Is there anyone that can help to shed some lights on how to achieve that? Much appreciated.
  1. Load more activity