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  1. Past hour
  2. I can now answer my own question. It is not a 'nice' solution but it works and may help others. The following would seem to be the logical way to change to using the Alt CS on this LCD shield but this fails. bool MTDS::begin() { // return begin(pinMtdsSelStd, frqMtdsSpiDefault); return begin(pinMtdsSelAlt, frqMtdsSpiDefault); // My change for alternate pin selection } In MtdsHal.h there is code to define the two IO pins used for CS, pinMtdsSelStd and pinMtdsSelAlt, for various types of hardware. Following all these #'define if elses, just force the library to always use the Arduino Uno's IO pin 8 by redefining everything the ' if elses' have setup. #define pinMtdsSelAlt 8 #define pinMtdsSelStd 8 Do not bother alter the MTDS::begin() code.
  3. Today
  4. Dear JColvin, thanks for your answer. I am not sure I completely understand your answer (I also guess a part is missing). What surprises me is that, when I connect the power to the board, it doesn't start the bootloader automatically and I need to press the PROG botton. This is a problem because, in case of power failure, the system will not restart running automatically and I will have to press the PROG botton again. Is it normal? Thanks, Lorenzo
  5. Hello @rcjhy8, Each pmod pin can be individually controlled by using the axi gpio core. This core provides a general purpose input/output interface to the AXI Interface. Trough the AXI interface you can easily control the state of your led. If you want a dynamic control, you have to implement a command parser on a serial terminal, such as putty or teraterm. Best Regards, Bogdan Vanca
  6. A previous thread noted use on the Arduino Mega seemed imposable because there is no obvious easy way to change the CS pin in the software libraries. My attempts to find what code needs changing and the attempts in the previous threads attempts, result in the display performing a short flash and then going black/dead. I do need to solve this as Digilents DMM card that I also need in my project uses the same CS as this LCD. This previous thread had an official response of 'oops perhaps it is not Arduino Mega compatible we had better take it out of the brochure web pages'.
  7. Hi @enliteneer You can use the ROM logic in Pattern Generator for such purpose, see:
  8. On the other hand, Arduino programming also allows you to provide C / C++ code. This is not the best way to write your C code, still you should know that you can do it.
  9. @malexander Thanks for reply. XC3S400 and XCF02S are powered at 3.3V, while JTAG powered at 5V. There is no any buffer/level translator in this circuitry. To configure only FPGA we shorted 1 and 2 of J13. When 2 and 3 of J13 shorted at that time FPGA and PROM both comes into picture. It’s my two observations: under ISE impact through parallel port on XP, there is an option to bypass FPGA & select PROM which apparently ensures that code related PROM & stays there. While under Adept HS1 you can’t bypass FPGA but can select PROM in that case it seems that bit stream comes through PROM yet doesn’t stay there as bypass option is not seen on screen. Is it hidden under selection procedure itself?
  10. asmi

    SdSOC tools

    It looks like Xilinx went all-Vitis. It replaces SDK, SDSoC and SDAccel. See here: https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis.html
  11. Starting from 2019.2, SDK isn't included with Vivado anymore, but it's now a part of "Vitis Unified Software Platform".
  12. It also depends on what you need to be able to do. If you're needing to debug your code, the only option are those mentioned. The Snap debugger is a very inexpensive option ($15, and discounts are pretty regular). If you don't need to debug, you would have to use a linker script to make the program look like something the MPIDE or Arduino IDE produces, but then you have to be able to download it through the bootloader.
  13. @D@n ---- thanks Dan! Just before your last post, I was already looking at your tutorial site and bookmarked the link - in preparation to work through those tutorials! It is a great tutorial site. I'm definitely going to be following your teachings from there. I've been looking at the nice details there, so I'm already one of your students. Greatly appreciated! I totally agree that learning to debug FPGA will be hugely beneficial. I will definitely enjoy working through the tutorial, and read your blogs too. Thanks again D@n! Once again - much appreciated!
  14. I am running into an issue following the Arty web server demo. After importing the project I get some build failure messages. I have tried cleaning the project and replacing xadapter.c file with no success on building the project. Here is the SDK window after I import the project into xilinx SDK 2019.1. Any help would be greatly appreciated.
  15. Yesterday
  16. Hi @brunomaximom, You would still be able to do C programming from MPLAB X; the catch is that you need additional hardware in order to do this as @Cristian.Fatu mentioned. Thanks, JColvin
  17. Hi @sab, I took a look online and found this Xilinx thread as well as one of Xilinx's User Guides as referenced by zygot that should be of help to you regarding the Worst Negative Slack. The maximum frequency (presuming you are talking about how fast your design will work) will not be related to the worst negative slack; it will depend on how your design has been implemented. The DC and AC Switching Characteristics on each of the respective chip's 7-Series datasheet will give you some maximum speeds; however since your design will inevitably not solely dedicated towards the singular task of getting one clock working at full speed, I would expect something more along the lines from this Xilinx thread. Every design will be different though. Thanks, JColvin
  18. Decanter

    I bricked my CMOD-A7

    Is no-one from Digilent going to address this problem? I have a dead Cmod that's consumed a couple of hours already, with no solution in sight. Others clearly have the same issue. If there is a reliable solution, could you please point us to the answer?
  19. Decanter

    I bricked my CMOD-A7

    hamster, what did you do??? You said "Success!", but didn't list your solution. I'm having the same problem. BTW, I tried what you suggested at https://www.eevblog.com/forum/fpga/unbricking-a-digilent-cmod-a7-fpga-devboard/ and it did not work.
  20. @JColvin Setup is really basic. I connected probe from AWG1 to CH1with BNC adapter. When I trimm capacitor on probe (red circle), edges of square wave doesn't change at all. 0 Ohm on AWG, DC coupling on CH1. Probe is set to x10 (square wave looks like in y first post) but also x1 doesn't work (square wave looks ok but trimming change nothing)
  21. Hey All, We recently posted a new version of WaveForms Live which ads some new features. This blog post lists all the changes in the update.
  22. Hi @thoriam, Could you provide a picture of your physical setup so that we can help better determine what the problem might be? Thanks, JColvin
  23. Hi @Duncan.Wu, Welcome to the Forums!
  24. Hi @sgrobler, I think it's entirely possible to include a timestamp in a log header when starting a session from a connected host. I'll put this on my list of additions & fixes, put some thought into a proper solution and get to work on it. I'll personally message you once I've made the changes (and you'll probably see a blog post about them as well). Regards, AndrewHolzer
  25. Hi kenken, Thank you for sending the VI! I managed to run your VI and ended up at the following conclusions: 1. In your oscilloscope settings, you were setting the vertical range to only 1V, too small to see the entire signal you were generating. Once I set it to a value larger than the peak-to-peak level of your signal (at 5V amplitude, peak-to-peak would be 10V, so I set the vertical range to 20V), the correct signal level appeared. 2. The default buffer size for the oscilloscope input channels which is provided by Analog Discovery 2 is 8192 samples/channel (please see https://reference.digilentinc.com/reference/instrumentation/analog-discovery-2/reference-manual?redirect=1#refnotes:1:note15 for details). At your set sampling rate of 20kSamples/s, this means only 409.6ms, which you obtained. Once I lowered the sampling rate to 10kSamples/s, I managed to see the 500ms you wanted. 3. However, I could not reproduce the spikes on the waveform which you showed in your capture above. Every time I ran the VI, the waveform looks rectangular. Please make sure you connect both terminals of oscilloscope channel 1: the "+" needs to connect to Waveform Generator 1 terminal, while the "-" needs to connect to GND. I've attached the updated VI here, together with some comments next to where I made the updates. Please let me know if you encounter any other issues. Best Regards! function2.vi
  26. Hi @chainastole, Re-reading through this thread and the Xilinx thread, you likely do not need the board files as they exist for "normal" Vivado, because as @AndrewHolzer mentioned My understanding with HLS is that you would be able to create all of your needed IPs in C or C++ rather than in HDL or through pre-made IP cores, so the purpose of creating a Digilent board entry in the VivadoHls_boards.xml is to ensure the correct FPGA (or SoC) is being targeted while creating your design. The rest of the board files add other conveniences (such as per-configuring the design for the on-board DDR memory) but that is a not a required component. Thanks, JColvin
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